NOM du laboratoire

 NOM de l’entreprise : STMicroelectronics Ville et code postal : Crolles 38926 (banlieue Grenoble) NOM du laboratoire : VERIMAG Numéro du laboratoire académique partenaire (si déjà connu) : UMR 5104 DESCRIPTIF du thème de recherche proposé (sans aucun caractère confidentiel): Subject: Data Flow Optimizations on the PSI‐SSA Form Description: Classic data‐flow optimizations in compilers rely on two separate steps: analysis and transformations. Recent research however shows that combining the two into a unified pass is more effective and efficient. The purpose of this research is to extend this unified approach to the compiler code generator optimizations for embedded media processors, by combining: 1. advanced description of machine operators; 2. compiler intermediate representation based on the PSI‐SSA form; and 3. semantic description of machine operators. The PSI‐SSA form is an extension of the classic Static Single Assignment (SSA) form that is used to represent predicated computations. Implementation of the research results will be based on the Open64 compiler framework and on the STMicroelectronics CLI‐JIT compiler [EuroPar'2008]. Target processors for this research are the ST200 VLIW (Lx architecture [ISCA'2000]) processors and the ARM processors. Requirements: The candidate must be familiar with the basics of graph theory and of compiler design. Knowledge of code generator optimizations problems is a plus. The candidate should have working knowledge of Unix systems, C|C++ for implementations, Perl|Python|Tcl for scripting. Conditions: Work located at STMicroelectronics, Grenoble. Supervision by an academic from the VERIMAG laboratory, Grenoble. Date de recrutement : Automne 2008 Adresse email à laquelle le candidat doit répondre:
Contact: [email protected], [email protected]