
Abstract
The constant search for lowering the power consumption of digitals cir-
cuits brings us into the world of sub-threshold circuits. In this world, delays
of logic cells are exponentially dependent of the threshold voltage Vth. With
the constant down-scaling of CMOS technology digital circuits, the varia-
bility of the Vth parameter increases dramaticaly. As a result, the change
of the switching activity of the circuit [13]. Because this activity is directly
linked to the dynamic energy consumption, this latest varies too.
This variability forces designers to take larger constraints on the choice
of the voltage regulator and on the selection of the maximum power that can
be delivered. Thus tools are needed to predict this variability into a circuit
to avoid prohibitive guardbomb. This is what we intent to provide in this
work.
First, analyzing a simple logic cell, we show that the relative variance
σ
µis influenced by two factors of the load. If the load is composed of logic
cells, the first factor is the capacitive coupling between the output node and
the output of the active load. The second factor is the slope of the input
signal as faster cells will have shorter relative time when the input is at its
maximum.
Then, to avoid prohibitively long SPICE simulation we manage to si-
mulate the variability of the dynamic at gate level. To do so, we propose a
new Monte-Carlo simulation flow at cell level which randomizes gate delays
inside the netlist. For this analysis, we use a global coefficient σ
µ. This is rele-
vant as we demonstrate that just a global σ
µunderevaluates dynamic energy
variations. We show that using a global coefficient in the case of sequential
netlist lead to hold violation.