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Embedded Design Handbook
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EDH | 2020.04.25
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Contents
1. Introduction................................................................................................................... 6
1.1. Document Revision History for Embedded Design Handbook........................................ 6
2. First Time Designer's Guide............................................................................................ 8
2.1. FPGAs and Soft-Core Processors.............................................................................. 8
2.2. Embedded System Design...................................................................................... 9
2.3. Embedded Design Resources................................................................................. 11
2.3.1. Intel Embedded Support........................................................................... 11
2.3.2. Intel Embedded Training........................................................................... 11
2.3.3. Intel Embedded Documentation................................................................. 12
2.3.4. Third Party Intellectual Property.................................................................12
2.4. Intel Embedded Glossary...................................................................................... 13
2.5. First Time Designer's Guide Revision History............................................................14
3. Hardware System Design with Intel Quartus Prime and Platform Designer.................. 15
3.1. FPGA Hardware Design......................................................................................... 16
3.1.1. Connecting Your FPGA Design to Your Hardware...........................................17
3.1.2. Connecting Signals to your Platform Designer System...................................17
3.1.3. Constraining Your FPGA-Based Design.........................................................18
3.2. System Design with Platform Designer....................................................................19
3.2.1. Intel System on a Programmable Chip (Platform Designer) Solutions.............. 20
3.2.2. Platform Designer Design..........................................................................22
3.3. Interfacing an External Processor to an Intel FPGA................................................... 23
3.3.1. Configuration Options...............................................................................24
3.3.2. RapidIO Interface.....................................................................................27
3.3.3. PCI Express Interface............................................................................... 29
3.3.4. PCI Interface...........................................................................................31
3.3.5. Serial Protocol Interface (SPI)................................................................... 31
3.3.6. Custom Bridge Interfaces..........................................................................33
3.4. Avalon-MM Byte Ordering......................................................................................35
3.4.1. Endianness............................................................................................. 35
3.4.2. Avalon-MM Interface Ordering................................................................... 36
3.4.3. Nios II Processor Data Accesses.................................................................40
3.4.4. Adapting Processor Masters to be Avalon-MM Compliant................................42
3.4.5. System-Wide Design Recommendations...................................................... 50
3.5. Memory System Design........................................................................................ 52
3.5.1. Memory Types......................................................................................... 52
3.5.2. On-Chip Memory......................................................................................52
3.5.3. External SRAM.........................................................................................55
3.5.4. Flash Memory..........................................................................................56
3.5.5. SDRAM...................................................................................................58
3.5.6. Case Study............................................................................................. 64
3.6. Nios II Hardware Development Tutorial................................................................... 68
3.6.1. Software and Hardware Requirements........................................................ 68
3.6.2. Intel FPGA IP Evaluation Mode................................................................... 69
3.6.3. Nios II Design Example.............................................................................69
3.6.4. Nios II System Development Flow.............................................................. 71
3.6.5. Creating the Design Example.....................................................................75
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3.7. Platform Designer System Design Tutorial............................................................... 89
3.7.1. Software and Hardware Requirements........................................................ 90
3.7.2. Download and Install the Tutorial Design Files..............................................91
3.7.3. Open the Tutorial Project...........................................................................91
3.7.4. Creating Platform Designer Systems...........................................................92
3.7.5. Assemble a Hierarchical System............................................................... 100
3.7.6. Viewing the Memory Tester System in Platform Designer............................. 107
3.7.7. Compiling and Downloading Software to a Development Board..................... 107
3.7.8. Debugging Your Design........................................................................... 109
3.7.9. Verifying Hardware in System Console...................................................... 109
3.7.10. Simulating Custom Components............................................................. 111
3.7.11. View a Diagram of the Completed System................................................117
3.8. Hardware System Design with Intel Quartus Prime and Platform Designer Revision
History...........................................................................................................118
4. Software System Design with a Nios II Processor ......................................................119
4.1. Nios II Command-Line Tools................................................................................ 120
4.1.1. Intel Command-Line Tools for Board Bringup and Diagnostics.......................120
4.1.2. Intel Command-Line Tools for Flash Programming.......................................122
4.1.3. Intel Command-Line Tools for Software Development and Debug..................125
4.1.4. Intel Command-Line Nios II Software Build Tools........................................128
4.1.5. Rebuilding Software from the Command Line............................................. 129
4.1.6. GNU Command-Line Tools....................................................................... 130
4.2. Developing Nios II Software................................................................................ 137
4.2.1. Software Development Cycle................................................................... 138
4.2.2. Software Project Mechanics..................................................................... 142
4.2.3. Developing With the Hardware Abstraction Layer........................................ 161
4.2.4. Linking Applications................................................................................182
4.3. Nios II MPU Usage..............................................................................................184
4.3.1. Requirements........................................................................................ 184
4.3.2. General Usage....................................................................................... 184
4.3.3. Nios II MPU Design Examples...................................................................192
4.4. Profiling Nios II Systems..................................................................................... 201
4.4.1. Requirements........................................................................................ 201
4.4.2. Tools.................................................................................................... 201
4.4.3. Using the GNU Profiler to Measure Code Performance..................................203
4.4.4. Using Performance Counter and Timer Components.................................... 210
4.4.5. Troubleshooting..................................................................................... 216
4.5. Software System Design with a Nios II Processor Revision History............................ 217
5. Nios II Configuration and Booting Solutions............................................................... 219
5.1. Introduction...................................................................................................... 219
5.1.1. Prerequisites......................................................................................... 219
5.2. Nios II Processor Booting Methods........................................................................220
5.2.1. Introduction to Nios II Booting Methods.................................................... 221
5.2.2. Nios II Processor Booting from On-Chip Flash (UFM)................................... 226
5.2.3. Nios II Processor Booting from EPCQ Flash................................................ 254
5.2.4. Nios II Processor Booting from QSPI Flash................................................. 275
5.2.5. Nios II Processor Booting from On-Chip Memory (OCRAM)........................... 305
5.2.6. Nios II Processor Booting from CFI Flash................................................... 313
5.2.7. Summary of Nios II Processor Vector Configurations and BSP Settings.......... 348
5.3. Alternative Nios II Boot Methods.......................................................................... 351
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5.3.1. Assumptions About the Reader................................................................351
5.3.2. Implementing a Custom Boot Copier........................................................351
5.3.3. Default Nios II Boot Copier..................................................................... 352
5.3.4. Advanced Boot Copier Example............................................................... 354
5.3.5. Implementing the Advanced Boot Copier Example..................................... 360
5.3.6. Small Boot Copier Example.....................................................................368
5.3.7. Implementing the Small Boot Copier Example........................................... 369
5.3.8. Debugging Boot Copiers.........................................................................374
5.3.9. Externally Controlling the Nios II Boot Process.......................................... 375
5.4. Boot Time Performance Analysis...........................................................................381
5.4.1. Boot Time Performance Analysis Design Example........................................381
5.4.2. Boot Time Measurement Strategy.............................................................382
5.4.3. Reducing Nios II Boot Time in Intel MAX 10 FPGA Design.............................383
5.4.4. Boot Time Performance and Estimation..................................................... 386
5.5. Nios II Configuration and Booting Solutions Revision History.................................... 390
6. Nios II Debug, Verification, and Simulation ............................................................... 391
6.1. Software Debugging Options................................................................................392
6.2. Debugging Nios II Designs.................................................................................. 394
6.2.1. Debuggers............................................................................................ 394
6.2.2. Run-Time Analysis Debug Techniques........................................................403
6.2.3. Using the Debug Code from Intel MAX 10 On-Chip Flash - User Flash
Memory (UFM).......................................................................................408
6.3. Verification and Board Bring-Up........................................................................... 417
6.3.1. Verification Methods............................................................................... 417
6.3.2. Board Bring-up...................................................................................... 422
6.3.3. System Verification.................................................................................428
6.4. Additional Embedded Design Considerations.......................................................... 432
6.4.1. JTAG Signal Integrity.............................................................................. 432
6.4.2. Memory Space For System Prototyping..................................................... 432
6.5. Simulating Nios II Embedded Processor Designs.....................................................433
6.5.1. Before You Begin....................................................................................433
6.5.2. Setting Up and Generating Your Simulation Environment in Platform Designer 434
6.5.3. Creating the Nios II Software...................................................................435
6.5.4. Running Simulation in the ModelSim Simulator Using Nios II SBT for Eclipse.. 437
6.5.5. Running Simulation in the ModelSim Simulator Using Command Line............ 437
6.6. Nios II Debug, Verification, and Simulation Revision History.....................................439
7. Optimizing Nios II Based Systems and Software........................................................ 440
7.1. Hardware Acceleration and Coprocessing...............................................................441
7.1.1. Hardware Acceleration............................................................................ 441
7.1.2. Coprocessing......................................................................................... 450
7.2. Software Application Optimization........................................................................ 457
7.2.1. Performance Tuning Background.............................................................. 457
7.2.2. Speeding Up System Processing Tasks...................................................... 457
7.2.3. Accelerating Interrupt Service Routines..................................................... 461
7.2.4. Reducing Code Size................................................................................ 462
7.3. Memory Optimization..........................................................................................464
7.3.1. Isolate Critical Memory Connections..........................................................464
7.3.2. Match Master and Slave Data Width..........................................................464
7.3.3. Use Separate Memories to Exploit Concurrency.......................................... 464
7.3.4. Understand the Nios II Instruction Master Address Space............................ 465
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7.3.5. Test Memory..........................................................................................465
7.4. Accelerating Nios II Networking Applications ......................................................... 466
7.4.1. Downloading the Ethernet Acceleration Design Example.............................. 466
7.4.2. The Structure of Networking Applications.................................................. 466
7.4.3. The User Application...............................................................................468
7.4.4. Structure of the NicheStack Networking Stack............................................472
7.4.5. Ethernet Device..................................................................................... 475
7.4.6. Benchmarking Setup, Results, and Analysis............................................... 477
7.4.7. Nios II Test Hardware and Test Results......................................................480
7.5. Using Tightly Coupled Memory with the Nios II Processor Tutorial............................. 481
7.5.1. Reasons for Using Tightly Coupled Memory................................................ 481
7.5.2. Tradeoffs...............................................................................................482
7.5.3. Guidelines for Using Tightly Coupled Memory............................................. 482
7.5.4. Tightly Coupled Memory Interface............................................................ 484
7.5.5. Building a Nios II System with Tightly Coupled Memory...............................485
7.5.6. Generate the Platform Designer System.................................................... 490
7.5.7. Run the Tightly Coupled Memories Examples from the Nios II Command....... 490
7.5.8. Program and Run the Tightly Coupled Memory Project.................................492
7.5.9. Understanding the Tcl Scripts...................................................................493
7.6. Optimizing Nios II Based Systems and Software Revision History..............................497
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