AAP - Mini-project - Elyes & Alae - Presentation

FPGA Development:
NIOS II DE2-115
Simulation with CPUlator
By: -Alae Bouchiba
-Elyes Khechine

Nios II Processor
01The World's Most Versatile Embedded Processor

Nios II Architecture
Nios II is a successor to Altera's first configurable 16-bit embedded
processor Nios, introduced in 2000.
It is a 32-bit embedded processor architecture designed specifically
for the Alterafamily of field-programmable gate array (FPGA)
integrated circuits. It’s a RISC type of architecture.
Nios II incorporates many enhancements over the original Nios
architecture, making it more suitable for a wider range of embedded
computing applications, fromdigital signal processing (DSP) to
system-control.
The Nios II processor, the world's most versatile processor, according
to Gartner Research, is the most widely used soft processor in the
FPGA industry. This processor delivers unprecedented flexibility for
cost-sensitive, real-time, safety-critical (DO-254), and applications
processing needs. It supports all Intel® FPGA and SoC families.

Optimized for highest
performance, optional
memory management unit
(MMU), or memory
protection unit (MPU)
Designed for smallest
possible logic utilization of
FPGAs. This is especially
efficient for low-cost
Cyclone II FPGA applications.
Designed to maintain a
balance between
performance, size and cost
Nios II/f (fast) Nios II/e (economy) Nios II/s (standard)
Nios II Processor Family
With over 200 DMIPs of performance in designs targeting the Stratix® II family of high-performance FPGAs, the Nios II
family delivers mainstream performance to address a broad range of embedded applications.It consists of three
members –fast (II/f), economy (II/e) and standard (II/s) –each optimized for a specific price and performance range. All
three cores use the same instruction set architecture (ISA) and are 100% binary code compatible.

Nios II Processor Features
Multiply and barrel shifter.
Single-Cycle Hardware
Up to 256 custom instructions and
unlimited hardware accelerators.
Custom Instructions
Up to 32 interrupts per
controller.
External Vector Interrupt
Controller
Configurable from 512 bytes to
64 KB.
Separate Instruction
and Data Caches
Up to six-stage pipeline to achieve
maximum DMIPS (Dhrystone 2.1
benchmark) per MHz.
Achieve Maximum DMIPS
Access up to 4 GB of
external address space
Optional Tightly-Coupled
Memory for Instructions
and Data
Advanced Exception
Support