Data read circuit for semiconductor storage device

iiililiili^
EuroPean Patent Office
@
^-S
Office europeen des brevets
EUROPEAN
(12)
(fi) Publication number: 0 4 0 8
031
B1
PATENT S P E C I F I C A T I O N
@ Date of publication of patent specification :
12.10.94 Bulletin 94/41
@ Int. CI.5 : G11C 7 / 0 0
(21) Application number: 90113338.9
(22) Date of filing : 12.07.90
(54) Data read circuit for semiconductor storage device.
(§) Priority: 12.07.89 JP 179816/89
(43) Date of publication of application :
16.01.91 Bulletin 91/03
@ Publication of the grant of the patent :
12.10.94 Bulletin 94/41
@ Designated Contracting States :
DE FR GB
(56) References cited :
EP-A- 0 235 889
EP-A- 0 313 748
US-A- 4 239 994
IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, vol. 30, 27 February
1987,NEW YORK US pages 264 - 265; OHTANI
ET AL: 'A 25ns 1Mb CMOS SRAM' and page
420
(72) Inventor : Hoshi, Satoru
4-7-1-412, Tote,
Saiwai-ku
Kawasaki-shi, Kanagawa-ken (JP)
Inventor : Kawaguchi, Takayuki
3-16-5-106, Namamugi,
Tsurumi-ku
Yokohama-shi, Kanagawa-ken (JP)
Inventor : Masuda, Masami
5, Murato-So,
594, Kamihirama,
Nakahara-ku
Kawasaki-shi, Kanagawa-ken (JP)
(74) Representative : Lehn, Werner, Dipl.-lng. et al
Hoffmann, Eitle & Partner,
Patentanwalte,
Postfach 81 04 20
D-81904 Miinchen (DE)
@) Proprietor : KABUSHIKI KAISHA TOSHIBA
72, Horikawa-cho
Saiwai-ku
Kawasaki-shi Kanagawa-ken 210 (JP)
Proprietor : TOSHIBA MICRO-ELECTRONICS
CORPORATION
25-1, Ekimae-hon-cho
Kawasaki-ku Kawasaki-shi Kanagawa-ken
^
(JP)
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CO
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Note : Within nine months from the publication of the mention of the grant of the European patent, any
person may give notice to the European Patent Office of opposition to the European patent granted.
Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been
filed until the opposition fee has been paid (Art. 99(1) European patent convention).
Jouve, 18, rue Saint-Denis, 75001 PARIS
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EP 0 408 031 B1
Description
FIELD OF THE INVENTION
The present invention relates to a data read circuit for a semiconductor storage device, and more
particularly to a data read circuit for a semiconductor
storage device of the type that data lines are equalized.
BACKGROUND OF THE INVENTION
Fig. 1 is a block diagram of a data output circuit
for a semiconductor storage device incorporated
herein to disclose the background art of this invention.
As seen from Fig. 1, data are read from a memory cell
11 via bit lines N1 and N2. The data on the bit lines
N1 and N2 are equalized by a bit line equalizing transistor Tr1. The bit line N1 is connected to a data line
N3 via a column selecting transistor Tr11. The bit line
N2 is connected to a data line N4 via a column selecting transistor Tr1 2. The transistors Tr11 and Tr12 are
controlled byacontrol line N11 to turn on or off so that
the bit lines N1 and N2 are connected to or disconnected from the data lines N3 and N4, respectively.
To the control line N1 1, there is applied a decoded signal of an address signal. The data lines N3 and N4 are
equalized by an input/output line equalizing transistor
Tr2. The input/output lines N3 and N4 are connected
to a first sense amplifier (differential amplifier) 21 . All
sense amplifiers in the following description are
made of a differential amplifier whose data relationship is shown in Fig. 2. The outputs from the first
sense amplifier 21 are delivered onto first sense amplifier output data lines N5 and N6. Between the first
sense amplifier output data lines N5 and N6, there is
connected a data line equalizing transistor Tr3. The
outputs from the first sense amplifier 21 are equalized by the transistor Tr3. The data on the data lines
N5 and N6 are inputted to a second sense amplifier
22. The outputs from the amplifier 22 are delivered to
second sense amplifier output data lines N7 and N8.
Between the data lines N5 and N7, there is connected
an input/output shorting transistor Tr5. Between the
data lines N6 and N8, there is connected an input/output shorting transistor Tr6. The transistors Tr5 and
Tr6 operate to short the inputs and outputs of the second sense amplifier 22. The second sense amplifier
output data lines N7 and N8 are connected to an output buffer amplifier 25 whose particular configuration
is shown in Fig. 3. An output equalizing transistor Tr4
is connected between the data lines N7 and N8 on the
input side of the output buffer amplifier 25, to equalize
the data on the lines N7 and N8. There are connected
to the output side of the output buffer amplifier 25,
output buffer transistors Tr21 and Tr22. Data is outputted from the interconnection node of the transistors Tr21 and Tr22.
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An equalizing pulse d>eq is supplied from an
equalizing pulse generator circuit 40 to the gates of
the transistors Tr1 to Tr6. The equalizing pulse generator circuit 40 is controlled by a detector circuit 30
which detects a change in address signal. The detector circuit 30 is constructed of input transition detector
circuits 31, 32, ... to which applied are addresses IN1,
IN2
respectively. Each of the input transition detector circuits 31, 32, ... has a circuit configuration
such as shown in Fig. 4. Signal waveforms at various
nodes of each of the circuits 31, 32, ... are shown in
Fig. 5. The relationship between the detector circuit
30 and equalizing pulse generator circuit 40 is shown
in Fig. 6. The number of inverters IV in the circuit 40
depends upon the capacitance of a load connected to
this circuit.
Next, the operation of the circuit shown in Fig. 1
will be described with reference to the timing chart
shown in Figs. 7 and 8 the difference between which
is the width of a pulse shown in Figs. 7(b) and 8(b).
Referring to Figs. 7 and 8, Figs. 7(a) and 8(b) represent the transition state of address inputs IN1 and
IN2, Figs. 7(b) and 8(b) represent the equalizing pulse
<3>eq> Figs. 7(c) and 8(c) represent the state of the first
sense amplifier output data lines N5 and N6, Figs.
7(d) and 8(d) represent the state of the second sense
amplifier output data lines N7 and N8, and Figs. 7(e)
and 8(e) represent the state of an output (N9).
At time t1, addresses IN1, IN2, ... transit. The intransition
detector circuits 31 , 32, detect address
put
transition. The detected signal is supplied to the
equalizing pulse generator circuit 40 which accordingly outputs the equalizing pulse d>eq as shown in Fig.
2(b) at time t2 in synchronization with the address
change. This equalizing pulse <Peq causes the transistors Tr1 to Tr6 to turn on during the period from time
t2 to t3. Namely, the transistor Tr1 is turned on to
short the bit lines N1 and N2, the transistor Tr2 is
turned on to short the data lines N3 and N4, the transistor Tr3 is turned on to short the data lines N5 and
N6, and the transistor Tr4 is turned on to short the
data lines N7 and N8. Accordingly, the pairs of data
lines are made the same potential because of shortcircuits. At the same time, the input/output shorting
transistors Tr5 and Tr6 turn on to short the inputs and
outputs of the second sense amplifier 22. Accordingly , the potentials of the outputs of the first and second
sense amplifiers 21 and 22 take a certain potential
Veq determined by the characteristics of transistors
constituting the amplifiers, as shown in Figs. 7(c) and
7(d). When the equalizing pulse <Peq falls down at time
t3, the transistors Tr1 to Tr6 turn off. The data from
the new memory cell selected by the new address are
read via the bit lines N1 and N2, and column selecting
transistors Tr11 and Tr12, to the data lines N3 and N4.
The data are supplied via the first and second sense
amplifiers 21 and 23, and output buffer amplifier 25
to the output buffer transistors Tr21 and Tr22. An out-
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EP 0 408 031 B1
put as shown in Fig. 7(e) is obtained at the output
node N9.
With the above operation, data can be read from
a memory cell without adversely affected by the contents of cell data at the preceding address.
In the above-described data output device, the
equalizing pulse performs an equalization function as
well as a function to inhibit data on the data lines to
be transferred during the equalization operation. In
order to read data from a memory cell at high speed,
it is necessary to speed up the fall time of the equalizing pulse ©eq- It is necessary therefore (1) to make
the pulse width of the equalizing pulse narrow or (2)
to shorten the period from when an address transition
is detected to when the equalizing pulse <Peq rises.
However, if a sufficient equalizing effect is desired by
using the equalizing pulse d>eq having a short pulse
width, it becomes necessary to obtain a high conductance gm of the transistors Tr1 to Tr6, which generally
results in an increase of the gate width of a MOS transistor and hence in an increase of the gate capacitance. The increase of the gate capacitance results in
an increase of the load capacitance C(<Peq) connected
to the equalizing pulse generating circuit 40. However
in general, the number of stages of logical circuits
(five stages of inverters IV in the case of Fig. 6) of the
equalizing pulse generator circuit 40 is designed as
small as possible to the extent that its load having the
capacitance C(<Peq) can be driven without delay and
the equalizing pulse d>eq can rise and fall at high
speed. Because of this, the number of stages of logical circuits cannot be reduced. If the number of stages were reduced, the establishment of a pulse could
be quickened but the load could not be driven sufficiently.
Apart from the above, there is another problem
associated with the operation of the transistors Tr5
and Tr6 for shorting the inputs and outputs of the second sense amplifier 22. Specifically, upon establishment of the equalizing pulse <Peq> the transistors Tr5
and Tr6 shortthe inputs and inverted outputs of active
elements of the second sense amplifier 22 so that the
active elements enter a negative feedback operation.
Therefore potentials at the inputs and outputs oscillate and converge to the potential Veq. If the width of
the equalizing pulse d>eq is made shorter, this pulse
may start terminating before the oscillation converges sufficiently. In this case, as shown in Figs. 8(c) and
8(d), convergence of oscillation of the potentials at
the data signal lines N5 and N6 is not satisfactory at
time t3 when the equalizing pulse d>eq starts falling
down. The second sense amplifier 22 therefore amplifies an insignificant potential difference between
the data signal lines N5 and N6, resulting in a considerable read time delay. As seen from the foregoing
description, it is necessary to set the width of the
equalizing pulse <Peq to have a sufficient margin. The
need to broaden the pulse width has been an obstacle
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against high speed data read.
As described above, the equalizing method for a
data output device according to the background art
does not provide stable data read at high speed,
which has been a bottleneck for high system performance, especially for multi-bit systems having a number of data lines.
EP-A-0 235 889 discloses a differential sense
amplifier whose pair of input lines is equalised by a
first switch, whose pair of output lines is equalised by
a second switch, and whose said switches are operated by different equalising pulses (<P1,<I>2).
US-A-4,239,994 discloses a sense amplifier havbetween
the input line (30) and the output line (32)
ing
feedback
circuit
a
including a feedback switch (TG1)
operated by a pre-charge pulse for precharging, ie.
offsetting the amplifier's input to an operation value
enabling quick response.
Above EP-A-0 235 889 combined with above USA-4,239,994 would lead to provide the sense amplifier as known from EP-A-0 235 889 with the feedback
circuit as known from US-A-4,239,994, but would
leave open if one - and if so - which one of the equalising pulses (0>1,0>2) according to EP-A-0 235 889
could or should be used to operate said feedback
switch.
SUMMARY OF THE INVENTION
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The present invention has been made in consideration of the above problems and aims at providing
a data read circuit for a semiconductor storage device
capable of shortening the time required for equalizing
the data lines during a data read cycle, and realizing
high speed access.
This problem is solved as indicated in claims 1
and 7.
A first equalizing pulse is applied to second
switching means for equalizing the outputs of a sense
amplifier having complementary data lines for receiving input data, and is applied to third switching means
for equalizing the input and output of the sense amplifier. A second equalizing pulse establishing earlier
than the first equalizing pulse is applied from second
equalizing pulse generator means to first switching
means connecting said input data lines. As a result,
the output state of the sense amplifier is substantially
established in accordance with the equalizing results
obtained by first switching means. Thereafter, in accordance with the first equalizing pulse, the equalizing operation is carried out stably at high speed.
As stated above, according to the present invention, it is possible to realize an establishment of an
equalizing pulse at an earlier timing and a setting of
short pulse width. Accordingly, the terminating timing
of the equalizing pulse can be quickened, and high
speed reading of data from a memory cell can be realized without considerably modifying a conventional
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EP 0 408 031 B1
system.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 shows a data read circuit according to the
background art;
Fig. 2 illustrates the input/output relationship of
the sense amplifier;
Figs. 3 and 4 show the configuration of the output
buffer and address input transition detector circuit, respectively;
Fig. 5 is a timing chart illustrating the operation
of the circuit shown in Fig. 4;
Fig. 6 shows the configuration of the address input transition detector circuit and equalizing
pulse generator circuit;
Figs. 7 and 8 are timing charts illustrating the operation of the circuit shown in Fig. 1;
Fig. 9 shows an embodiment of this invention;
Fig. 10 is a timing chart illustrating the operation
of the embodiment circuit shown in Fig. 9;
Fig. 11 shows examples of the address input transition detector circuit, first and second equalizing
pulse generator circuits;
Fig. 12 shows another embodiment of this invention; and
Figs. 13 and 14 show modifications of the embodiment shown in Figs. 9 and 12, respectively.
DESCRIPTION OF THE PREFERRED
EMBODIMENTS
The embodiments of this invention will be described with reference to the accompanying drawings.
Fig. 9 is a block diagram showing the data output
device according to an embodiment of this invention.
In Fig. 9, like elements to those shown in Fig. 1 are
represented by using identical reference numerals.
As seen from Fig. 11, a first equalizing pulse generator circuit 41 shown in Fig. 9 has the same structure
as that of the equalizing pulse generator circuit 40
shown in Fig. 1. A load capacitance C(<Peq) is coupled
to this circuit 41 . The circuit 41 generates a first equalizing pulse <Peq in accordance with the address
change detection signal from input transition detector
circuits 31, 32,
This equalizing pulse is applied to
transistors Tr1 , Tr2, Tr5, Tr6, and Tr4. Asecond equalizing pulse generator circuit 42 generates a second
equalizing pulse <Peq' in accordance with the address
change detection signal from the input transition detector circuits 31, 32,
This equalizing pulse is <Peq'
is applied to an data line equalizing transistor Tr3.
This circuit 42 is constructed as shown in Fig. 11.
Since the load capacitance C (<3>eq') connected to the
circuit 42 is smaller than the load capacitance C (<Peq)
connected to the circuit 41 , the number of stages of
logical circuits (inverter IV) of the circuit 42 is "3"
which is smaller than "5" of the circuit 41. The other
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structure is similar to that shown in Fig. 1.
The operation of the data output device constructed as above will be described with reference to
the timing chart shown in Fig. 10. Fig. 10(a) represents the state of change in address inputs IN1,
IN2
Fig. 10(b) represents the equalizing pulse
<3>eq>
' Fig. 10(c) represents the equalizing pulse <Peq,
Fig. 10(d) represents the state of first sense amplifier
output data lines N5and N6, Fig. 10(e) represents the
state of second sense amplifier output data lines N7
and N8, and Fig. 10(f) represents the state of an output.
As shown in Fig. 9, the equalizing pulse <Peq from
the first equalizing pulse generator circuit 41 is supplied to the gates of the transistors Tr1 , Tr2, Tr4, Tr5,
and Tr6. The equalizing pulse <Peq' from the second
equalizing pulse generator 42 is supplied only to the
gate of the input/output equalizing transistor Tr3.
Consider now the load capacitance C(<Peq) associated
with the equalizing pulse <Peq and the load capacitance C(<Peq') associated with the equalizing pulse
<3>eq'- Obviously, the load capacitance C(<Peq') connected to a lesser number of gates is smaller than the
load capacitance C(<Peq), i.e., C(<Peq) > C(<Peq')- It is
therefore possible to construct the second equalizing
pulse generator 42 generating the equalizing pulse
<3>eq'with a lesser stage number of logical circuits than
that of the first equalizing pulse generator circuit 41
generating the equalizing pulse <Peq- Accordingly the
equalizing pulse <Peq' can be established at an earlier
timing than the equalizing pulse <PeqAs shown in Fig. 10(a), when an address supplied
from the address IN1, IN2, ... changes, this change is
detected by the input transition detector circuits 31,
32, ... at time t1. The equalizing pulse <Peq' is outputted from the second equalizing pulse generator circuit
42 at time t2. The equalizing pulse <Peq is thereafter
outputted from the first equalizing pulse generator
circuit 41 at time t3. Such operation will be detailed
hereinafter. As shown in Figs. 10(b) and 10(c), the
equalizing pulse <Peq' is established at an earlier timing than the equalizing pulse <Peq- Accordingly, only
the input/output equalizing transistor Tr3 with its gate
being supplied with the equalizing pulse <Peq' turns on
earlier than the other transistors Tr1 , Tr2, Tr4 to Tr6.
The data lines N5and N6 at the output side of the first
sense amplifier 21 are shorted and the potential on
the data lines become near the equalizing potential
Veqi specific to the first sense amplifier 21 as shown
in Fig. 10(d). At this time t2, the second sense amplifier 22 still remains at its active state. Accordingly, as
the input potential changes toward the potential Veqi,
the output of the second sense amplifier 22 under the
active state changes toward a potential Veq2 corresponding to the potential Veqi. The potentials Veqi and
Veq2 take the median values between the high level
and low level outputs of the first and second sense
amplifiers 21 and 22 under the normal active state,
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EP 0 408 031 B1
respectively. The difference between potentials Veqi
and Veq2 is far smaller than the potential difference
across the source and drain of the input/output shorting transistors Tr5 and Tr6.
Next, as shown in Fig. 10(c), when the equalizing
pulse ©eq is established at time t3, the transistors Tr1 ,
Tr2, Tr4, Tr5 and Tr6 turn on. Short circuits are thereby formed between the bit lines N1 and N2, between
the data lines N3 and N4, between the second sense
amplifier output data lines N7 and N8, and between
the first sense amplifier output data line N7 and the
second sense amplifier output data line N8. Until this
time, the output potential of the first sense amplifier
21 has been changing toward the potential Veqi, and
the output potential of the second sense amplifier 22
receiving the potential Veqi of the second sense amplifier 22 receiving the potential Veqi has been changing toward the potential Veq2. Accordingly the potential
differences across the sources and drains of the input/output shorting transistors Tr5 and Tr6 are sufficiently small. As shown in Figs. 10(d) and 10(e), potential oscillation resulting from the negative feedback effects, i.e. the shorting inputs and outputs of
the second sense amplifier 22 is small and can converge in a short time. Therefore, there is less possibility of generating an insignificant potential difference between the data lines. As a result, even if the
width of the equalizing pulse to be outputted from the
first equalizing pulse generator circuit 41 is set short
and the equalizing pulse is terminated at an earlier
timing (time t5), unnecessary oscillation has been
converged almost completely up to this time. Therefore, as shown in Fig. 10(f), it is possible to read data
without delay and prevent delays caused by reading
unnecessary data due to potential oscillation or the
like.
As stated above, according to the embodiment of
this invention, the width of the equalizing pulse <Peq to
be outputted from the first equalizing pulse generator
circuit 41 can be made short so that data can be read
from a memory cell reliably at high speed.
Fig. 12 is a block diagram showing another embodiment of this invention. In Fig. 12, like elements to
those shown in Fig. 9 are represented by identical reference numerals. The differences of the structure
shown in Fig. 12 from that shown in Fig. 9 are as follows. Between the second sense amplifier 22 and
output buffer amplifier 25, there are provided cascaded third and fourth sense amplifiers 23 and 24. In addition, there are provided transistors Tr31 and Tr32
for shorting the input sides of the third and fourth
sense amplifiers 23 and 24, and transistors Tr33,
Tr34, Tr35, and Tr36 for shorting the inputs and outputs of the amplifiers 23 and 24. The equalizing pulse
<3>eq' from the second equalizing pulse generator circuit 42 is used also for shorting the data signal lines
at the input side of the third sense amplifier 23. So
long as the condition that load capacitance C(<Peq') is
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sufficiently smaller than the load capacitance C(<Peq)
is satisfied, the equalizing pulse <Peq', may be supplied to a plurality of gates, with the same advantageous effects as the structure shown in Fig. 9 being
obtained.
Although the number of sense amplifier stages is
five, this may be six or more. In such a case, all sense
amplifiers may be divided into forward and backward
stage blocks, and the equalizing pulse <Peq' from the
second equalizing pulse generator 42 may be added
to the forward stage block and the equalizing pulse
<3>eqfrom the first equalizing pulse generator 41 to the
backward stage block.
Figs. 13 and 14 show another embodiment the
difference of which from the embodiments shown in
Figs. 9 and 12 is that there is provided a transistor
Tr3Afor equalizing the output sides N5 and N6 of the
first sense amplifier 21 , and the gate of this transistor
is supplied with the pulse <Peq from the first equalizing
pulse generator 41 .
Reference signs in the claims are intended for
better understanding and shall not limit the scope.
Claims
1. A data read circuit for a semiconductor storage
device comprising:
a sense amplifier (22) to which is inputted
data of a memory cell (11) selected according to
an address via a pair of complementary first data
lines (N1 to N6) and outputs the inputted and amplified data to a pair of complementary second
data lines (N7, N8);
first switching means (Tr3) for equalizing
said pair of complementary first data lines (N5,
N6) at the input side of said sense amplifier (22)
by connecting said first data lines to each other;
second switching means (Tr4) for equalizsaid
pair of complementary second data lines
ing
(N7, N8) by connecting said second data lines to
each other;
third switching means (Tr5, Tr6) for equalizing by connecting the lines of said pair of first
data lines (N5, N6) at the input side of said sense
amplifier (22) to corresponding ones of said pair
of second data lines (N7, N8);
second equalizing pulse generator means
for
(42)
generating a second equalizing pulse
when
said address is changed and for turn(®eq')
said
first switch means (Tr3) by applying
ing on
said second equalizing pulse to a control terminal
of said first switch means; and
first equalizing pulse generator means
for
(41)
generating a first equalizing pulse (<Peq)
when said address is changed and for turning on
said second and third switching means (Tr4; Tr5,
Tr6) by applying said first equalizing pulse to gate
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EP 0 408 031 B1
terminals of said second and third switching
means;
wherein the load capacitance [C(<Peq')]
connected to an output terminal of said second
equalizing pulse generator means (42) is set
smaller than the load capacitance [C(<Peq)] connected to an output terminal of said first equalizing pulse generating means (41), and
wherein the number of stages of logical circuits constituting said second equalizing pulse
generator means (42) is smaller than the number
of stages of logical circuits constituting said first
equalizing pulse generator means (41), and
whereby said second equalizing pulse (<J>eq') from
said second equalizing pulse generator means
(42) is established earlier than said first equalizing pulse (d>eq) from said first equalizing pulse
generator means (41).
A data read circuit according to claim 1, further
comprising a detector circuit (30) for detecting a
change of said address, whereby
said first and second equalizing pulse generator circuits (41, 42) generate said first and
second equalizing pulses (<Peq> <J>eq') in response
to a signal outputted from said detector circuit
(30).
A data read circuit according to claim 1, further
comprising:
an output buffer (25) for receiving signals
from said pair of second data lines (N7, N8); and
output buffer transistors including serially
connected first and second transistors (Tr21,
Tr22) for receiving a pair of complementary outputs from said output buffer (25), the gates of
said first and second transistors being applied
with one and the other output of said pair of complementary outputs, and the data in a memory
cell (11) corresponding to said address being outputted from an interconnection point (N9) between said first and second transistors.
A data read circuit according to claim 1, wherein
said complementary pair of first data lines (N1 to
N6) has another sense amplifier (21) at the intermediate thereof, said pair of data lines (N5, N6)
between said other sense amplifier (21) and said
sense amplifier (22) are connected together by
said first switching means (Tr3), fourth switching
means (Tr2) is connected between said pair of
first data lines (N3, N4) at the input side of said
other sense amplifier (21) for equalizing by connecting the lines of said pair of first data lines (N3,
N4) to each other, and a control terminal of said
fourth switching means (Tr2) and an output terminal of said first equalizing pulse generator (41)
means are connected together.
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5. A data read circuit according to claim 4, wherein
fifth switching means (Tr11, Tr12) is serially connected between said other sense amplifier (21)
and said memory cell (11) at the corresponding
ones of said complementary first data lines (N1
to N6), sixth switching means (Tr1) is connected
between the lines of said pair of first data lines at
the input side of said memory cell (11) for equalizing by connecting said pair of first data lines
(N1, N2) to each other, and a control terminal of
said sixth switching means (Tr1) is connected to
the output terminal of said first equalizing pulse
generator means (41).
6. A data read circuit according to claim 1, wherein
further switching means (Tr3A) is connected between said pair of first data lines (N5, N6) in parallel with said first switching means (Tr3), and
said first equalizing pulse (<Peq) is applied to a
control terminal of said seventh switching means
(Tr3A).
7. A data read circuit for a semiconductor storage
device comprising:
a plurality of sense amplifiers (22, 23, 24)
sequentially and serially connected by a complementary pair of first data lines (N10 to N13), a
complementary pair of second data lines (N1 to
N6) being connected to a first stage sense amplifier (22) of said plurality of sense amplifiers, and
data of a memory cell (11) selected according to
an address being outputted onto said complementary pair of second data lines;
first switching means (Tr3) for equalizing
said complementary pair of second data lines
(N5, N6) at the input side of said first sense amplifier (22) by connecting said second data lines
to each other;
second switching means (Tr31, Tr32) for
equalizing said complementary pair of first data
lines (N10, N11; N12, N13) by connecting said
first data lines to each other;
third switching means (Tr5, Tr6, Tr33 to
for
Tr36)
equalizing by connecting the lines of
said complementary pair of data lines at the input
side of each of said plurality of sense amplifiers
(22, 23, 24) to corresponding ones of said complementary pair of data lines at the output side of
each of said plurality of sense amplifiers
fourth switching means (Tr4) for equalizing
a complementary pair of third data lines (N7, N8)
as the output terminals of the last stage sense
amplifier (24) of said plurality of sense amplifiers
(22 to 24) by connecting the lines of said complementary pair of third data lines to each other;
second equalizing pulse generator means
for
(42)
generating a second equalizing pulse
when
said address is changed and forturn(<3>eq')
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EP 0 408 031 B1
ing on said first switch means (Tr3) and at least
the first stage second switch means (Tr31 ) of said
second switching means (Tr31 , Tr32) by applying
said second equalizing pulse to control terminals
of said first switch means (Tr3) and said at least
the first stage second switch means (Tr31); and
first equalizing pulse generator means
for
(41)
generating a first equalizing pulse (<Peq)
when said address is changed and for turning on
said second stage second switch means (Tr32) of
said second switching means (Tr31 , Tr32) not applied with said second equalizing pulse (<J>eq')>
said third switching means (Tr5, Tr6, Tr33 to Tr36)
by applying said first equalizing pulse (<Peq) and
said fourth switching means (Tr4) to control terminals of said second stage second switch
means (Tr32), said third switching means (Tr5,
Tr6, Tr33 to Tr36) and said fourth switching
means (Tr4);
wherein the load capacitance [C(<Peq')]
connected to an output terminal of said second
equalizing pulse generator means (42) is set
smaller than the load capacitance [C(<Peq)] connected to an output terminal of said first equalizing pulse generating means (41), and
wherein the number of stages of logical circuits constituting said second equalizing pulse
generator means (42) is smaller than the number
of stages of logical circuits constituting said first
equalizing pulse generator means (41), and
whereby said second equalizing pulse (<J>eq') from
said second equalizing pulse generator means
(42) is established earlier than said first equalizing pulse (d>eq) from said first equalizing pulse
ge nerator mea ns (4 1).
8.
9.
A data read circuit according to claim 7, further
comprising a detector circuit (30) for detecting a
change of said address, whereby
said first and second equalizing pulse generator circuits (41, 42) generate said first and
second equalizing pulses (<Peq> <J>eq') in response
to a signal from said detector circuit (30).
A data read circuit according to claim 7, further
comprising:
an output buffer (25) for receiving signals
from said pair of third data lines (N7, N8); and
output buffer transistors including serially
connected first and second transistors (Tr21,
Tr22) for receiving a complementary pair of outputs from said output buffer (25), the gates of
said first and second transistors being applied
with one and the other output of said complementary pair of outputs, and the data in a memory cell
(11) corresponding to said address being outputted from an interconnection point (N9) between
said first and second transistors.
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25
30
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40
10. A data read circuit according to claim 6, wherein
said complementary pair of second data lines (N1
to N6) has another sense amplifier (21) at the intermediate thereof, said pair of data lines (N5,
N6) between said other sense amplifier (21) and
said sense amplifier (22) are connected together
by said first switching means (Tr3), fifth switching
means (Tr2) is connected between said pair of
second data lines (N3, N4) at the input side of
said other sense amplifier (21) for equalizing by
connecting the lines of said pair of second data
lines (N3, N4) to each other, and a control terminal of said fifth switching means (Tr2) and an output terminal of said first equalizing pulse generator means (41) are connected together.
11. Adata read circuit according to claim 10, wherein
sixth switching means (Tr11, Tr12) is serially connected between said other sense amplifier (21)
and said memory cell (11) at the corresponding
ones of said complementary second data lines
(N1, N3; N2, N4), seventh switching means (Tr1)
is connected between the lines of said pair of second data lines at the input side of said memory
cell (11) for equalizing by connecting said pair of
second data lines (N1, N2) to each other, and a
control terminal of said seventh switching means
(Tr1) is connected to the output terminal of said
first equalizing pulse generator means (41).
12. Adata read circuit according to claim 7, wherein
further switching means (Tr3A) is connected between said pair of second data lines (N5, N6) in
parallel with said first switching means (Tr3), and
said first equalizing pulse (<Peq) is applied to a
control terminal of said seventh switching means
(Tr3A).
Patentanspruche
1.
45
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7
12
Datenleseschaltung fur eine Halbleiterspeichereinrichtung, umfassend:
einen Leseverstarker (22), dem Daten einer
Speichzelle (11) gewahlt gemali einer Adresse
uberein Paarvon komplementaren ersten Datenleitungen (N1 bis N6) eingegeben werden und
der die eingegebenen und verstarkten Daten an
ein Paar von komplementaren zweiten Datenleitungen (N7, N8) ausgibt;
eine erste Schalteinrichtung (Tr3) zum Angleichen des Paars von komplementaren ersten Datenleitungen (N5, N6) an der Eingangsseite des
Leseverstarkers (22) durch Verbinden der ersten
Datenleitungen miteinander;
eine zweite Schalteinrichtung (Tr4) zum Angleichen des Paars von komplementaren zweiten
Datenleitungen (N7, N8) durch Verbinden der
13
EP 0 408 031 B1
zweiten Datenleitungen miteinander;
eine dritte Schalteinrichtung (Tr5, Tr6) zum Angleichen durch Verbinden des Paars von ersten
Datenleitungen (N5, N6) an der Eingangsseite
des Leseverstarkers (22) an entsprechende des
Paars von zweiten Datenleitungen (N7, N8);
eine zweite Angleichungsimpuls-Erzeugungseinrichtung (42) zum Erzeugen eines zweiten Angleichungsimpulses (<>
| eq')> wenn die Adresse geandert wird und zum Einschalten der ersten
Schalteinrichtung (Tr3) durch Anlegen des zweiten Angleichungsimpulses an einen Steueranschluli der ersten Schalteinrichtung; und
eine erste Angleichungsimpuls-Erzeugungseinrichtung (41) zum Erzeugen eines ersten Angleichungsimpulses (<|>eq), wenn die Adresse geandert wird und zum Einschalten der zweiten und
dritten Schalteinrichtung (Tr4; Tr5, Tr6) durch Anlegen des ersten Angleichungsimpulses an GateAnschlusse der zweiten und dritten Schalteinrichtung;
wobei die mit einem Ausgangsanschluli der zweiten Angleichungsimpuls-Erzeugungseinrichtung
(42) verbundene Lastkapazitat [C(<|>eq')] kleiner
eingestellt wird als die mit einem Ausgangsanschluli der ersten Angleichungsimpuls-Ezeugungseinrichtung (41) verbundene Lastkapazitat
[C(4>aq)]; und
wobei die Anzahl von Stufen von Logikschaltungen, die die zweite Angleichungsimpuls-Erzeugungseinrichtung (42) bilden, kleiner ist als die Anzahl von Stufen von Logikschaltungen, die die erste
Angleichungsimpuls-Erzeugungsschaltung (41)
bilden, und wobei derzweite Angleichungsimpuls
(<|>eq') von der zweiten Angleichungsimpuls-Erzeugungseinrichtung (42) fruher eingerichtet
wird, als der erste Angleichungsimpuls (<>
| eq) von
der ersten Angleichungsimpuls-Erzeugungseinrichtung (42).
2.
3.
Datenleseschaltung nach Anspruch 1,fernerumfassend eine Detektorschaltung (30) zum Erfassen einer Anderung der Adresse, wobei
die ersten und zweiten Angleichungsimpuls-Erzeugungsschaltungen (41, 42) die ersten und
zweiten Angleichungsimpulse (§eq, <|>eq') im Ansprechen auf ein von der Detektorschaltung (30)
ausgegebenes Signal erzeugen.
Datenleseschaltumg nach Anspruch 1, ferner
umfassend:
einen Ausgangspuffer (25) zum Empfang von Signalen von dem Paar von zweiten Datenleitungen (N7, N8); und
Ausgangspuffertransistoren mit in Reihe geschalteten ersten und zweiten Transistoren
(Tr21, Tr22) zum Empfang eines Paars von komplementaren Ausgangen von dem Ausgangspuf-
fer (25), wobei an die Gates der ersten und zweiten Transistoren einer und der andere Ausgang
des Paars von komplementaren Ausgangen angelegt wird, und wobei die Daten in einer Speicherzelle (11) entsprechend der Adresse von einem Verbindungsknotenpunkt (N9) zwischen den
ersten und zweiten Transistoren ausgegeben
werden.
5
10
4.
Datenleseschaltung nach Anspruch 1, wobei das
komplementare Paar von ersten Datenleitungen
(N1 bis N6) einen anderen Leseverstarker (21) an
einer zwischen ihnen liegenden Stelle aufweist,
das Paar von Datenleitungen (N5, N6) zwischen
dem anderen Leseverstarker (21) und dem Leseverstarker (22) durch die erste Schalteinrichtung
(Tr3) zusammengeschaltet sind, eine vierte
Schalteinrichtung (Tr2) zwischen das Paar von
ersten Datenleitungen (N3, N4) auf der Eingangsseite des anderen Leseverstarkers (21)
zum Angleichen durch Zusammenschalten der
Leitungen des Paars von ersten Datenleitungen
(N3, N4) geschaltet ist, und ein Steueranschluli
der vierten Schalteinrichtung (Tr2) und ein Ausgangsanschluli der ersten AngleichungsimpulsErzeugungseinrichtung (41) zusammengeschaltet sind.
5.
Datenleseschaltung nach Anspruch 4, wobei einefunfte Schalteinrichtung (Tr11, Tr1 2) zwischen
dem anderen Leseverstarker (21) und die Speicherzelle (11) an den entsprechenden der komplementaren ersten Datenleitungen (N1 bis N6)
in Reihe geschaltet ist, eine sechste Schaltungseinrichtung (Tr1) zwischen die Leitungen des
Paars von ersten Datenleitungen auf der Eingangsseite der Speicherzelle (11) zum Angleichen
durch Zusammenschalten des Paars von ersten
Datenleitungen (N1, N2) geschaltet ist, und ein
Steueranschluli der sechsten Schalteinrichtung
(Tr1 ) mit dem Ausgangsanschluli der ersten Angleichungsimpuls-Erzeugungseinrichtung (41) verbunden ist.
6.
Datenleseschaltung nach Anspruch 1, wobei eine weitere Schalteinrichtung (Tr3A) zwischen
das Paar von ersten Datenleitungen (N5, N6)
parallel zu der ersten Schalteinrichtung (Tr3) geschaltet ist und der erste Angleichungsimpuls
(<|>eq) an einen Steueranschluli der siebten Schalteinrichtung (Tr3A) angelegt ist.
7.
Datenleseschaltung fur eine Halbleiterspeichereinrichtung, umfassend:
eine Vielzahl von Leseverstarkern (22, 23, 24),
die sequentiell und seriell durch ein komplementares Paar von ersten Datenleitungen (N10 bis
N13) verbunden sind, wobei ein komplementares
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55
8
14
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EP 0 408 031 B1
Paar von zweiten Datenleitungen (N1 bis N6) mit
einem Leseverstarker (22) einer ersten Stufe der
Vielzahl von Leseverstarkern verbunden ist und
wobei Daten einer gemali einer Adresse gewahlten Speicherzelle (11) auf das komplementare
Paar von zweiten Datenleitungen ausgegeben
werden;
eine erste Schalteinrichtung (Tr3) zum Angleichen des komplementaren Paars von zweiten
Datenleitungen (N5, N6) an der Eingangsseite
des ersten Leseverstarkers (22) durch Zusammenschalten der zweiten Datenleitungen;
eine zweite Schalteinrichtung (Tr31, Tr32) zum
Angleichen des komplementaren Paars von ersten Datenleitungen (N10, N11; N12, N13) durch
Zusammenschalten der ersten Datenleitungen;
eine dritte Schalteinrichtung (Tr5, Tr6, Tr33 bis
Tr36) zum Angleichen durch Verbinden der Leitungen des komplementaren Paars von Datenleitungen auf der Eingangsseite jeder der Vielzahl
von Leseverstarkern (22, 23, 24) mit entsprechenden des komplementaren Paars von Datenleitungen auf der Ausgangsseite jeder der Vielzahl von Leseverstarkern;
eine vierte Schalteinrichtung (Tr4) zum Angleichen eines komplementaren Paars von dritten
Datenleitungen (N7, N8) als die Ausgangsanschlusse des Leseverstarkers (24) der letzten
Stufe der Vielzahl von Leseverstarkern (22 bis
24) durch Zusammenschalten der Leitungen des
komplementaren Paars von dritten Datenleitungen;
eine zweite Angleichungsimpuls-Erzeugungseinrichtung (42) zum Erzeugen eines zweiten Angleichungsimpulses (<>
| eq')> wenn die Adresse geandert wird und zum Einschalten der ersten
Schaltungseinrichtung (Tr3) und wenigstens der
zweiten Schaltungseinrichtung (Tr31) fur die erste Stufe der zweiten Schalteinrichtung (Tr31,
Tr32) durch Anlegen des zweiten Angleichungsimpulses an Steueranschltisse der ersten Schaltungseinrichtung (Tr3) und an die besagte wenigstens zweite Schalteinrichtung (Tr31) fur die erste Stufe; und
eine erste Angleichungsimpuls-Erzeugungseinrichtung (41) zum Erzeugen eines ersten Angleichungsimpulses (<|>eq), wenn die Adresse geandert wird und zum Einschalten der zweiten Schaltungseinrichtung (Tr32) fur die zweite Stufe der
zweiten Schaltungseinrichtung (Tr31, Tr32), an
die der zweite Angleichungsimpuls (<|)eq') nichtangelegt ist, der dritten Schalteinrichtung (Tr5, Tr6,
Tr33 bis Tr36) durch Anlegen des ersten Angleichungsimpulses (<>
| eq) und dervierten Schalteinrichtung (Tr4) an Steueranschltisse der Schaltungseinrichtung (Tr32) der zweiten Stufe, der
dritten Schalteinrichtung (Tr5, Tr6, Tr33 bis Tr36)
und dervierten Schaltungseinrichtung (Tr4),
wobei die mit einem Ausgangsanschluli der zweiten Angleichungsimpuls-Erzeugungseinrichtung
(42) verbundene Lastkapazitat [C(<|>eq')] kleiner
eingestellt ist als die mit einem Ausgangsanschluli der ersten Angleichungsimpuls-Erzeugungseinrichtung (41) verbundene Lastkapazitat
[C(<|)eq)]; und
wobei die Anzahl von Stufen von Logikschaltungen, die die zweite Angleichungsimpuls-Erzeugungseinrichtung (42) bilden, kleiner ist als die
Anzahl von Stufen von Logikschaltungen, die die
erste Angleichungsimpuls-Erzeugungseinrichtung (41) bilden, und wobei der zweite Angleichungsimpuls (<|>eq') von der zweiten Angleichungsimpuls-Erzeugungseinrichtung (42) fruher eingerichtet wird als der erste Angleichungsimpuls (<|>eq) von der ersten AngleichungsimpulsErzeugungseinrichtung (41).
5
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20
8.
Datenleseschaltung nach Anspruch 7, ferner umfassend eine Detektorschaltung (30) zum Erfassen einer Anderung einer Adresse; wobei
die ersten und zweiten Angleichungsimpuls-Erzeugungsschaltungen (41, 42) die ersten und
zweiten Angleichungsimpulse (<|>eq, <|>eq') im Ansprechen auf ein Signal von der Detektorschaltung (30) erzeugen.
9.
Datenleseschaltung nach Anspruch 7, ferner umfassend:
einen Ausgangspuffer (25) zum Empfang von Signalen von dem Paar von dritten Datenleitungen
(N7, N8); und
Ausgangspuffertransistoren mit in Reihe geschalteten ersten und zweiten Transisotren
(Tr21, Tr22) zum Empfang eines komplementaren Paars von Ausgangen von dem Ausgangspuffer (25), wobei die Gates der ersten und zweiten Transistoren einen und den anderen Ausgang
des komplementaren Paars von Ausgangen erhalten, und die Daten in einer Speicherzelle (11)
entsprechend der Adresse von einem Verbindungsknotenpunkt (N9) zwischen den ersten und
zweiten Transistoren ausgegeben werden.
25
30
35
40
45
50
55
9
16
10. Datenleseschaltung nach Anspruch 6, dadurch
gekennzeichnet, dali das komplementare Paar
von zweiten Datenleitungen (N1 bis N6) einen
anderen Leseverstarker (21) an einer dazwischenliegenden Stelle aufweist, das Paar von
Datenleitungen (N5, N6) zwischen dem anderen
Leseverstarker (21) und dem Leseverstarker (22)
durch die erste Schalteinrichtung (Tr3) zusammengeschaltet werden, einefunfte Schalteinrichtung (Tr2) zwischen das Paarvon zweiten Datenleitungen (N3, N4) an der Eingangsseite des anderen Leseverstarkers (21) zum Angleichen
durch Zusammenschalten der Leitungen des
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EP 0 408 031 B1
Paars von zweiten Datenleitungen (N3, N4) geschaltet ist, und ein Steueranschluli der funften
Schalteinrichtung (Tr2) und ein Ausgangsanschluli der ersten Angleichungsimpuls-Erzeugungsschaltung (41) zusammengeschaltet sind.
11. Datenleseschaltung nach Anspruch 10, wobei eine sechste Schalteinrichtung (Tr11, Tr12) zwischen den anderen Leseverstarker (21) und die
Speicherzelle (11) an den entsprechenden der
komplementaren zweiten Datenleitungen (N1,
N3; N2, N4) in Reihe geschaltet ist, eine siebte
Schalteinrichtung (Tr1) zwischen die Leitungen
des Paars von zweiten Datenleitungen an der
Eingangsseite der Speicherzelle (1 1) zum Angleichen durch Zusammenschalten des Paars von
zweiten Datenleitungn (N1, N2) geschaltet ist,
und ein Steueranschluli der siebten Schalteinrichtung (Tr1) mit dem Ausgangsanschluli der ersten
Angleichungsimpuls-Erzeugungseinrichtung (41) verbunden ist.
12. Datenleseschaltung nach Anspruch 7, wobei eine weitere Schalteinrichtung (Tr3A) zwischen
das Paar von zweiten Datenleitungen (N5, N6)
parallel zu der ersten Schalteinrichtung (Tr3) geschaltet ist und der erste Angleichungsimpuls
(<|>eq) an einen Steueranschluli der siebten Schalteinrichtung (Tr3A) angelegt ist.
- un troisieme moyen de commutation (Tr5,
Tr6) pour assurer une egalisation par
connexion des lignes de ladite paire de premieres lignes de donnees (N5, N6), du cote
d'entree dudit amplificateur de detection
(22), avec des lignes correspondantes de
ladite paire de secondes lignes de donnees
(N7, N8) ;
- un moyen generateur de seconde impulsion d'egalisation (42) pour produire une
seconde impulsion d'egalisation (<J>eq<)
quand ladite adresse est changee et pour
rendre conducteur ledit premier moyen de
commutation (Tr3) par application de ladite
seconde impulsion d'egalisation a une borne de commande dudit premier moyen de
commutation ;
- un moyen generateur de premiere impulsion d'egalisation (41) pour produire une
premiere impulsion d'egalisation (<Peq)
quand ladite adresse est changee et pour
rendre conducteurs lesdits second et troisieme moyens de commutation (Tr4 ; Tr5,
Tr6) par application de ladite premiere impulsion d'egalisation a des bornes de
commande desdits second et troisieme
moyens de commutation ;
Circuit
dans lequel la capacite de charge [C(®eq)] reliee a une borne de sortie dudit
moyen generateur de seconde impulsion
d'egalisation (42) est reglee a une valeur
plus petite que la capacite de charge
[C(©eq)] reliee a une borne de sortie dudit
moyen generateur de premiere impulsion
d'egalisation (41), et
- dans lequel le nombre d'etages de circuits
logiques constituant ledit moyen generateur de seconde impulsion d'egalisation
(42) est plus petit que le nombre d'etages
de circuits logiques constituant ledit moyen
generateur de premiere impulsion d'egalisation (41), et dans lequel ladite seconde
impulsion d'egalisation (<J>eq<) provenant dudit moyen generateur de seconde impulsion
(42) est produite plus tot que ladite premiere
impulsion d'egalisation (<Peq) provenant dudit moyen generateur de premiere impulsion d'egalisation (41).
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20
25
Revendications
1.
Circuit de lecture de donnees pour un dispositif
semi-conducteur de memorisation, comprenant :
- un amplif icateur de detection (22) a I'entree
duquel sontappliquees des donnees provenant d'une cellule de memoire (11), selectionnees en correspondance a une adresse
par I'intermediaire d'une paire de premieres
lignes de donnees complementaires (N1 a
N6) et qui transmet a sa sortie des donnees
introduites et amplif iees a une paire de secondes lignes de donnees complementaires (N7, N8) ;
- un premier moyen de commutation (Tr3)
pour assurer legalisation de ladite paire de
premieres lignes de donnees complementaires (N5, N6), sur le cote d'entree dudit
amplificateur de detection (22), par
connexion desdites premieres lignes de
donnees I'une avec I'autre ;
- un second moyen de commutation (Tr4)
pour assurer une egalisation de ladite paire
de secondes lignes de donnees complementaires (N7, N8) par connexion desdites
secondes lignes de donnees I'une avec
I'autre ;
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40
45
50
55
10
18
2.
Un circuit de lecture de donnees selon la revendication 1, comprenant en outre un circuit detecteur (30) pour detecter un changement de ladite
adresse et dans lequel lesdits circuits (41 , 42) generateurs de premiere et de seconde impulsion
d'egalisation produisent lesdites premiere et seconde impulsion d'egalisation (<Peq' <J>eq<) en reponse a un signal produit a la sortie dudit circuit
detecteur (30).
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EP 0 408 031 B1
Un circuit de lecture de donnees selon la revendication 1, comprenant en outre :
- un tampon de sortie (25) pour recevoir des
signaux provenant de ladite paire de secondes lignes de donnees (N7, N8) et
- des transistors de tampon de sortie
comprenant des premier et second transistors relies en serie (Tr21, Tr22) pour recevoir une paire de signaux complementaires
de sortie dudit tampon de sortie (25), des
electrodes de commande desdits premier
et second transistors recevant I'un et I'autre
un signal de sortie de ladite paire de signaux complementaires de sortie, et les
donnees se trouvant dans une cellule de
memoire (11) en correspondance a ladite
adresse etant transmises a la sortie a partir
d'un point d'interconnexion (N9) entre lesdits premier et second transistors.
Un circuit de lecture de donnees selon la revendication 1, dans lequel ladite paire complementaire de premieres lignes de donnees (N1 a N6)
comporte un autre amplificateur de detection
(21) dans une zone intermediate, lesdites deux
lignes de donnees (N5, N6) sont reliees ensemble, entre ledit autre amplificateur de detection
(21) et ledit premier amplificateur de detection
(22) , par ledit premier moyen de commutation
(Tr3), un quatrieme moyen de commutation (Tr2)
est connecte entre les deux premieres lignes de
donnees (N3, N4) sur le cote d'entree dudit autre
amplificateur de detection (21) en vue d'assurer
une egalisation par connexion des lignes de ladite paire de premieres lignes de donnees (N3, N4)
I'une avec I'autre, et une borne de commande dudit quatrieme moyen de commutation (Tr2) et une
borne de sortie dudit moyen generateur de premiere impulsion d'egalisation (41) sont reliees
ensemble.
Un circuit de lecture de donnees selon la revendication 4, dans lequel un cinquieme moyen de
commutation (Tr11, Tr12) est connecte en serie
entre ledit autre amplificateur de detection (21)
et ladite cellule de memoire (11) en correspondance avec certaines desdites premieres lignes
de donnees complementaires (N1 a N6), un sixieme moyen de commutation Tr1) est connecte entre les lignes faisant partie desdites premieres lignes de donnees sur le cote d'entree de ladite
cellule de memoire (11) afin d'assurer une egalisation par connexion de ladite paire de premieres
lignes de donnees (N1, N2) I'une avec I'autre, et
une borne de commande dudit sixieme moyen de
commutation (Tr1) est connectee a la borne de
sortie dudit moyen generateur de premiere impulsion d'egalisation (41).
6.
Un circuit de lecture de donnees selon la revendication 1, dans lequel un autre moyen de
commutation (Tr3A), situe entre les deux lignes
de ladite paire de premieres lignes de donnees
(N5, N6), est connecte en parallele avec ledit premier moyen de commutation (Tr3), et ladite premiere impulsion d'egalisation (<Peq) est appliquee
a une borne de commande dudit septieme moyen
de commutation (Tr3A).
7.
Un circuit de lecture de donnees pour un dispositif semi-conducteur de memorisation, comprenant :
- un ensemble d'amplif icateurs de detection
(22, 23, 24) connectes sequentiellement et
en serie au moyen d'une paire complementaire de premieres lignes de donnees (N10
a N13), une paire complementaire de secondes lignes de donnees (N1 a N6) etant
connectees a un amplificateur de detection
de premier etage (22) faisant partie dudit
ensemble d'amplificateur de detection, et
une donnee d'une cellule de memoire (11)
selectionnee en correspondance a une
adresse etant transmise a ladite paire
complementaire de secondes lignes de
donnees ;
- un premier moyen de commutation (Tr3)
pour legalisation de ladite paire complementaire de secondes lignes de donnees
(N5, N6) sur le cote d'entree dudit premier
amplificateur de detection (22) par
connexion desdites secondes lignes de
donnees I'une avec I'autre ;
- un second moyen de commutation (Tr31,
Tr32) pour assurer une egalisation de ladite
paire complementaire de premieres lignes
de donnees (N10, N11 ; N12, N13) par
connexion desdites premieres lignes de
donnees I'une avec I'autre ;
- un troisieme moyen de commutation (Tr5,
Tr6, Tr33 a Tr36) pour assurer une egalisation par connexion des lignes de ladite paire
complementaire de lignes de donnees sur
le cote d'entree de chacun des amplificateurs de detection dudit ensemble (22, 23,
24) avec les lignes correspondantes de ladite paire complementaire de lignes de donnees du cote de sortie de chacun des amplif icateurs de detection dudit ensemble ;
- un quatrieme moyen de commutation (Tr4)
pour assurer une egalisation d'une paire
complementaire de troisiemes lignes de
donnees (N7, N8) aux bornes de sortie de
I'amplif icateur de detection de dernier etage (24) dudit ensemble d'amplificateur de
detection (22 a 24) par connexion des lignes de ladite paire complementaire de
5
10
15
20
25
30
35
40
45
so
55
11
20
21
-
-
-
-
EP 0 408 031 B1
troisiemes lignes de donnees I'une avec
I'autre ;
un moyen generateur de seconde impulsion d'egalisation (42) pour produire une
seconde impulsion d'egalisation (<J>eq<) lorsque ladite adresse est changee et pour rendre conducteur ledit premier moyen de
commutation (Tr3) et au moins le second
commutateurde premier etage (Tr31) dudit
second moyen de commutation (Tr31 , Tr32)
par application de ladite seconde impulsion
d'egalisation aux bornes de commande dudit premier moyen de commutation (Tr3) et
aux bornes de commande d'au moins ledit
second commutateur de premier etage
(Tr31);
un moyen generateur de premiere impulsion d'egalisation pour produire une premiere impulsion d'egalisation (<Peq) quand
ladite adresse est changee et pour rendre
conducteur le second commutateur de second etage (Tr32) dudit second moyen de
commutation (Tr31, Tr32) qui n'a pas recu
ladite seconde impulsion d'egalisation
(<3>eq')> pour rendre conducteur ledit troisieme moyen de commutation (Tr5, Tr6, Tr33
a Tr36) par application de ladite premiere
impulsion d'egalisation (<J>eq), et pour rendre
conducteur ledit quatrieme moyen de
commutation (Tr4) par application de cette
premiere impulsion d'egalisation (<Peq) aux
bornes de commandes dudit second
commutateurde second etage (Tr32), dudit
troisieme moyen de commutation (Tr5, Tr6,
Tr33 a Tr36) dudit quatrieme moyen de
commutation (Tr4) ;
circuit dans lequel la capacite de charge [C(®eq)]. reliee a une borne de sortie dudit
moyen generateur de seconde impulsion
d'egalisation (42) est reglee a une valeur
plus petite que la capacite de charge
[C(©eq)] reliee a une borne de sortie dudit
moyen generateur de premiere impulsion
d'egalisation (41), et
dans lequel le nombre d'etages de circuits
logiques constituant ledit moyen generateur de seconde impulsion d'egalisation
(42) est plus petit que le nombre d'etages
de circuits logiques constituant ledit moyen
generateur de premiere impulsion d'egalisation (41), et oil ladite seconde impulsion
d'egalisation (<J>eq<) provenant dudit moyen
generateur de seconde impulsion d'egalisation (42) est produite plus tot que ladite
premiere impulsion d'egalisation (<Peq) provenant dudit moyen generateurde premiere
impulsion d'egalisation (41).
8.
Circuit de lecture de donnees selon la revendication 7, comprenant en outre un circuit detecteur
(30) pour detecter un changement de ladite
adresse et dans lequel lesdits circuits (41 , 42) de
generation de premiere etde seconde impulsions
d'egalisation produisent lesdites premiere et seconde impulsions (<beq, <Peq') en reponse a un signal fourni par ledit circuit detecteur (30).
9.
Circuit de lecture de donnees selon la revendication 7, comprenant en outre :
- un tampon de sortie (25) pour recevoir des
signaux provenant de ladite paire de troisiemes lignes de donnees (N7, N8); et
des
transistors de tampon de sortie
comprenant des premier et second transistors relies en serie (Tr21, Tr22) pour recevoir une paire complementaire de signaux
de sortie provenant dudit tampon de sortie
(25) , les electrodes de commande desdits
premier et second transistors recevant I'un
et I'autre signal de sortie de ladite paire
complementaire et les donnees se trouvant
dans une cellule de memoire (11) en correspondance a ladite adresse etant transmises
a la sortie a partir d'un point d'interconnexion (N9) entre lesdits premier et second
transistors.
5
10
15
20
25
30
35
40
45
50
55
12
22
10. Circuit de lecture de donnees selon la revendication 6, dans lequel ladite paire complementaire de
secondes lignes de donnees (N1 a N6) comporte
un autre amplif icateurde detection (21) dans une
zone intermediate, les deux lignes de donnees
(N5, N6) de ladite paire situees entre ledit autre
amplificateur de detection (21) et ledit premier
amplificateur de detection (22) sont reliees ensemble par ledit premier moyen de commutation
(Tr3), un cinquieme moyen de commutation (Tr2)
est connecte entre les secondes lignes de donnees (N3, N4) de ladite paire sur le cote d'entree
dudit autre amplificateur de detection (21) pour
assurer une egalisation par connexion des lignes
de ladite paire de secondes lignes de donnees
(N3, N4) I'une avec I'autre, et une borne de
commande dudit cinquieme moyen de commutation (Tr2) ainsi qu'une borne de sortie dudit
moyen generateurde premiere impulsion d'egalisation (41) sont reliees ensemble.
11. Circuit de lecture de donnees selon la revendication 10, dans lequel un sixieme moyen de
commutation (Tr11, Tr12) est connecte en serie
entre ledit autre amplificateur de detection (21)
et ladite cellule de memoire (11) en correspondance a des lignes complementaires faisant partie des secondes lignes de donnees ( N1, N3 ;
N2, N4), un septieme moyen de commutation
23
EP 0 408 031 B1
(Tr1) est connecte entre les lignes de ladite paire
de secondes lignes de donnees sur le cote d'entree de ladite cellule de memoire (11) pour assurer une egalisation par connexion de ladite paire
de secondes lignes de donnees (N1, N2) I'une
avec I'autre, et une borne de commande dudit
septieme moyen de commutation (Tr1) est reliee
a la borne de sortie dudit moyen generateur de
premiere impulsion d'egalisation (41).
12. Circuit de lecture de donnees selon la revendication 7, dans lequel un autre moyen de commutation (Tr3A) est connecte, entre les deux secondes lignes de donnees precitees (N5, N6), en parallel avec ledit premier moyen de commutation
(Tr3), et ladite premiere impulsion d'egalisation
(<3>eq) est appliquee a une borne de commande
dudit septieme moyen de commutation (Tr3A).
5
10
15
20
25
30
35
40
45
50
13
24
EP 0 408 031 B1
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