Three-Step vs Six-Step PWM in Three-Phase Boost PFC Rectifier

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2506554, IEEE
Transactions on Power Electronics
Performance Comparison of Three-Step and Six-Step PWM
in Average-Current-Controlled
Three-Phase Six-Switch Boost PFC Rectifier
Laszlo Huber, Misha Kumar, and Milan M. Jovanović
Abstract – In this paper, a three-step PWM method for the
average-current-controlled three-phase six-switch boost PFC
rectifier is proposed. It is shown that the three-step PWM
compared to the conventional six-step PWM exhibits a lower
total harmonic distortion of input currents and higher power
factor. However, the three-step PWM, unlike the six-step
PWM, is adversely affected by duty-cycle limitations and has
unbalanced conduction losses of the upper and lower switches of
the three-phase rectifier bridge. The average-current control
with three-step and six-step PWM is illustrated with
Matlab/Simulink simulation waveforms and experimentally
verified on a 3-kW prototype.
Index Terms –Three-phase six-switch boost PFC rectifier,
average-current control, three-step PWM, six-step PWM,
discontinuous space-vector modulation (SVM), segment
detection, duty-cycle limitation, low-pass filtering and sampling,
zero-sequence signal (ZSS) injection, total harmonic distortion
(THD), power factor (PF)
I. INTRODUCTION
Today, active three-phase PFC rectifiers need to meet very
challenging performance requirements. In the majority of
applications, the input current of active three-phase PFC
rectifiers is required to have a total harmonic distortion
(THD) less than 5% and a power factor (PF) greater than 0.99
[1]. One of the most cost-effective topologies that can meet
these requirements is the three-phase six-switch boost PFC
rectifier [2], which is usually implemented without neutralpoint connection.
A number of control methods that can achieve a high
quality of input currents in the three-phase six-switch boost
PFC rectifier are available [3], [4]. Generally, approaches
using direct control of input current versus, for example,
direct power control, result in better quality of the input
currents [5].
Today, the control circuit is usually
implemented with digital technology. One direct current
control method, well suited for digital implementation, is the
average current control [6], [7].
In three-wire, three-phase applications, because the sum of
the phase currents is zero, the control can be implemented by
having only two out of three current controllers actively
shaping the current at a given time. The desired current in the
inactive-controller phase is obtained by the sum of currents of
the actively controlled phases. One implementation of this
control method is based on dividing the line cycle of the input
phase voltages into six 60o segments (six-step PWM) as
shown in Fig. 1(a) [8], [9]. In each 60o segment, the
controller in the phase with the highest absolute value voltage
is disabled, i.e., switches in the corresponding leg are turned
off, which results in reduced switching losses.
In this paper, another implementation of this control
method is proposed. It is based on dividing the line cycle of
the input phase voltages into three 120o segments (three-step
PWM) as shown in Fig. 2. In each 120o segment, the
controller in the phase with the most positive (or most
negative) phase voltage is disabled, i.e., the switches in the
corresponding leg are turned off. The three-step PWM is
equivalent to the discontinuous space-vector modulation
(SVM) with unbalanced conduction losses between the upper
and lower switches [10].
A detailed performance comparison of the three-step and
six-step PWM in the average-current controlled three-phase
six-switch boost PFC rectifier is also provided in the paper.
It is shown that the three-step PWM compared to the six-step
PWM exhibits lower THD of input currents and higher PF.
The operation of the three-step and six-step PWM is
illustrated with Matlab/Simulink simulation waveforms and
experimentally verified on a 3-kW prototype.
II. AVERAGE CURRENT CONTROL WITH THREE-STEP AND
SIX-STEP PWM
In the six-step PWM, a line cycle of input phase voltages is
divided into six 60o segments such that within a 60o segment
none of the three phase voltages changes sign, as shown in
Fig. 1(a). In each 60o segment, the controller in the phase
with the highest absolute value voltage is disabled, i.e.,
switches in the corresponding leg are turned off. For
example, in segment I, the controller in phase “a” is disabled,
i.e., switches Sap and San are turned off, as shown in Fig. 1(b).
The simplified circuit diagram of the three-phase six-switch
boost PFC rectifier with six-step PWM in segment I is shown
in Fig. 1(c). Since in segment I, the leg in phase “a” is
disabled and phase current ia is positive, rectifier input aR is
connected to the positive output rail (through diode Dap). By
sinusoidal modulation of switches in legs “b” and “c”,
desired sinusoidal average phase-to-phase voltages vaRbR and
vaRcR can be generated between the rectifier inputs,
respectively. As the sum of the phase-phase voltages at the
rectifier inputs must be zero, desired voltage vbRcR is
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Transactions on Power Electronics
DISABLED
PHASE
Sap
v c0
v b0
v a0
va0
La
i a >0
vb0
Lb
i b <0
Lc
i c <0
0
ωt
o
-30
0
I
30
o
90o
II
150o
III
210 o
IV
270o
V
vc0
Scp
Cp
aR
Vo
bR
cR
S an
330 o
p
S bp
S bn
v a0
ωt
Scn
0o
n
(a)
60 o
I
(b)
180 o
La
i a>0
vab>0
Lb
i b<0
vbc
ib = iab − ibc
a
i ac
vac >0
i ab
b
i bc
c
Lc
i c <0
ic = iac + ibc
300 o
(a)
Scp
Dap
aR
v c0
Cp
0o
vaRbR
vaRcR
Vo
bR
Cn
cR
Sbn
360 o
I
III
II
p
Sbp
v envp
Cn
VI
ia = iab + iac
v c0
v b0
Scn
n
v a0
120 o
I
v b0
240 o
II
ωt
v envn
360 o
III
(b)
Fig. 2
Three-step PWM with 120o
segments referenced to: (a) positive
envelope, (b) negative envelope of input
phase voltages.
(c)
Fig. 1 Six-step PWM: (a) 60o segments, (b) circuit diagram in segment I, (c) simplified circuit diagram in
segment I.
automatically generated. To generate sinusoidal average
phase-to-phase voltages between rectifier inputs, the current
controllers are designed to control phase-phase currents. The
output of the phase-phase-current controllers determines the
phase-phase duty cycles dab, dbc, and dca so that in steady-state
operation vaRbR=dabVo, vbRcR=dbcVo, and vcRaR=dcaVo. Switch
duty cycles dap, dbp and dcp are obtained from phase-phase
duty cycles so that dab=dap-dbp, dbc=dbp-dcp, and dca=dcp-dap.
For example, in segment I, dap=1 and, therefore, dbp=1-dab and
dcp=1+dca. It should be noted that dap=1 means that rectifier
input aR is connected to the positive output rail due to the
conduction of diode Dap. The steady-state duty cycle of all
switches is summarized in Table I, whereas, the variation of
duty cycle dap during the whole line cycle is shown in Fig. 3
as an example. As can be seen in Fig. 3, duty cycle dap
exhibits abrupt changes at 60o-segment transitions, which
induces input-current transients at the segment transitions.
These transients, which can be seen as notches and glitches in
the input current waveforms and can be regarded as segmenttransition noise, may cause false segment detection in the sixstep PWM.
In the proposed three-step PWM, a line cycle of input
phase voltages is divided into three 120o segments such that
within a 120o segment one phase voltage is always greater or
smaller than the other two phase voltages, as shown in Figs.
2(a) and 2(b), respectively. Accordingly, the three-step
PWM is either referenced to the positive or to the negative
envelope of the phase voltages. In each 120o segment, the
controller in the phase with the most positive (or most
negative) phase voltage is disabled, i.e., the switches in the
corresponding leg are turned off. Similarly to the six-step
PWM, the control goal is to generate sinusoidal average
phase-to-phase voltages between the rectifier inputs aR, bR
and cR, and, therefore, the current controllers are designed to
control the phase-phase currents. The steady-state duty
cycles of the switches operating with three-step PWM
referenced to the positive and negative envelope of the phase
voltages are summarized in Tables II and III, respectively,
whereas, the variation of the corresponding duty cycle dap
during the whole line cycle is shown in Figs. 4(a) and 4(b).
As can be seen in Fig. 4, duty cycle dap does not exhibit
abrupt changes at 120o-segment transitions. As a result, the
three-step PWM exhibits much reduced notches and glitches
at the segment transitions so that segment detection is much
less sensitive to segment-transition noise compared to that in
the six-step PWM.
Comparing duty cycle dap in Figs. 3 and 4, it can be
concluded that practical duty-cycle limitations (in order to
meet the dead-time requirements for the IGBT module and
taking into account the propagation delay times of the
optocouplers in the interface circuit between the DSP and
IGBT module) only affect the three-step PWM. As can be
seen from Fig. 3, for a minimum duty cycle Dmin=0.05 and
maximum duty cycle Dmax=0.95, as an example, the dutycycle limitations do not have effect on the six-step PWM
circuit operation because the duty-cycles of the switches in
the two active phases are in the 0.265-0.735 range. In Fig. 3,
when the switches in leg “a” are turned off, dap=1 in segment
I and dap=0 in segment IV is achieved through the conduction
of diodes Dap and Dan, respectively. However, for the threestep PWM implementation, the limited duty-cycle range
affects circuit operation and its performance. As can be seen
in Fig. 4(a), at the beginning of segment II duty cycle dap is
required to continuously decrease from unity, whereas at the
end of segment III dap is required to continuously increase to
unity. However, if the maximum duty cycle is limited to
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Transactions on Power Electronics
TABLE I - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR SIX-STEP PWM
60° Segment dap
dan
dbn
dcp
dcn
I
II
III
IV
V
1
0
1-dab dab
-dca 1+dca dbc 1-dbc
1
0
1+dab -dab
0
1
-dab 1+dab
1-dca dca 1+dbc -dbc
1+dca
0
1-dbc
dca
1
-dca
1
dbc
1-dca
0
VI
dab
-dbc
1+dbc
1-dab
dbp
0
1
TABLE II - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR THREE-STEP
PWM REFERENCED TO POSITIVE ENVELOPE OF PHASE VOLTAGES
d ap
1
0.95
0.735
I
II
III
dap
dan
dbp
1
0
1-dab
1
1+dab -dab
1- dca dca 1+dbc
dbn
dab
0
-dbc
dcp
1+dca
1-dbc
1
TABLE III - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR THREE-STEP
PWM REFERENCED TO NEGATIVE ENVELOPE OF PHASE VOLTAGES
120° Segment
I
II
III
dap
dan
dbp
dbn
dcp
dcn
-dca 1+ dca dbc
0
1
-dab
0
dab 1-dab
1-dbc
1+dab
1
0
dca
-dbc
1
1- dca
1+dbc
Dmax=0.95, the phase current will be distorted at the I-to-II
and III-to-I segment transitions. Similarly, as can be seen in
Fig. 4(b), at the end of segment I duty cycle dap is required to
decrease to zero, whereas at the beginning of segment III dap
is required to increase from zero. However, if the minimum
duty cycle is limited to Dmin=0.05, the phase current will be
distorted at the I-to-II and II-to-III segment transitions.
It should be noted that for both six-step and three-step
PWM, identical operation can be achieved if instead of
phase-to-phase-current controllers, phase-current controllers
are used with appropriate zero-sequence-signal (ZSS)
injection. The implementation with phase-current controllers
and ZSS injection is described in the next section.
III. POWER STAGE AND CONTROL CIRCUIT
The simplified circuit diagram of the three-phase sixswitch boost PFC rectifier is shown in Fig. 5. The switches
are implemented with IGBTs in a six-pack module [11]. The
switching frequency is selected as fsw = 20 kHz, which is the
maximum recommended fsw for the IGBT module. The input
phase voltage range is 120 ± 15% Vrms, 45-65 Hz, the
nominal output voltage is 400 V, and the maximum output
power is 3 kW.
The block diagram of the control circuit common for both
six-step and three-step PWM implemented with phase-phase
current controllers is also shown in Fig. 5. Average-current
control is implemented using digital signal processor (DSP)
TMS320F2808 from TI [12]. For average-current control,
the input phase-phase voltages, phase currents, and the output
voltage are sensed and converted to digital signals through
the 12-bit analog-digital converter (ADC) of the DSP. The
input voltage range of the ADC is 0-3 V, i.e., the full-scale
range FSR = 3 V. As only positive voltages can be applied to
d ab
1 d ca
Dmax
Dmin
30
o
90
I
o
II
150
o
210
o
270o
IV
III
o
330
ωt
VI
V
Fig. 3 Duty cycle of upper switch in phase “a” for six-step PWM at
120Vrms input voltage.
1
0.95
Dmax
1 d ca
1 d ab
d ap
dcn
-dca
dbc
0
1 d ab
0.265
0.05
0
o
-30 0
0
120° Segment
d ca
0o
60 o
120o
I
180 o
II
240 o
360o ωt
300o
III
I
(a)
1
d ca
d ap
0.05
0
0o
d ab
Dmin
60o
I
120o
180o
II
240o
300o
360o ω t
III
(b)
Fig. 4 Duty cycle of upper switch in phase “a” for three-step PWM
referenced to: (a) positive envelope, (b) negative envelope of input phase
voltages (120Vrms).
the input of the ADC, the bipolar phase-phase voltages and
phase currents are scaled to ±FSR/2 and level shifted by
FSR/2. The output signals of the DSP are the digital PWM
(DPWM) gate signals for the bottom switches Sxn, xϵ{a,b,c}.
The DPWM operates with a triangular carrier. As the clock
frequency of the DSP is fsysclock = 100 MHz, the peak value of
the triangular carrier is Cpk = 1/2·fsysclock/fsw = 2500. All the
sensed signals are sampled at the peak of the triangular
carrier, i.e., at the middle of the turn-on time of the upper
switches. It should be noted that by sampling the inductor
currents at the middle of the turn-on time of the upper
switches, the sampled values of the inductor currents are
equal to the average values during a switching period. Since
the value of the average inductor current is directly obtained
in each sample, i.e., it is not reconstructed from several
samples, no antialiasing filter is needed for the sampled
inductor currents. Instead, the sensed current signals need to
be conditioned by a low-pass filter to remove the switching
noise. The corner frequency of the input- and output-voltage
antialiasing filters is fAAFin = 3 kHz and fAAFout = 550 Hz,
respectively, whereas the corner frequency of the low-pass
filter of the sensed inductor-currents is fLPF = 92.5 kHz.
The voltage controller is implemented with PI
compensation (for better regulation of the output voltage),
whereas, the current controller is implemented with P
compensation which exhibits better performance compared to
that with PI compensation. Namely, as it was shown in [13],
[14] for the three-phase six-switch boost PFC rectifier with
average-current control and with mismatched input-voltage
and input-current sensing gains, the current controller with P
compensation exhibits lower THD of input currents and
higher PF compared to that of PI compensation. The
average-current control implementation also includes voltage
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Transactions on Power Electronics
p
S ap
va0
vb0
vc0
ia
La
ib
Lb
ic
Lc
Sbp
S cp
Cp
LINE VOLTAGE
SENSING
S cn
S bn
ANTIALIASING
FILTER
1.5V
Offset
LOW-PASS
FILTER
SEG*
v *oref
ADC
*
1 v abSh
FSR
*
v caSh
*
*
iab
VOLTAGE
FEEDFORWARD
i abref K mAB B
2
C
*
vab
*
VOLTAGE
CONTROLLER
A
AVG
*
v ab
1
3
i aref
Phase-Phase AB
*
Phase-Phase BC v b0
*
Phase-Phase CA v c0
v o*
K mAB
B
ADC
FSR
2
*
v ab
1
FSR
*
v ca
*
va0
VOLTAGE
CONTROLLER
SEGMENT
DETECTION
DSP
*
v ZSS
AVG
v *a0
1
3
ZERO-SEQUENCE
SIGNAL (ZSS)
GENERATOR
Phase A
Phase B
SEG *
*
v oref
*
v EA
C2
Phase C
*
v a0
1
ADC FSR
DPWM
D*CCa
*
*
S ap
C A
*
v oref
v EA
S an
*
Dan
ia
1
FSR
v o*
d*ca
C
FSR
2
v *oref
ADC
1
ADC FSR
STEP
LOGIC
d*ab
CURRENT
CONTROLLER
1
3
* +v*
v a0
ZSS
*
1*
2
CURRENT
CONTROLLER
DPWM
*
v ab
ADC *
1 i aSh
FSR
*
i bSh
*
v a0
Sap
S an
DUTY-CYCLE
FEEDFORWARD
ANTIALIASING
FILTER
DUTY-CYCLE
FEEDFORWARD +
ZSS INJECTION
v ZSS
n
PHASE CURRENT
SENSING
n
OUTPUT VOLTAGE
SENSING
-
Cn
S an
1.5V
Offset
+
vo
*
v b0
*
v c0
Fig. 6 Block diagram of control circuit for implementation of sixstep and three-step PWM with phase-current controllers and ZSS
injection.
* - notation for digital values
Fig. 5 Simplified circuit diagram of power stage (La=Lb=Lc=1mH, Cp=Cn=2240µF) and
block diagram of control circuit.
feedforward (VFF) [6] and duty-cycle feedforward (DFF)
[15]. Generally, VFF can make the output voltage practically
insensitive to line-voltage variations. However, VFF with Pcompensated current controller is effective only if DFF is
also implemented, as shown in [13], [14].
The 60o-segments for six-step PWM are detected by using
comparators to determine the sign of the phase voltages,
whereas, the 120o-segments for three-step PWM are detected
by comparing the phase voltages. Because in the six-step
PWM strong transient input-current noise is generated at 60osegment transitions, additional measures are taken to improve
the reliability of the 60o-segment detection. First, the
segment detection is disabled if the absolute value of the sum
of the sensed and sampled phase voltages is significantly
greater than zero, i.e., if |va0+vb0+vc0| > ΔVzero. Second, after
a new segment is detected, the segment detection is disabled
for a specified blanking time Tblank to prevent noise-induced
segment change due to false segment detection. In the
experimental circuit, the segment detection is implemented
with ΔVzero = 13V and Tblank = 9Tsw = 450 μs.
It should be noted that in order to meet the dead-time
requirements for the IGBT module [11] and taking into
account the propagation delay times of the optocouplers in
the interface circuit between the DSP and IGBT module [16],
the duty cycle range is limited from Dmin=0.05 to Dmax =0.95.
The block diagram of the control circuit common for both
six-step and three-step PWM implemented with phasecurrent controllers and ZSS injection is shown in Fig. 6. ZSS
signal vZSS for the six-step PWM, shown in Fig. 7, is obtained
from the input phase voltages and the output reference
voltage as
Voref
− venvp if venvp ≥ venvn

vZSS =  2
V
− oref − v
envn if venvp < venvn

2
,
(1)
while ZSS signals for the three-step PWM referenced to the
positive and negative envelope of input phase voltages,
shown in Figs. 8(a) and (b), respectively, are defined as
vZSS =
Voref
2
− venvp ,
(2)
and
Voref
(3)
− venvn .
2
It can be observed in Figs. 7 and 8 that the sum of phase
voltage va0 and ZSS voltage vZSS, when divided by Voref and
level shifted by ½ will result in the same duty cycle dap as
obtained with the phase-phase-current controllers shown in
Figs. 3 and 4, respectively.
Finally, it should be noted that both the six-step PWM and
three-step PWM implemented with phase-current controllers
and ZSS injection can be equivalently implemented with
space vector modulation with appropriate distribution of the
zero switching state vectors [17], [18].
vZSS = −
IV. PERFORMANCE COMPARISON OF THREE-STEP AND SIXSTEP PWM
Figures 9(a) and (b) show the measured steady-state
waveforms of phase currents ia, ib, and ic at nominal phase
voltage of 120 Vrms and for 2-kW load for the six-step and
three-step PWM referenced to the negative envelope of the
phase voltages, respectively. As can be seen in Figs. 9(a) and
(b), for both six-step and three-step PWM, the phase currents
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Transactions on Power Electronics
Voref / 2
Vm
Va0+vZSS
Va0
Ia
Ib
Ic
THDb=6.83%
PFb=0.9926
(a)
vZSS
0
− Vm
− Voref / 2
THDa=8.52%
PFa=0.9926
THDc=8.19%
PFc=0.9923
Ia
π
0
[ωt]
2π
Fig. 7 ZSS signal for six-step PWM.
Voref / 2
Vm
Va0
Va0+vZSS
0
− Vm
π
[ωt]
2π
(a)
Vm
Va0
0
vZSS
− Vm
− Voref / 2
Va0+vZSS
0
Ic
THDa=3.79%
PFa=0.9982
THDb=3.29%
PFb=0.9976
THDc=3.56%
PFc=0.9976
Fig. 9 Experimental waveforms during steady-state operation (120Vrms,
2kW): phase currents Ia, Ib, Ic [A] with (a) six-step PWM, (b) three-step
PWM referenced to negative envelope of input phase voltages.
vZSS
0
(b)
Ib
π
[ωt]
2π
(b)
Fig. 8 ZSS signal for three-step PWM referenced to: (a) positive envelope,
(b) negative envelope.
are distorted at segment transitions.
However, these
distortions are more pronounced for the six-step PWM.
Consequently, the six-step PWM has higher THD of phase
currents and lower PF compared to the three-step PWM, as
shown by respective THD and PF measurements in Figs. 9(a)
and (b).
The phase-current distortions at segment transitions are
primarily caused by the low-pass filtering and sampling of
the inductor currents. In the three-step PWM, they are also
affected by duty-cycle limitations.
To explain the distortions in the phase currents caused by
the low-pass filtering and sampling, Simulink simulations are
employed. Specifically, simulations for the six-step and
three-step PWM were performed for a decreased low-pass
corner frequency of 20 kHz, instead of 92.5 kHz used in the
experimental circuit, to amplify the effect of the low-pass
filtering for the sake of a more clear explanation. The
simulations were done without limiting the duty cycle, i.e., by
allowing the full duty-cycle range from zero to unity. The
effect of a limited duty-cycle range is addressed by a separate
set of simulations.
The results of the simulations are presented in Fig. 11,
which shows the sampled inductor-current waveforms before
and after the filtering. Specifically, in Figs. 11(c) and (e), the
waveforms of the sampled filtered and unfiltered inductor
current for the six-step and three-step PWM are compared,
respectively. The definition of sampled filter inductor current
Ixfs, xϵ{a,b,c}, and sampled unfiltered inductor current Ixs,
xϵ{a,b,c}, is given in Fig. 10.
As it can be observed in Fig. 11(c) for the six-step PWM,
in every 60o-segment, the sampled filtered inductor currents
in two actively controlled phases are greater than the
corresponding sampled unfiltered inductor currents. For
example, in the highlighted 60o-segment in Fig. 11(c), Iafs>Ias
and Icfs>Ics. To facilitate the understanding of this effect, the
waveforms of input phase voltages vx0, xϵ{a,b,c}, and
inductor currents of phase “a”, i.e., ia, iaf, iafs, and ias in Figs.
11(a)-11(c) are zoomed in around instant T1, where sampled
currents ias and iafs have a negative slope, and instant T2,
where sampled currents ias and iafs have a positive slope, as
shown in Figs. 12(a) and 12(b), respectively. As can be seen
in Fig. 12, filtered inductor current iaf lags behind inductor
current ia. At the sampling instant (at the middle of a
switching period, i.e., at the middle of the turn-on time of the
upper switches), iaf > ia, and, therefore, the sampled filtered
inductor current is greater than the sampled unfiltered
inductor current, i.e., iafs>ias.
The current controllers shape the sampled filtered-inductor
currents to follow the reference currents so that iafs+ibfs+icfs=0.
At the same time, the sum of the three phase currents flowing
in the circuit must be zero, i.e., the sum of the sampled
unfiltered-inductor currents is also zero iaf+ibf+icf=0.
Therefore, if iafs>ias and icfs>ics, it follows that ibfs < ibs, as
shown in Fig. 11(c). Since the current in the phase of nonactive (passive) controller is greater than the activelycontrolled phase currents, at the 60o-segment transitions
when the role of actively and non-actively controlled currents
changes, the current of the phase transitioning to passive
control and the phase transitioning to active control exhibit
step changes. These current changes at the 60o-segment
transitions are primarily responsible for increased current
THD.
At 120o-segment transitions of the three-step PWM, the
difference between sampled filtered and sampled unfiltered
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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Transactions on Power Electronics
200
Ix
LPF
I xf
Ixs
S/H
S/H
V
Ixfs
a0
-100
c0
xϵ{a,b,c}
-200
-4
-5
I
I
200
Vb0
Vc0
0
V
b0
Fig. 10 Definition of sampled filtered and sampled unfiltered currents.
Va0
a
-6
af
-7
100
I
0
I
-100
-200
10
as
afs
(a)
V
a0
0
0
V
-100
af
-5
c0
I
THD=7.63%
(b)
I
I
5
I
bs
I
0
afs
bfs
I
cs
I
-5
cfs -200
-10
10
-2
-3
af
-4
Ibfs<Ibs
I
Iafs>Ias
I
Icfs>Ics
a
I
T1
(c)
0
-5
I
I
5
I
bs
I
0
THD=4.05%
(d)
as
afs
bfs
I
cs
I
cfs
0.295 0.2951 0.2952
Fig. 12 Key simulated waveforms in Figs. 11(a)-(c) for six-step PWM
zoomed in around instants: (a) T1, (b) T2.
T2
af
-10
10
as
afs
-5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0.2946 0.2947 0.2948 0.2949
(b)
5
I
-200
0
a
as
I
(a)
-1
-10
10
I
0.2893 0.2894 0.2895 0.2896 0.2897 0.2898 0.2899
100
V
b0
a
-8
-4
-4.5
-5
-5.5
-6
-6.5
-7
200
5
I
100
V
-5
-10
0.284 0.286 0.288 0.29 0.292 0.294 0.296 0.298
T4
(e)
T3
0.3
Fig. 11 Key simulated waveforms during steady-state operation (120Vrms,
2kW) for corner frequency of low-pass filter of 20 kHz and without dutycycle limitations: (a) input phase voltages [V]; (b) inductor current Ia[A],
filtered inductor current Iaf [A], (c) sampled filtered and sampled unfiltered
inductor currents [A] for six-step PWM; (d) Ia, Iaf [A], (e) sampled filtered
and sampled unfiltered inductor currents [A] for three-step PWM
(referenced to venvn).
inductor currents is significantly smaller than that at 60osegment transitions of the six-step PWM, as it can be
observed in Fig. 11(e). This effect can be explained by the
reduced ripple in the inductor currents at the 120o-segment
transitions, as shown by the zoomed in waveforms in Fig. 13.
Consequently, the phase-current distortions at segment
transitions due to the effect of low-pass filtering and
sampling are less pronounced for three-step PWM than for
six-step PWM.
Simulation waveforms in Fig. 14 illustrate the effect of the
duty-cycle limitations on the phase-current distortions at
segment transitions for the three-step PWM. At 120osegment transitions, without duty-cycle limitations, duty
cycles dxn, xϵ{a,b,c}, and inductor currents ix change without
oscillations, as shown in Figs. 14(c) and 14(b), respectively.
However, limitation of the maximum duty cycle below 1
causes a perturbation and results in duty-cycle oscillations at
120o-segment transitions, as shown in Fig. 14(e).
Consequently, inductor currents also exhibit oscillations at
120o-segment transitions as shown in Fig. 14(d), which
results in increased THD. Specifically, with 5-95% dutycycle limits, the THD of inductor currents increases by 1.48%
compared to that without duty-cycle limits. The THD of
inductor currents at different duty-cycle limits is presented in
Table IV. It can be concluded from Table IV that in order to
meet the THD < 5% requirement, the duty-cycle limits
should be equal or less than 6-94%.
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2506554, IEEE
Transactions on Power Electronics
200
V
a0
Va0
Vb0
Vc0
100
V
b0
0
V
c0
-100
I
a
I
b
I
c
D
an
D
bn
D
-200
-2
-3
I
I
I
I
a
-4
af
-5
as
afs
-6
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
-6
cn
0.2886
0.2888
a0
0.2892
(a)
200
V
0.289
cn
100
V
b0
0
V
c0
-100
I
I
I
-3
a
-4
af
-5
as
afs
-6
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
-6
(a)
THD=2.28%
(b)
(c)
THD=3.76%
(d)
(a)
0.285
0.29 (e)
0.295
0.3
Fig. 14 Key simulated waveforms during steady-state operation (120Vrms,
2kW) with three-step PWM (referenced to negative envelope of input phase
voltages) for corner frequency of low-pass filter of 92.5-kHz: (a) input phase
voltages [V]; (b) inductor currents [A], and (c) duty cycle of bottom switches
[digital values with respect to Cpk=2500] without duty-cycle limits; (d)
inductor currents [A], and (e) duty cycle of bottom switches [digital values
with respect to Cpk=2500] at 5-95% duty-cycle limits.
-200
-2
I
I
a
I
b
I
c
D
an
D
bn
D
200
100
0
-100
-200
10
5
0
-5
-10
2500
2000
1500
1000
500
0
10
5
0
-5
-10
2500
2000
1500
1000
500
0
TABLE IV – THD OF INDUCTOR CURRENTS AT DIFFERENT DUTYCYCLE LIMITS
Duty-cycle limits [%] 0-100
3-97
5-95
6-94
7-93
2.28
2.6
3.76
4.86
6.54
THDi [%]
0.2944
0.2946
(b)
0.2948
0.295
Fig. 13 Key simulated waveforms in Figs. 11(a), (d), (e) for three-step
PWM zoomed in around instants: (a) T3, (b) T4.
Finally, the measured THD of phase currents and power
factor (PF) in the 10%-100% load range, are presented in
Figs. 15(a) and (b), respectively. It should be noted that the
THD and PF values in Fig. 15 are obtained as average values
of the measured THD and PF of individual phases. As can be
seen from Fig. 15, in the entire measured load range the
three-step PWM exhibits lower THD and correspondingly
Six-step PWM
Three-step PWM
Six-step PWM
Three-step PWM
(a)
(b)
Fig. 15 Measured performance of three-step and six-step PWM as function of load current: (a) THDi; (b) PF.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2506554, IEEE
Transactions on Power Electronics
higher PF compared to the six-step PWM. The performance
of the three-step is significantly better than that of the sixstep PWM at lighter loads. For the experimental circuit with
the three-step PWM the measured THD of the input current
was below 5% in the 50-100% load range.
V. SUMMARY
In this paper, a three-step PWM method for average
current controlled three-phase six-switch boost PFC rectifier
is proposed and its performance is compared to the
conventional six-step PWM method.
The steady-state duty cycles of the switches in the threestep PWM do not exhibit abrupt changes at the 120o-segment
transitions, unlike the steady-state duty cycles of the switches
in the six-step PWM which change abruptly at the 60osegment transitions. As a result, the three-step PWM induces
smaller input-current transients at the segment transitions,
which improves its THD and PF performance and reduces its
sensitivity to false segment detection. However, the threestep PWM, unlike the six-step PWM, is adversely affected by
duty cycle limitations.
Both the six-step and three-step PWM can be implemented
either with phase-current controllers and an appropriate ZSS
injection or with phase-phase current controllers, which
inherently include ZSS injection.
Performance comparison of the three-step and six-step
PWM is done on a 3-kW prototype of the three-phase sixswitch boost PFC rectifier. In the entire measured load range
the three-step PWM exhibits lower THD and correspondingly
higher PF compared to the six-step PWM. The performance
of the three-step is significantly better than that of the sixstep PWM at lighter loads.
REFERENCES
[1] J.W. Kolar and T. Friedli, “The essence of three-phase PFC
rectifier systems – Part I,” IEEE Trans. Power Electronics, vol. 28,
no 1, pp. 176-198, Jan. 2013.
[2] T. Friedli, M. Hartmann, and J.W. Kolar, “The essence of
three-phase PFC rectifier systems – Part II,” IEEE Trans. Power
Electronics, vol. 29, no 2, pp. 543-560, Jan. 2014.
[3] M.P. Kazmierkowski and L. Malesani, “Current control
techniques for three-phase voltage-source PWM converters; A
survey,” IEEE Trans. Ind. Electronics, vol. 45, no 5, pp. 691-703,
Oct. 1998.
[4] M. Malinowski and M.P. Kazmierkowski, “Control of threephase PWM rectifiers,” Control in Power Electronics – Selected
Problems, Academic Press, San Diego, CA, 2002.
[5] M. Hartmann, H. Ertl, and J.W. Kolar, “Current control of
three-phase rectifier systems using three independent current
controllers,” IEEE Trans. Power Electronics, vol. 28, no 8, pp.
3988-4000, Aug. 2013.
[6] P.C. Todd, “UC3854 controlled power factor correction circuit
design,” Unitrode Application Note, U-134, pp. 3-269-3-288.
[7] M. Fu and Q. Chen, “A DSP based controller for power factor
correction (PFC) in a rectifier circuit, Proc. Applied Power
Electronics Conf. (APEC), pp. 144-149, Mar. 2001.
[8] C. Qiao and K.M. Smedley, “A general three-phase PFC
controller for rectifiers with a parallel-connected dual boost
topology,” IEEE Trans. Power Electronics, vol. 17, no 6, pp. 925934, Nov. 2002.
[9] S. Hiti, D. Borojević, R. Ambatipudi, R. Zhang, and Y. Jiang,
“Average current control of three-phase PWM boost rectifier,” Rec.
IEEE Power Electronics Specialists Conf. (PESC), pp. 131-137,
Jun. 1995.
[10] K. Zhou and D. Wang, “Relationship between space-vector
modulation and three-phase carrier-based PWM: a comprehensive
analysis,” IEEE Trans. Ind. Electronics, vol. 49, no 1, pp. 186-196,
Feb. 2002.
[11] Powerex: PM50CLA120 Intelligent Power Modules, Data
Sheets, 2009.
[12] Texas Instruments: TMS320F2808 Digital Signal Processor,
Data Manual, 2011.
[13] L. Huber, M. Kumar, and M.M. Jovanović, “Performance
comparison of PI and P compensation in average-current-controlled
three-phase six-switch boost PFC rectifier,” Proc. Applied Power
Electronics Conf. (APEC), pp. 935-942, Mar. 2014.
[14] L. Huber, M. Kumar, and M.M. Jovanović, “Performance
comparison of PI and P compensation in DSP-based averagecurrent-controlled three-phase six-switch boost PFC rectifier,” IEEE
Trans. Power Electronics (paper accepted for publication).
[15] D.M. Van de Sype, K. De Gusseme, A.P.M. Van den Bossche,
and J.A. Melkebeek, “Duty-ratio feedforward for digitally controlled
boost PFC converters,” IEEE Trans. Ind. Electronics, vol. 52, no 1,
pp. 108-115, Feb. 2005.
[16] Powerex: BP7B - L-Series IPM Interface Circuit Reference
Design, Application Notes, 2009.
[17] L. Huber, M. Kumar, and M.M. Jovanović, “Implementation
and performance comparison of five DSP-based control methods for
three-phase six-switch boost PFC rectifier,” Proc. Applied Power
Electronics Conf. (APEC), pp. 101-108, Mar. 2015.
[18] K. Zhou and D. Wang, “Relationship between space-vector
modulation and three-phase carrier-based PWM: a comprehensive
analysis,” IEEE Trans. Ind. Electronics, vol. 49, no 1, pp. 186-196,
Feb. 2002.
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