Three-Step vs Six-Step PWM in Three-Phase Boost PFC Rectifier

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0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Transactions on Power Electronics

Performance Comparison of Three-Step and Six-Step PWM

in Average-Current-Controlled

Three-Phase Six-Switch Boost PFC Rectifier

Laszlo Huber, Misha Kumar, and Milan M. Jovanović

Abstract – In this paper, a three-step PWM method for the

average-current-controlled three-phase six-switch boost PFC

rectifier is proposed. It is shown that the three-step PWM

compared to the conventional six-step PWM exhibits a lower

total harmonic distortion of input currents and higher power

factor. However, the three-step PWM, unlike the six-step

PWM, is adversely affected by duty-cycle limitations and has

unbalanced conduction losses of the upper and lower switches of

the three-phase rectifier bridge. The average-current control

with three-step and six-step PWM is illustrated with

Matlab/Simulink simulation waveforms and experimentally

verified on a 3-kW prototype.

Index Terms –Three-phase six-switch boost PFC rectifier,

average-current control, three-step PWM, six-step PWM,

discontinuous space-vector modulation (SVM), segment

detection, duty-cycle limitation, low-pass filtering and sampling,

zero-sequence signal (ZSS) injection, total harmonic distortion

(THD), power factor (PF)

I. INTRODUCTION

Today, active three-phase PFC rectifiers need to meet very

challenging performance requirements. In the majority of

applications, the input current of active three-phase PFC

rectifiers is required to have a total harmonic distortion

(THD) less than 5% and a power factor (PF) greater than 0.99

[1]. One of the most cost-effective topologies that can meet

these requirements is the three-phase six-switch boost PFC

rectifier [2], which is usually implemented without neutral-

point connection.

A number of control methods that can achieve a high

quality of input currents in the three-phase six-switch boost

PFC rectifier are available [3], [4]. Generally, approaches

using direct control of input current versus, for example,

direct power control, result in better quality of the input

currents [5]. Today, the control circuit is usually

implemented with digital technology. One direct current

control method, well suited for digital implementation, is the

average current control [6], [7].

In three-wire, three-phase applications, because the sum of

the phase currents is zero, the control can be implemented by

having only two out of three current controllers actively

shaping the current at a given time. The desired current in the

inactive-controller phase is obtained by the sum of currents of

the actively controlled phases. One implementation of this

control method is based on dividing the line cycle of the input

phase voltages into six 60o segments (six-step PWM) as

shown in Fig. 1(a) [8], [9]. In each 60o segment, the

controller in the phase with the highest absolute value voltage

is disabled, i.e., switches in the corresponding leg are turned

off, which results in reduced switching losses.

In this paper, another implementation of this control

method is proposed. It is based on dividing the line cycle of

the input phase voltages into three 120o segments (three-step

PWM) as shown in Fig. 2. In each 120o segment, the

controller in the phase with the most positive (or most

negative) phase voltage is disabled, i.e., the switches in the

corresponding leg are turned off. The three-step PWM is

equivalent to the discontinuous space-vector modulation

(SVM) with unbalanced conduction losses between the upper

and lower switches [10].

A detailed performance comparison of the three-step and

six-step PWM in the average-current controlled three-phase

six-switch boost PFC rectifier is also provided in the paper.

It is shown that the three-step PWM compared to the six-step

PWM exhibits lower THD of input currents and higher PF.

The operation of the three-step and six-step PWM is

illustrated with Matlab/Simulink simulation waveforms and

experimentally verified on a 3-kW prototype.

II. AVERAGE CURRENT CONTROL WITH THREE-STEP AND

SIX-STEP PWM

In the six-step PWM, a line cycle of input phase voltages is

divided into six 60o segments such that within a 60o segment

none of the three phase voltages changes sign, as shown in

Fig. 1(a). In each 60o segment, the controller in the phase

with the highest absolute value voltage is disabled, i.e.,

switches in the corresponding leg are turned off. For

example, in segment I, the controller in phase “a” is disabled,

i.e., switches Sap and San are turned off, as shown in Fig. 1(b).

The simplified circuit diagram of the three-phase six-switch

boost PFC rectifier with six-step PWM in segment I is shown

in Fig. 1(c). Since in segment I, the leg in phase “a” is

disabled and phase current ia is positive, rectifier input aR is

connected to the positive output rail (through diode Dap). By

sinusoidal modulation of switches in legs “b” and “c”,

desired sinusoidal average phase-to-phase voltages vaRbR and

vaRcR can be generated between the rectifier inputs,

respectively. As the sum of the phase-phase voltages at the

rectifier inputs must be zero, desired voltage vbRcR is

Transactions on Power Electronics

automatically generated. To generate sinusoidal average

phase-to-phase voltages between rectifier inputs, the current

controllers are designed to control phase-phase currents. The

output of the phase-phase-current controllers determines the

phase-phase duty cycles dab, dbc, and dca so that in steady-state

operation vaRbR=dabVo, vbRcR=dbcVo, and vcRaR=dcaVo. Switch

duty cycles dap, dbp and dcp are obtained from phase-phase

duty cycles so that dab=dap-dbp, dbc=dbp-dcp, and dca=dcp-dap.

For example, in segment I, dap=1 and, therefore, dbp=1-dab and

dcp=1+dca. It should be noted that dap=1 means that rectifier

input aR is connected to the positive output rail due to the

conduction of diode Dap. The steady-state duty cycle of all

switches is summarized in Table I, whereas, the variation of

duty cycle dap during the whole line cycle is shown in Fig. 3

as an example. As can be seen in Fig. 3, duty cycle dap

exhibits abrupt changes at 60o-segment transitions, which

induces input-current transients at the segment transitions.

These transients, which can be seen as notches and glitches in

the input current waveforms and can be regarded as segment-

transition noise, may cause false segment detection in the six-

step PWM.

In the proposed three-step PWM, a line cycle of input

phase voltages is divided into three 120o segments such that

within a 120o segment one phase voltage is always greater or

smaller than the other two phase voltages, as shown in Figs.

2(a) and 2(b), respectively. Accordingly, the three-step

PWM is either referenced to the positive or to the negative

envelope of the phase voltages. In each 120o segment, the

controller in the phase with the most positive (or most

negative) phase voltage is disabled, i.e., the switches in the

corresponding leg are turned off. Similarly to the six-step

PWM, the control goal is to generate sinusoidal average

phase-to-phase voltages between the rectifier inputs aR, bR

and cR, and, therefore, the current controllers are designed to

control the phase-phase currents. The steady-state duty

cycles of the switches operating with three-step PWM

referenced to the positive and negative envelope of the phase

voltages are summarized in Tables II and III, respectively,

whereas, the variation of the corresponding duty cycle dap

during the whole line cycle is shown in Figs. 4(a) and 4(b).

As can be seen in Fig. 4, duty cycle dap does not exhibit

abrupt changes at 120o-segment transitions. As a result, the

three-step PWM exhibits much reduced notches and glitches

at the segment transitions so that segment detection is much

less sensitive to segment-transition noise compared to that in

the six-step PWM.

Comparing duty cycle dap in Figs. 3 and 4, it can be

concluded that practical duty-cycle limitations (in order to

meet the dead-time requirements for the IGBT module and

taking into account the propagation delay times of the

optocouplers in the interface circuit between the DSP and

IGBT module) only affect the three-step PWM. As can be

seen from Fig. 3, for a minimum duty cycle Dmin=0.05 and

maximum duty cycle Dmax=0.95, as an example, the duty-

cycle limitations do not have effect on the six-step PWM

circuit operation because the duty-cycles of the switches in

the two active phases are in the 0.265-0.735 range. In Fig. 3,

when the switches in leg “a” are turned off, dap=1 in segment

I and dap=0 in segment IV is achieved through the conduction

of diodes Dap and Dan, respectively. However, for the three-

step PWM implementation, the limited duty-cycle range

affects circuit operation and its performance. As can be seen

in Fig. 4(a), at the beginning of segment II duty cycle dap is

required to continuously decrease from unity, whereas at the

end of segment III dap is required to continuously increase to

unity. However, if the maximum duty cycle is limited to

v b0

v c0

-30 90 150 210 270 330

I II III IV

V VI

o o o o o o

vb0

bp S

an S

bn S

a>0

DISABLED

PHASE

(a) (b)

(c)

Fig. 1 Six-step PWM: (a) 60o segments, (b) circuit diagram in segment I, (c) simplified circuit diagram in

segment I.

iab

iac

ibc

aRbR

aRcR

bp S

bn S

a>0

vab>0

ac >0

vbc

acaba iii +=

bcabb iii −=

bcacc iii +=

v b0

v c0

0 180 300 360

I II III I

o o o o o

envp

(a)

0 120 360

I II III

o o o 240

v b0

v envn

(b)

Fig. 2 Three-step PWM with 120o

segments referenced to: (a) positive

envelope, (b) negative envelope of input

phase voltages.

Transactions on Power Electronics

Dmax=0.95, the phase current will be distorted at the I-to-II

and III-to-I segment transitions. Similarly, as can be seen in

Fig. 4(b), at the end of segment I duty cycle dap is required to

decrease to zero, whereas at the beginning of segment III dap

is required to increase from zero. However, if the minimum

duty cycle is limited to Dmin=0.05, the phase current will be

distorted at the I-to-II and II-to-III segment transitions.

It should be noted that for both six-step and three-step

PWM, identical operation can be achieved if instead of

phase-to-phase-current controllers, phase-current controllers

are used with appropriate zero-sequence-signal (ZSS)

injection. The implementation with phase-current controllers

and ZSS injection is described in the next section.

III. POWER STAGE AND CONTROL CIRCUIT

The simplified circuit diagram of the three-phase six-

switch boost PFC rectifier is shown in Fig. 5. The switches

are implemented with IGBTs in a six-pack module [11]. The

switching frequency is selected as fsw = 20 kHz, which is the

maximum recommended fsw for the IGBT module. The input

phase voltage range is 120 ± 15% Vrms, 45-65 Hz, the

nominal output voltage is 400 V, and the maximum output

power is 3 kW.

The block diagram of the control circuit common for both

six-step and three-step PWM implemented with phase-phase

current controllers is also shown in Fig. 5. Average-current

control is implemented using digital signal processor (DSP)

TMS320F2808 from TI [12]. For average-current control,

the input phase-phase voltages, phase currents, and the output

voltage are sensed and converted to digital signals through

the 12-bit analog-digital converter (ADC) of the DSP. The

input voltage range of the ADC is 0-3 V, i.e., the full-scale

range FSR = 3 V. As only positive voltages can be applied to

the input of the ADC, the bipolar phase-phase voltages and

phase currents are scaled to ±FSR/2 and level shifted by

FSR/2. The output signals of the DSP are the digital PWM

(DPWM) gate signals for the bottom switches Sxn, xϵ{a,b,c}.

The DPWM operates with a triangular carrier. As the clock

frequency of the DSP is fsysclock = 100 MHz, the peak value of

the triangular carrier is Cpk = 1/2·fsysclock/fsw = 2500. All the

sensed signals are sampled at the peak of the triangular

carrier, i.e., at the middle of the turn-on time of the upper

switches. It should be noted that by sampling the inductor

currents at the middle of the turn-on time of the upper

switches, the sampled values of the inductor currents are

equal to the average values during a switching period. Since

the value of the average inductor current is directly obtained

in each sample, i.e., it is not reconstructed from several

samples, no antialiasing filter is needed for the sampled

inductor currents. Instead, the sensed current signals need to

be conditioned by a low-pass filter to remove the switching

noise. The corner frequency of the input- and output-voltage

antialiasing filters is fAAFin = 3 kHz and fAAFout = 550 Hz,

respectively, whereas the corner frequency of the low-pass

filter of the sensed inductor-currents is fLPF = 92.5 kHz.

The voltage controller is implemented with PI

compensation (for better regulation of the output voltage),

whereas, the current controller is implemented with P

compensation which exhibits better performance compared to

that with PI compensation. Namely, as it was shown in [13],

[14] for the three-phase six-switch boost PFC rectifier with

average-current control and with mismatched input-voltage

and input-current sensing gains, the current controller with P

compensation exhibits lower THD of input currents and

higher PF compared to that of PI compensation. The

average-current control implementation also includes voltage

TABLE I - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR SIX-STEP PWM

60° Segment dap d

an d

bp d

bn d

cp d

I 1 0

1-dab d

ab 1+dca -dca

II -dca 1+dca d

bc 1-dbc 0 1

III 1+dab -dab 1 0

1-dbc d

IV 0 1

-dab 1+dab d

ca 1-dca

V 1-dca d

ca 1+dbc -dbc 1 0

VI dab 1-dab 0 1

-dbc 1+dbc

TABLE II - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR THREE-STEP

PWM REFERENCED TO POSITIVE ENVELOPE OF PHASE VOLTAGES

120° Segment dap d

an d

bp d

bn d

cp d

I 1 0 1-dab d

ab 1+dca -dca

II 1+dab -dab 1 0

1-dbc dbc

III 1- dca d

ca 1+dbc -dbc 1 0

TABLE III - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR THREE-STEP

PWM REFERENCED TO NEGATIVE ENVELOPE OF PHASE VOLTAGES

120° Segment dap d

an d

bp d

bn d

cp d

I -dca 1+ dca d

bc 1-dbc 0 1

II 0 1

-dab 1+dab d

ca 1- dca

III dab 1-dab 0 1

-dbc 1+dbc

-30 90 150 210 270 330

I II III

IV V VI

o o o o o o o

d ab

1 ca

0.735

0.265

0.95

0.05

max

min

Fig. 3 Duty cycle of upper switch in phase “a” for six-step PWM at

120Vrms input voltage.

120 180 240 300 360

I II III

o o o o o o o

1 ca

max

0.95

(

)

ω t

120 240 360

I II III

o o o o

d ab

o 180

o 300

min

0.05

(b)

Fig. 4 Duty cycle of upper switch in phase “a” for three-step PWM

referenced to: (a) positive envelope, (b) negative envelope of input phase

voltages (120Vrms).

Transactions on Power Electronics

feedforward (VFF) [6] and duty-cycle feedforward (DFF)

[15]. Generally, VFF can make the output voltage practically

insensitive to line-voltage variations. However, VFF with P-

compensated current controller is effective only if DFF is

also implemented, as shown in [13], [14].

The 60o-segments for six-step PWM are detected by using

comparators to determine the sign of the phase voltages,

whereas, the 120o-segments for three-step PWM are detected

by comparing the phase voltages. Because in the six-step

PWM strong transient input-current noise is generated at 60o-

segment transitions, additional measures are taken to improve

the reliability of the 60o-segment detection. First, the

segment detection is disabled if the absolute value of the sum

of the sensed and sampled phase voltages is significantly

greater than zero, i.e., if |va0+vb0+vc0| > ΔVzero. Second, after

a new segment is detected, the segment detection is disabled

for a specified blanking time Tblank to prevent noise-induced

segment change due to false segment detection. In the

experimental circuit, the segment detection is implemented

with ΔVzero = 13V and Tblank = 9Tsw = 450 μs.

It should be noted that in order to meet the dead-time

requirements for the IGBT module [11] and taking into

account the propagation delay times of the optocouplers in

the interface circuit between the DSP and IGBT module [16],

the duty cycle range is limited from Dmin=0.05 to Dmax =0.95.

The block diagram of the control circuit common for both

six-step and three-step PWM implemented with phase-

current controllers and ZSS injection is shown in Fig. 6. ZSS

signal vZSS for the six-step PWM, shown in Fig. 7, is obtained

from the input phase voltages and the output reference

voltage as











<−−

≥−

envnenvpenvn

oref

envnenvpenvp

oref

ZSS vvifv

vvifv

2 , (1)

while ZSS signals for the three-step PWM referenced to the

positive and negative envelope of input phase voltages,

shown in Figs. 8(a) and (b), respectively, are defined as

envp

oref

ZSS v

v−= 2

, (2)

and

envn

oref

ZSS v

v−−= 2

. (3)

It can be observed in Figs. 7 and 8 that the sum of phase

voltage va0 and ZSS voltage vZSS, when divided by Voref and

level shifted by ½ will result in the same duty cycle dap as

obtained with the phase-phase-current controllers shown in

Figs. 3 and 4, respectively.

Finally, it should be noted that both the six-step PWM and

three-step PWM implemented with phase-current controllers

and ZSS injection can be equivalently implemented with

space vector modulation with appropriate distribution of the

zero switching state vectors [17], [18].

IV. PERFORMANCE COMPARISON OF THREE-STEP AND SIX-

STEP PWM

Figures 9(a) and (b) show the measured steady-state

waveforms of phase currents ia, ib, and ic at nominal phase

voltage of 120 Vrms and for 2-kW load for the six-step and

three-step PWM referenced to the negative envelope of the

phase voltages, respectively. As can be seen in Figs. 9(a) and

(b), for both six-step and three-step PWM, the phase currents

LINE VOLTAGE

SENSING

PHASE CURRENT

SENSING

OUTPUT VOLTAGE

SENSING

Sap Sbp Scp

San Scn

Sbn

ANT IALIASING

FILTER

LOW-PASS

FILTER

ANTIALIASING

FILTER

Phase-Phase AB

ADC

FSR

ADC

A C

v caSh

v abSh

FSR

ab AVG

DPWM

an Sap

ADC

VOLTAGE

CONT ROLLER

oref

vEA

K AB

1.5V

i abref

aSh

FSR

CURRENT

CONT ROLLER

Offset Offset

1.5V

bSh

STEP

LOGIC

FSR

SEGMENT

DETECT ION

SEG *

SEG*

DUTY-CYCLE

FEEDFORWARD

oref

VOLTAGE

FEEDFORWARD

DSP

Phase-Phase BC

Phase-Phase CA

* - notation for digital values

Fig. 5 Simplified circuit diagram of power stage (La=Lb=Lc=1mH, Cp=Cn=2240µF) and

block diagram of control circuit.

Fig. 6 Block diagram of control circuit for implementation of six-

step and three-step PWM with phase-current controllers and ZSS

injection.

Phase A

VOLTAGE

CONTROLLER

ADC

FSR

ADC

Phase B

Phase C

oref

vEA

i aref

aK AB

v ca

v ab

ADC

FSR

a0 AVG

CURRENT

CONT ROLLER

DPWM

Sap

vZSS

ZSS INJECTION

DUTY-CYCLE

FEEDFORWARD +

ZSS

* v*

oref

GENERATOR

ZERO-SEQUENCE

SIGNAL (ZSS)

vZSS

FSR

Dan

DCCa

Transactions on Power Electronics

are distorted at segment transitions. However, these

distortions are more pronounced for the six-step PWM.

Consequently, the six-step PWM has higher THD of phase

currents and lower PF compared to the three-step PWM, as

shown by respective THD and PF measurements in Figs. 9(a)

and (b).

The phase-current distortions at segment transitions are

primarily caused by the low-pass filtering and sampling of

the inductor currents. In the three-step PWM, they are also

affected by duty-cycle limitations.

To explain the distortions in the phase currents caused by

the low-pass filtering and sampling, Simulink simulations are

employed. Specifically, simulations for the six-step and

three-step PWM were performed for a decreased low-pass

corner frequency of 20 kHz, instead of 92.5 kHz used in the

experimental circuit, to amplify the effect of the low-pass

filtering for the sake of a more clear explanation. The

simulations were done without limiting the duty cycle, i.e., by

allowing the full duty-cycle range from zero to unity. The

effect of a limited duty-cycle range is addressed by a separate

set of simulations.

The results of the simulations are presented in Fig. 11,

which shows the sampled inductor-current waveforms before

and after the filtering. Specifically, in Figs. 11(c) and (e), the

waveforms of the sampled filtered and unfiltered inductor

current for the six-step and three-step PWM are compared,

respectively. The definition of sampled filter inductor current

xfs

, xϵ{a,b,c}, and sampled unfiltered inductor current I

xϵ{a,b,c}, is given in Fig. 10.

As it can be observed in Fig. 11(c) for the six-step PWM,

in every 60

-segment, the sampled filtered inductor currents

in two actively controlled phases are greater than the

corresponding sampled unfiltered inductor currents. For

example, in the highlighted 60

-segment in Fig. 11(c), I

afs

and I

cfs

. To facilitate the understanding of this effect, the

waveforms of input phase voltages v

, xϵ{a,b,c}, and

inductor currents of phase “a”, i.e., i

, i

afs

, and i

in Figs.

11(a)-11(c) are zoomed in around instant T

, where sampled

currents i

and i

afs

have a negative slope, and instant T

where sampled currents i

and i

afs

have a positive slope, as

shown in Figs. 12(a) and 12(b), respectively. As can be seen

in Fig. 12, filtered inductor current i

lags behind inductor

current i

. At the sampling instant (at the middle of a

switching period, i.e., at the middle of the turn-on time of the

upper switches), i

> i

, and, therefore, the sampled filtered

inductor current is greater than the sampled unfiltered

inductor current, i.e., i

afs

The current controllers shape the sampled filtered-inductor

currents to follow the reference currents so that i

afs

bfs

cfs

=0.

At the same time, the sum of the three phase currents flowing

in the circuit must be zero, i.e., the sum of the sampled

unfiltered-inductor currents is also zero i

=0.

Therefore, if i

afs

and i

cfs

, it follows that i

bfs

< i

, as

shown in Fig. 11(c). Since the current in the phase of non-

active (passive) controller is greater than the actively-

controlled phase currents, at the 60

-segment transitions

when the role of actively and non-actively controlled currents

changes, the current of the phase transitioning to passive

control and the phase transitioning to active control exhibit

step changes. These current changes at the 60

-segment

transitions are primarily responsible for increased current

THD.

At 120

-segment transitions of the three-step PWM, the

difference between sampled filtered and sampled unfiltered

Fig. 7 ZSS signal for six-step PWM.

[ωt]

ZSS

ore

−

ore

−

(a)

(b)

Fig. 8 ZSS signal for three-step PWM referenced to: (a) positive envelope,

(b) negative envelope.

[ωt]

ZSS

ore

−

0π

[ωt]

vZSS

Va0

ZSS

Va0

ore

−

Fig. 9 Experimental waveforms during steady-state operation (120Vrms,

2kW): phase currents I

, I

[A] with

(a) six-step PWM, (b) three-step

PWM referenced to negative envelope of input phase voltages.

THDa=8.52%

PFa=0.9926

THDa=3.79%

PFa=0.9982

THDb=3.29%

PFb=0.9976

THDc=3.56%

PFc=0.9976

THDb=6.83%

PFb=0.9926

THDc=8.19%

PFc=0.9923

(a)

(b)

Ia Ic

1 / 8 100%

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