Transactions on Electrical and Electronic Materials
1 3
design (TCAD) simulator. These models contain two com-
ponents near the conduction band minimum (CBM) states,
gA
(E)
and (
(E
) that are known as conduction band-
tail and gaussian-distributed donor-like, respectively. So, to
investigate the (DOS) components effect on the subthreshold
region data ((Vth), (SS), and (Ion/Ioff)). A study of the model
tail acceptor density (
) and tail acceptor energy (
) for
the conduction band-tail
g
(E)
on one hand, and donor
Gaussian energy (
) and donor Gaussian distribution (
)
for the gaussian-distributed donor-like (
(E
) on the other
hand, is required since the mathematical (DOS) models are
an exponential function.
2 Experimental Methods
The schematic structure of the (a-IGZO TFT) is a bottom-
gate staggered structure. The device is composed of a heav-
ily doped
silicon wafer that acts as a gate, and a
100nm of (SiO2) layer placed on top of it that is used as a
gate insulator. Also, a 20nm thick (a-IGZO) active layer was
deposited on the unheated (SiO2) layer. Finally, the (Au/Ti)
stacked layer
thick was deposited as the source
and drain electrodes. Noting that the channel width (W) and
length (L) are 180μm, 30μm, respectively.
For the operation of a thin film transistor, the following
standard Eqs.(1)–(3) are used [15, 16]. The threshold volt-
age (Vth) and field-effect mobility (µsat) were extracted from
the expression of the operation of a field-effect transistor,
which is a function of the capacitance and applied voltage:
where Ids is the drain current, (W) is the channel width, (L)
is the channel length, (Vgs) is the gate voltage, (Vds) is the
drain bias voltage, (Cox) is the capacitance per unit area of
the gate insulator, and (Vth) and (µsat) are the threshold volt-
age and Saturation mobility that were extracted from the
linear fit of Eq.1.
Subthreshold swing (SS) is a gate voltage required for the
decade increase in drain current at a constant drain voltage.
Typically, the (SS) of an (a-IGZO TFT) is in the range of
0.2–0.5V/decade [17], and it can be further reduced to be
lower than 0.1V/decade by, for example, reducing the chan-
nel bulk trap density, applying high-K dielectrics, or adopt-
ing fully depleted states. Subthreshold swing is obtained
from the equation given below:
The (SS) was also extracted from the subthreshold region
data at the maximum slope point using Fig.4 transfer
(1)
DS =
Cox 𝜇sat
VGS −Vth
,VDS ≥VDS −V
(2)
=
gs
𝜕
logI
Vds =
characteristics in the logarithmic scale. Saturation mobil-
ity is defined based on how quickly an electron can move
through the active layer, which is obtained by the following
equation:
2.1 2D Numerical Simulation
The two-dimensional cross-section along the channel of
the (a-IGZO TFT) structure used in this work is shown in
Fig.1. It is designed to match with the actual (TFT) used in
this study. The structure consists of a 20nm thick (a-IGZO)
channel layer, a heavily doped n-type poly-silicon substrate
that also acts as a gate, a 100nm thick gate insulator (SiO2)
layer, and drain and source Ohmic contacts that are the low
resistance (Au/Ti)
thick stacked layer. The channel
width (W) is 180μm, and the channel length (L) is 30μm,
respectively.
Contacts between (S/D) electrodes and the (a-IGZO)
layer are both assigned as Schottky in this work. The (S/D)
metal work function (
and the electron affin-
ity of (a-IGZO)
𝜒
were included in the calculation.
Both thermionic emission and tunneling current were con-
sidered [18].
𝜒
is estimated from a simple linear
relation between electron affinities of its three elementary
compounds.
where a, b, and c are molar percentages.
𝜒
was cal-
culated to be 4.16eV. Throughout this paper, the Schottky
contact model is used as a default in numerical simulation.
The channel is made of (a-IGZO) which is an amorphous
n-type semiconductor. Disordered materials [like a-Si and
(a-IGZO)] contain a large number of defect states continu-
ously distributed within the bandgap of the material. The
(3)
sat =⎡
d√Ids
dVgs
1
CiW
2L
⎤
(4)
=a
𝜒
+b
𝜒
+c
𝜒
Fig. 1 Structure of an a-IGZO TFT in a bottom gate (top-contact)
staggered configuration