EPE Journal European Power Electronics and Drives ISSN: 0939-8368 (Print) 2376-9319 (Online) Journal homepage: http://www.tandfonline.com/loi/tepe20 Control with high performances based DTC strategy: FPGA implementation and experimental validation Saber Krim, Soufien Gdaim, Abdellatif Mtibaa & Mohamed Faouzi Mimouni To cite this article: Saber Krim, Soufien Gdaim, Abdellatif Mtibaa & Mohamed Faouzi Mimouni (2018): Control with high performances based DTC strategy: FPGA implementation and experimental validation, EPE Journal, DOI: 10.1080/09398368.2018.1548802 To link to this article: https://doi.org/10.1080/09398368.2018.1548802 Published online: 27 Nov 2018. Submit your article to this journal View Crossmark data Full Terms & Conditions of access and use can be found at http://www.tandfonline.com/action/journalInformation?journalCode=tepe20 EPE JOURNAL https://doi.org/10.1080/09398368.2018.1548802 ARTICLE Control with high performances based DTC strategy: FPGA implementation and experimental validation Saber Krima, Souﬁen Gdaimb, Abdellatif Mtibaab and Mohamed Faouzi Mimounia a Research Unit of Industrial Systems study and Renewable Energy, National Engineering School of Monastir, University of Monastir, Monastir, Tunisia; bLaboratory of Electronics and Microelectronics, Faculty of Sciences, University of Monastir, Monastir, Tunisia ABSTRACT KEYWORDS This paper aims to improve the induction motor performances using a modiﬁed Direct Torque Control (DTC). The DTC is featured by its simple structure and fast dynamic response. Also, it does not require a speed sensor and it is less dependent on the motor parameters. However, the basic handicaps of this method are the torque ripples and the current distortions due to the presence of the hysteresis controllers. This paper aims; ﬁrstly, to replace the hysteresis controllers and the switching table by a fuzzy logic system in order to overcome these handicaps. Furthermore, the sampling frequency is another parameter which must be investigated to reduce the commutation losses and the harmonic stator current waves. The second purpose of this paper is to reduce the execution time using a Field Programmable Gate Array (FPGA). The FPGA is able to execute the Fuzzy DTC (FDTC) with a higher sampling frequency, thanks to its parallel processing relative to the Digital Signal Processor (DSP). The FDTC model is veriﬁed by simulation using system generator tool and validated by experimentation utilizing an FPGA Virtex 5. Thus, excellent performances at low processing time are obtained using the Xilinx FPGA Virtex 5. Direct torque control; fuzzy logic system; real time; Xilinx system generator; Field Programmable Gate Array (FPGA) 1. Introduction Recently, Induction Motors (IMs) are the most used motors in industrial applications thanks to theirs simple design, low maintenance, low cost, and it operates in open loop . Day by day, the basic Direct Torque Control (DTC) is becoming more popular in the industrial world thanks to its simple structure, its robustness under motor parameter variation and its rapid dynamic response, and because it does not require a speed sensor [2–4]. Since its invention, the basic DTC is counted as the most eﬃcient approach for controlling the induction motor . Despite of the cited advantages, the basic DTC produces a torque and a ﬂux with high ripples, and a stator current with high distortions, which aﬀect the stator winding and reduce the motor service life. The conventional DTC can be improved utilizing the Space Vector Modulation (SVM) and discrete space vector modulation techniques, as given in [6–12]. In this case, it is possible to apply the required stator voltage vector and guarantee an operation with constant switching frequency, which consequently reduces the ripples and the commutation losses. However, in these methods accurate design of Proportional Integral (PI) controllers for the torque and the ﬂux is required which aﬀects the system robustness, the stability and the dynamic of the control system, due to the variation of the induction motor CONTACT Saber Krim [email protected] Monastir, University of Monastir, Tunisia © 2018 European Power Electronics and Drives Association parameters and the external disturbances. Others researchers have associated the DTC-SVM and the multilevel inverter to control the switching frequency of the inverter and reduce the ripples [9,13–20]. The main technologies of the multilevel inverter used in the industrial applications are the Neutral Point Clamped (NPC) [17,18], the Flying Capacitors (FC) , and the Cascaded H-Bridge (CHB) [9,20]. Yet, using the multilevel inverter, switching losses increases, the reliability decreases and the price of the system increases. Other studies for the DTC have been developed, such as the combination between the DTCSVM and the predictive control , to control the switching frequency and select the desired voltage vector. This method provides a signiﬁcant improvement in terms of ripples. Nevertheless, in this case the algorithm is based on a complex mathematical model that depends on several machine parameters. In recent works a combination between the DTC-SVM and sliding mode controllers is developed to reduce the ripples, improve the system robustness and reject perturbations [7,22,23]. However, the main problem in these controllers is the chattering phenomenon, due to discontinuous nature of the control law which introduces a persistent static error and the need for knowledge of the system dynamics. In addition, the sliding mode controllers are diﬃcult in design and tuning. In recent years, the artiﬁcial intelligent techniques like the Research Unit of Industrial Systems study and Renewable Energy, National Engineering School of 2 S. KRIM ET AL. fuzzy logic and neural networks have gained more importance to improve the electrical system performances. In order to improve the conventional DTC performances, few researchers have used the fuzzy logic and sliding mode fuzzy to improve the conventional DTC performances by replacing the PI controller by an intelligent controller, as given in [24,25]. In these works, the speed transient response is improved but the torque ripples are not much reduced. Improvements in the DTC performances using neural networks based switching controller is developed in some researches works, as given in . The drawback of Artiﬁcial Neural Network (ANN) based switching controller is that it doesn’t give heuristic knowledge of process in selection of optimal switching voltage vector; in addition the control algorithm is complex and requires a processor with high computation power. To overcome the limitations of all the cited control strategies, the fuzzy logic can be used to improve the nonlinear system performances. The fuzzy logic process is easy to understand due to its simple logical structure and inference mechanism. In fact, the conventional DTC uses two hysteresis controllers to control the torque and the stator ﬂux. These controllers generate two states, which produce the same results for the small and the big error of the torque and the stator ﬂux. As consequence, the generated switching states of the inverter cannot produce the best voltages vectors to make the ﬂux and the torque errors both zero. This leads in ripples of torque and ﬂux [27–29], and variations of the switching frequency . In paper , the authors present an analysis of the switching frequency variation which is caused by the hysteresis band, the motor speed and torque slope. These ripples can be reduced if the torque and ﬂux errors are subdivided into several smaller subsections on which different control action is taken. However, it is hard to obtain the optimal subsection boundaries for the torque and ﬂux errors. Furthermore, the torque ripples are aﬀected by the width of the torque hysteresis band . These ripples change proportionally with the variations in hysteresis bandwidth of the torque. However, due to the discrete nature of the control system, there might be still ripples even with the zero bandwidth of the hysteresis controller. In addition, if the bandwidth decreases, the inverter switching frequency increases, which consequently increases the switching losses in the semiconductors. To solve this problem the bandwidth of the torque hysteresis controller must be optimized in order to keep the ripple level and switching frequency variations within acceptable limits. Therefore, the Fuzzy Logic Control (FLC) based on the language rules can be used to adapt the torque hysteresis band in order to reduce the torque ripples and provide a precise speed response by selecting the suitable voltage vector [33–35]. The Fuzzy logic uses the people’s experience knowledge to release the rule base and it is based on intuition and simulation . The FLC is not based on the IM model and its parameters. It is more suitable for the imprecise processes and does not require any mathematical models. Also, the FLS is a more eﬀective technique when the system is based on a severely nonlinear mathematical model . The FLC has been proposed in several researches work to select the optimal voltage vectors in conventional DTC [38–41] and to solve the problem of variable switching frequency [42,43]. Other researchers have used the fuzzy logic in speed control and ﬂux observer to improve the electrical motors performances [44–47]. In addition, the fuzzy logic is used in some research works to improve the DTC performances and to reduce the commutation losses in the inverter, as given in [48–50]. In paper , the authors presented a fuzzy logic controller associated to the DTC of PMSM to reduce the ripples and the switching losses in the inverter by arranging the inverter switching. In paper [49,50], the authors present a combination between the DTC and the fuzzy logic control in order to provide an operation with low ripples and to keep the switching losses at an acceptable level, by selecting a suitable voltage vector for each sampling period. This demonstrates that utilizing the fuzzy logic technique, it is possible to improve the DTC performances by reducing the ripples of the inverter losses. The ﬁrst contribution in this paper is oriented toward the use of a Fuzzy Logic System (FLS) to replace the switching table and the hysteresis controllers, in order to reduce the torque and the ﬂux ripples, as well as the stator current distortions. The design with the XSG tool and the hardware implementation on the FPGA of the proposed Fuzzy DTC (FDTC) control strategy is the second contribution in this paper. In this study, the torque and the ﬂux errors and the stator ﬂux vector position are fuzziﬁed into several fuzzy subsets in order to select a more suitable space voltage vector to smooth the torque and the ﬂux ripples and control the switching frequency variations. With the proposed method, the transistors are only switched when it is needed which consequently reduces the inverter switching losses. The Fuzzy rule base provides precise control by selecting optimal switching state of the inverter in order to meet required torque and ﬂux demand by the induction motor. The performance of the proposed method has been veriﬁed by digital simulation utilizing the Matlab/Simulink environment and the Xilinx System Generator (XSG) tool, and experimental validation using an FPGA Virtex 5 and a squirrel cage induction motor. Traditionally, two main families of digital devices are used to control the induction motor drive. The ﬁrst family integrates the microcontroller (STM32F3, STM32F4, STM32F1. . .) [51,52] and the Digital Signal Processor (DSP) [53–55] which can be JOURNAL: EUROPEAN POWER ELECTRONICS AND DRIVES programmed with ‘C code’ or a graphical programming approach MATLAB/Simulink . The second family integrates the Field Programmable Gate Array (FPGA) device (FPGA)  which can be programmed with VHSIC Hardware Description Language (VHDL) or Verilog code. However, the limitation factor of the STM microcontrollers is the computing power and the processing speed which depends of the algorithm complexity, this limit allows ﬁxing an important sampling period which creates delays in the control loop. The DSPs controllers’ devices are considered as an appropriate solution in electrical drives applications  which integrate a high-performing processor core based on a hardware accelerator computing block and few peripherals to communicate with the external environment. It should be noted that the sampling frequency of the processor depends on the computational burden due to the serial processing, which consequently creates delays in the feedback loop and reduces the control algorithm performances. In fact, if the sampling time increased, the torque and ﬂux ripples and the stator current harmonic waveforms increased [59,60]. For the conventional DTC algorithm, generally the sampling frequency of the DSP (DSPACE 1104 based on a DSPTMS320F240) can reach up to 20 kHz . However, this sampling frequency is still insuﬃcient for the hysteresis controllers operations to reach the same performances provided by the analogue control solutions, such as the accuracy and the absence of the delays in the feedback loop. To overcome the DSP limitation, a combination between the DSP and the FPGA has been developed by some researchers to reduce the calculation burden of the DSP, by distributing some algorithm tasks to the FPGA [62,63], thus the sampling period is minimized and the ripples are reduced. However, this is not a solution for commercialization, due to the complexity of the interfacing circuits and the high cost. To overcome these limitations, the FPGA can be chosen as an alternative solution to control the induction motor with shorter execution time, which can be beneﬁcial in high performance applications. In this paper, the DTC based on a FLS, referred to as Fuzzy-DTC (FDTC) can be considered as a complex control algorithm that requires a digital device with a high computation power. Recently, several researchers have used the software solutions like the DSP (e.g. dSPACE 1104) to control the electrical motor [61,64,65]. However, the main limitation factor of these solutions is that the processing speed depends on the complexity of the algorithm by adopting a serial processing . In this context, other researchers have explored utilizing the FPGA to overcome the DSP limitation [60,66– 68]. In this work, the FPGA is chosen, thanks to its parallel processing. Thus, using the FPGA it is 3 possible to implement more complex algorithms with a low execution time and a smaller sampling period which can reach up to 200 kHz . Conﬁguring an FPGA, a bitstream ﬁle is required, which can be generated using a VHDL or Verilog code. On the other hand, programming the VHDL or Verilog is diﬃcult and requires a lot of prototyping time. To overcome this problem, a Xilinx System Generator (XSG) toolbox is used in this work to automatically generate the VHDL (or Verilog) code and the bitstream ﬁle [69,70]. The XSG is a toolbox integrated into a Simulink environment, developed by Xilinx and featured by its simplicity and rapid implementation time . In this paper, the DTC based on the fuzzy logic control has been developed, designed from the XSG tool, veriﬁed by digital simulation and experimental validation utilizing an FPGA Virtex 5. The rest of the paper is structured as follows: The basic DTC principle is detailed in section 2. The proposed FDTC is developed in section 3. In section 4, the design, the digital simulation, and hardware implementation on the FPGA of the basic DTC and the FDTC are presented. A comparative study between the basic DTC and the FDTC is shown in section 5 by experimental results. Finally, a conclusion is presented in section 6. 2. Basic DTC principle In the Concordia reference (α, β), the IM model can be described as follows: 8 dφsα > > > dt ¼ vsα Rs isα > > > < dφsβ ¼ vsβ Rs isβ dt (1) dφrα > ¼ Rr irα ωφrβ > > dt > > > : dφrβ dt ¼ Rr irβ þ ωφrα where ● ðvsα ; vsβ Þ; ðφsα ; φsβ Þ; ðφrα ; φrβ Þ and ðisα ; isβ Þ: are the components of the voltage, the stator ﬂux, the rotor ﬂux and stator current respectively, in the Concordia reference (α, β). Rs ; Rr and ω: are the stator resistance, the rotor resistance and the motor speed. The mechanical motor behavior is described as follows: ( dΩ J dt ¼ Te Tl f Ω (2) Tem ¼ 32 Np φsα isβ φsβ isα where ● Te and Tl are the electromagnetic torque and the load one. J; f and Np are rotor inertia, 4 S. KRIM ET AL. viscous friction coeﬃcient, and the number of pole pairs. The basic idea of the DTC method is to control the stator ﬂux and the electromagnetic torque simultaneously through the selected voltage vector for each sampling time. The basic DTC diagram is given in Figure 1 [2,4,5]. where the components φsα and φsβ are represented by the following equations: ð 8 > < φsα ¼ ðvsα Rs isα Þdt ð (3) > : φ ¼ vsβ Rs isβ dt sβ The components ðvsα ; vsβ Þ are expressed as: According to Figure 1, the torque and the ﬂux are both controlled by two hysteresis controllers. Indeed, the torque and ﬂux errors present the hysteresis controller inputs. These controllers present in their outputs two logical decisions ðKφ and KT Þ. To determine the position where the stator ﬂux vector is located, the following equation can be used: φsβ θs ¼ arctg (4) φsα The basic DTC consists in subdividing the Concordia (α, β) reference in six sectors (sector 1 to sector 6); each sector is deﬁned by an angle of 60° as given by Figure 2 [2,4]. The diﬀerent sectors and voltagevector positions are illustrated in Figure 2. Figure 1. Block diagram of the basic DTC. As presented in Figure 1, the voltage vector is selected through the hysteresis controller’s decisions ðKφ ; KT Þ and the position of the stator ﬂux vector (N), utilizing the switching Table . 3. Proposed approach: fuzzy direct torque control (FDTC) 3.1. FDTC principle The real problem of the basic DTC is that the torque and the ﬂux are known by high ripples because of the poor choice of a voltage vector for each sampling time. These ripples are caused by the hysteresis controllers and the switching table, which are replaced by a fuzzy approach. The fuzzy logic is able to generate the desired voltage vector, which consequently reduces the ripples. The FDTC diagram of an induction motor is illustrated in Figure 3. In order to get a control with high performances, a Fuzzy Logic System (FLS) is used to replace the hysteresis controllers and the switching table, as illustrated in Figure 3. The FLS has three inputs and one output. The ﬂux error, the torque error and the angle θS (stator ﬂux vector position) are the FLS inputs. The voltage vector Vi is the FLS output. The FLS is based on three steps : i) the fuzziﬁcation step consists in to converting input analogue variables into fuzzy variables, ii) a base of rules which is based on the fuzzy rules and describes the functionality of the fuzzy system—in this step we have found also a fuzzy inference engine which associates the inputs variables with fuzzy rules, iii) the defuzziﬁcation is JOURNAL: EUROPEAN POWER ELECTRONICS AND DRIVES β V3 (0 1 0) V2 (1 1 0) 3 Sector 1 2 α 1 4 V1 (1 0 0) V4 (0 1 1) 6 5 V5 (0 0 1) V0 (0 0 0)/ V7 (1 1 1) V6 (1 0 1) Figure 2. Sectors and voltage vectors. the ﬁnal step of the reasoning fuzzy system, which consists in converting the fuzzy output to a real variable usable to control the system. 3.2. Fuzzy variables The performance of the FLS is inﬂuenced by the shape of the membership function, the fuzzy reasoning, and the defuzziﬁcation method. In this work, symmetric triangular and trapezoidal membership functions were choosing. The shape of these membership functions reduces the complexity of the FLS, the sampling time of the system and the used resources from the FPGA. Thanks to its simplicity, the shape of these membership functions is used in several research works [73– 75]. The widths of the membership functions can be chosen by the experience of the designer and Figure 3. FDTC diagram. 5 optimized by simulations under diﬀerent conditions of speed and torque. As presented in Figure 4, the stator ﬂux error is described by an overlapping of three fuzzy sets named as: Positive (P), Zero (Z) and Negative (N). In this ﬁgure it can be noticed that the membership function of the stator ﬂux error is described by an isosceles triangle for the ‘Z’ fuzzy sets and two trapezoidal functions for ‘P’ and ‘N’ fuzzy sets. where F1 = –F2 = 0.024Wb. As presented in Figure 5, the torque error is described by an overlapping of ﬁve fuzzy sets named as: Positive Large (PL), Positive Small (PS), ZE, Negative Small (NS) and Negative Large (NL). The membership functions of the torque error is described by three isosceles triangles for the PS, ZE and NS fuzzy sets and two trapezoidal functions for PL and NL fuzzy sets, as shown in Figure 5. In this paper the widths of the membership functions can be chosen by the experience of the designer and optimized by simulations under diﬀerent conditions of speed and torque. In fact, the parameters F1, F2, T1 and T2 are chosen by intuition and simulations. After determining the suitable value of these µϕ N 1 Z P eϕ (Wb) F2 0 F1 Figure 4. Fuzzy membership functions of ﬂux error eφ. 6 S. KRIM ET AL. μc NL 1 NS ZE PS PL eT (N.m) -1 T2 0 T1 1 Figure 5. Fuzzy membership functions of torque error eTem. twelve fuzzy sets for the ﬂux vector position. The combination between these fuzzy sets provides 180 fuzzy rules (3*5*12 = 180). The fuzzy rules are archived in the following Table 1: Each control rule is based on three fuzzy-set inputs, as given by the following equation that describes the ﬁrst fuzzy rules R1. R1 : Ifðeφ is PÞ & ðeT is PLÞ & ðθS is θi Þ then ðVi is V1 Þ where T1 = –T2 = 0.52Nm. (5) parameters, we have generated the VHDL code and then the Bitstream ﬁle which is used for the conﬁguration of the FPGA in the experimental step. The universe of discourse of the stator ﬂux vector position is equal to 360° ([0,2π]). In the basic DTC, this position is divided into six sectors. For more precision, the universe of discourse is divided into 12 fuzzy sets (ϴ1 to ϴ12). The membership functions are presented by 12 equidistant isosceles triangles, as shown in Figure 6. As illustrated in Figure 7, the FLS output is described by eight singletons, which are eight voltage vectors Vi (i = 0. . .7), two zero vectors and six active vectors. 3.3. Fuzzy control rules The fuzzy controller behaviour is described by the rules base which reﬂects the knowledge acquired by the human operator that manipulates the process to be controlled . The fuzzy control rules can be synthesized by the extending of the diagram presented in Figure 3 into 12 sectors. The FLS has three inputs which are presented by Figures 4–6. These inputs are described by three fuzzy sets of the ﬂux error, ﬁve fuzzy sets of the torque error and 3.4. Fuzzy inferences The fuzzy inference method used in this paper is based on the Min-Max decision which is proposed by MAMDANI. This method realizes the logic operator ‘&’ with the Minimum (Min) function. Also, the conclusion ‘then’ of each fuzzy rule is realized by the ‘Min’ function. Considering the following fuzzy rule: Ri : If ðeφ is Xi Þ & ðeT is Yi Þ & ðθS is θi Þ then ðV is Vi Þ (6) where Xi, Yi, and ϴi are the fuzzy set of the inputs variable eφ, eT and θ respectively. Vi and Ri are the fuzzy singleton of the output and fuzzy rule number i. The membership functions of the variables X, Y, ϴ and V are given by μX, μY, μϴ and μV respectively. The weighting factor δi for the ith fuzzy rule can be decided utilizing the ‘Min’ operator, as given by the following equation: δi ¼ min ðμXi ðeφÞ; μYi ðeT Þ; μΘi ðθÞÞ (7) μ0Vi ðvÞ ¼ max δi ; μVi ðvÞ (8) 3.5. Deﬀuziﬁer The defuzziﬁcation is the ﬁnal step of the FLS. With this step, the return to the output real values (V0 to Table 1. Fuzzy control rule table. θS eᵠ P Figure 6. Fuzzy membership functions of angle θS . Vi (Sa Sb Sc) V2 V3 V4 V5 V6 V7 V0 V1 (000) (100) (110) (010) (011) (001) (101) (111) Z 1 N 0 1 2 3 4 5 6 Figure 7. Fuzzy membership functions of output. 7 eT PL PS Z NS NL PL PS Z NS NL PL PS Z NS NL θ1 V1 V2 V0 V6 V6 V2 V2 V7 V7 V5 V2 V3 V0 V4 V5 θ2 V2 V3 V7 V1 V6 V2 V2 V0 V0 V6 V2 V3 V7 V5 V5 θ3 V2 V3 V7 V1 V1 V3 V3 V0 V0 V6 V3 V4 V7 V5 V6 θ4 V3 V4 V0 V2 V1 V3 V3 V7 V7 V1 V3 V4 V0 V6 V6 θ5 V3 V4 V0 V2 V2 V4 V4 V7 V7 V1 V4 V5 V0 V6 V2 θ6 V4 V5 V7 V3 V2 V4 V4 V0 V0 V2 V4 V5 V7 V1 V2 θ7 V4 V5 V7 V3 V3 V5 V5 V0 V0 V2 V5 V6 V7 V1 V1 θ8 V5 V6 V0 V4 V3 V5 V5 V7 V7 V3 V5 V6 V0 V2 V1 θ9 V5 V6 V0 V4 V4 V6 V6 V7 V7 V3 V6 V2 V0 V2 V3 θ10 V6 V1 V7 V5 V4 V6 V6 V0 V0 V4 V6 V2 V7 V3 V3 θ11 V6 V1 V7 V5 V5 V1 V1 V0 V0 V4 V1 V1 V7 V3 V4 θ12 V1 V2 V0 V6 V5 V1 V1 V7 V7 V5 V1 V1 V0 V4 V4 JOURNAL: EUROPEAN POWER ELECTRONICS AND DRIVES V7) is realized. The membership functions of the output voltage vectors are illustrated in Figure 7. The diﬀerent used defuzziﬁcation methods are the ‘centre of gravity method’, which is characterized by its complexity. Another method named ‘Max method’ is chosen in this paper thanks to its simplicity, which is given in Equation (9). Utilizing this method, the maximum value of fuzzy output can be decided and used as control output. 8 μV 0 output ðVÞ ¼ Maxðμ0Vi ðvÞÞ i¼1 (9) The fuzzy logic system is illustrated by the following diagram in Figure 8. The combination between the inputs generates more than one fuzzy rule. Each fuzzy rule generates a signiﬁcant control action depending on the input variables. Finally, the defuzziﬁcation is applied to determine the control output. Figure 8. FLS diagram. Develop algorithm and System Model Simulink MDL and XSG Automatic VHDL code generation RTL schematic Xilinx Implementation Flow Bitstream Download to FPGA Figure 9. Xilinx system generator design ﬂow. 7 4. Implementation of the FDTC on the FPGA 4.1. Xilinx system generator design ﬂow The XSG software is the toolbox which was developed by Xilinx. It could be integrated in a Matlab/Simulink environment where it could let the utilizer create parallel FPGA systems. These created models could be displayed as blocks, and linked to other Matlab/Simulink-like blocks. Once the system was developed from the XSG, the VHDL code could be generated, and more exactly reproducing the behaviour noticed in Matlab. The design ﬂow utilizing the XSG is shown in Figure 9. 4.2. Design of the FDTC from XSG The hardware implementation on the FPGA of the FDTC requires the VHDL code and then the Bitstream ﬁle, which can be automatically generated using the FDTC design from the XSG, as presented by Figure 9. As shown in Figure 3 the FDTC consists 8 S. KRIM ET AL. in Figure 2 is used. In this case, we have utilized a programming Matlab built in the XSG using the Mcode block. 5. Simulation and implementation results Figure 10. Design of the fuzzy logic system from the XSG. of several blocks which are the Concordia transform, the torque and ﬂux estimators, the ﬂux module, the θS angle, and the FLS. As shown in Figure 8, the FLS is based on three inputs and one output. Using the XSG, the FLS design is illustrated in the following ﬁgure. In this study the hysteresis controllers and the switching table are replaced by the FLS. 1) Fuzziﬁcation step: The ﬁrst step of the fuzzy logic system is the fuzziﬁcation, which consists in transforming the analog inputs to fuzzy variables. The error of the stator ﬂux is based on three fuzzy sets (P, Z, and N), as presented in Figure 4. The design of this input from the XSG requires the determination of the mathematical model of each fuzzy set. For example, the mathematical model of the fuzzy set ZE is given by the Equation (10). The architecture of the Equation (10) can be realized using the XSG toolbox. 8 if eφ < F1 then μZE ¼ 0 > > > > < if eφ < F2 then μ ¼ 0 ZE (10) 1 < 0 then μ if e > φ ZE ¼ F2 eφ þ 1 > > > : else μ ¼ 1 e þ 1 ZE F2 φ The error of the torque is based on ﬁve fuzzy sets (PL, PS, ZE, NS, and NL), as illustrated in Figure 5. The stator ﬂux position is described by the angle ‘Theta: ϴ’ which is described by 12 fuzzy sets, as shown in Figure 6. The design of these inputs from the XSG requires determining the mathematical model of each fuzzy set. 2) Inverter switching states ðSa ; Sb ; Sc Þ: To determine the inverter switching states form the selected voltage vector, the relationship presented (a) 5.1. Simulation results and discussion The developed models of the basic DTC and the FDTC approaches are simulated using the XSG. The stator ﬂux and the electromagnetic torque references are 0.91 Wb and 10 Nm, respectively. The load torque is proportional to the rotor speed, as given by the following equation: Tl ¼ kl Ωr (13) with kl ¼ 0:067 The parameters of the IM are presented by the table below (Table 2). With Hφ and HTe are the Hysteresis bands of the stator ﬂux and the electromagnetic errors. Figure 11 presents the evolution of the stator ﬂux locus plotted in stationary coordinates (α, β). Figure 11(a) shows the distortion under gone by the stator ﬂux vector at each sector transition, for the basic DTC. When the proposed FDTC is used, the stator ﬂux vector presents less distortion as shown by Figure 11(b). Figure 12 shows the evolution of the electromagnetic torque developed by the basic DTC and the proposed FDTC. It can be seen that torque reached quickly it reference value for the both control methods, thanks to the fast dynamic of the DTC. As shown in Figure 12(a), the torque presents ripples around its nominal value which is equal 10 Nm. Table 2. IM parameters. Number of pairs of poles P = 2 F = 50 Hz V/U: 220/380 V Rs = 5,717 Ω HTe = ± 0.1Nm Hφ = ± 0.01Wb (b) Figure 11. Stator ﬂux locus is plotted in stationary coordinates (α, β): (a) basic DTC, (b) FDTC. Rr = 4,282 Ω Ls = 464mH Lr = 464mH Msr = 441,7mH J = 0.0049 kg.m2 f = 0.0029kg.m2/s JOURNAL: EUROPEAN POWER ELECTRONICS AND DRIVES 10 T e m (N m ) T e m (N m ) 10 5 5 Time (s) 0 9 0 0.005 0.01 0.015 0 0.02 Time (s) 0 0.005 0.01 (a) 0.015 0.02 (b) Figure 12. Evolution of electromagnetic torque for: (a) basic DTC, (b) FDTC. These ripples are reduced with the proposed FDTC, as shown by Figure 12(b). The stator current, and the letter’s module is illustrated in Figures 13 and 14, respectively. It can be noticed that the stator current distortion are reduced in the case of the proposed FDTC. The performances of the FDTC relative to the basic DTC in terms of ripples are archived in Table 3. In the basic DTC, the switching frequency varies between 8 and 10 kHz. When the IM is controlled 20 Stator current (A) S t at or c urrent (A ) 20 10 0 -10 10 0 -10 -20 0 -20 2 Time (s) 3 1 5 5 0 -5 0.11 0 2 Time (s) 1 3 0 -5 0.115 0.12 0.125 0.13 0.11 0.115 0.12 (a) 0.125 0.13 (b) Figure 13. Evolution of the stator current for: (a) basic DTC, (b) FDTC. 20 Stator current (A) Stator current module (A) 20 15 10 5 0 0 2 Time (s) 3 1 15 10 5 0 2 Time (s) 3 1 0 6 5 5 4.5 4 4 3.5 1 1.5 2 3 1 (a) Figure 14. Evolution of the stator current module in (A) for: (a) basic DTC, (b) FDTC. 1.5 (b) 2 10 S. KRIM ET AL. Table 3. A comparative study between the FDTC and the basic DTC in terms of ripples. Basic DTC Max-Min Electromagnetic torque ripples 1 Stator ﬂux ripples 0.03 Stator current distortions 0.5 % 9.523 3.333 10.526 Table 4. Resources utilization. Used FDTC Max-Min 0.6 0.02 0.25 % 5.769 2.197 5.882 with the FDTC, the switching frequency is almost constant and equal to 6 kHz. 5.2. Implementation results and discussion After completing the design and simulation of the FDTC from the XSG, the VHDL code is generated, synthesized and implemented in Xilinx ISE 12.4. After synthesis, the RTL schematic for the FDTC algorithm is given as follows (Figure 15). In this work, the Xilinx Virtex-5 FPGA with an xc5vfx70t-3ﬀ1136 package is used. The resources Figure 15. Synthesis result of FDTC using Xilinx ISE 12.4. Number Number Number Number of of of of bonded IOBs Slices Registers Slice LUTs MULT18X18s DTC 68 259 1987 16 FDTC 68 866 4655 43 utilization of the basic DTC and the FDTC are archived in Table 4. This table presents data about the input/output number, multipliers, ﬂip ﬂops and slices required for the hardware implementation on the chosen FPGA. 6. Experimental validation The proposed control strategy, presented in Figure 3, has been implemented on the Xilinx Virtex-5 FPGA with an xc5vfx70t-3ﬀ1136 package. The experimental test bench, illustrated in Figure 16, is based on JOURNAL: EUROPEAN POWER ELECTRONICS AND DRIVES 11 Figure 16. Block diagram of the test bench. a three-phase IM with a squirrel cage, a Semikron voltage converter, a magnetic powder brake, an electronic board based on two sensors, which are used to measure the stator current, an electronic board for analogue-digital conversion of the stator current, and an inverter interface circuit board to create the dealt time. Figure 17 presents the used experimental test bench. The IM parameters are provided in Table 2. The DC bus voltage is equal to 400 V. The stator ﬂux and electromagnetic torque references are equal to 0.91 Wb and 10 Nm, respectively. The developed control law requires only the measuring of the stator currents. The experimental results have been recorded using the serial RS232 transmission and plotted utilizing the MATLAB environment. The obtained experimental results for the hardware implementation on the FPGA of the basic DTC and Figure 17. Real view of the test bench. the FDTC of an IM are given by Figures 18–21, respectively. Figure 18(a,b), illustrate the experimental results of the real electrical rotor speed in the case of the basic DTC and the FDTC. It can be seen that the speed response is very fast thanks to the high dynamic of the DTC. Moreover, the rotor speed ripples are reduced with the FDTC. The experimental results of the stator ﬂux and the electromagnetic torque are presented by Figures 19 and 20, respectively. It has been noted that the stator ﬂux and the electromagnetic ripples are reduced when the IM is controlled by the FDTC approach. The experimental results of the stator current for the basic DTC and the FDTC are presented by Figure 21. The obtained experimental results verify the eﬀectiveness of the FDTC approach relative to 12 S. KRIM ET AL. m (rad/sec) Estimated Torque Load Torque 5 200 0 100 -5 0 Tem (Nm) 10 300 0 1 2 x 10 1 2 3 x 10 4 (a) m 0 3 (a) 10 Tem(Nm) (rad/sec) 300 4 Estimated Torque Load Troque 5 200 0 100 -5 0 0 0.5 1 1.5 2 0 0.5 1 x 10 (b) Figure 20. Experimental results of the estimated electromagnetic torque for the: (a) basic DTC, (b) FDTC. 5 Flux (Wb) Current (A) 0.8 0.92 0.91 0.9 0.4 0 4 2 0 -2 -4 2.53 0 1 0.2 1.2 1.4 4 2.535 x 10 x 10 4 x 10 -5 0 1 2 3 (a) 1 x 10 5 0.8 0.92 0.91 0.9 0.4 1 0.2 0 1.2 0 4 0.5 1.5 1 Current (A) 5 1.4 x 10 0 4 (a) Flux (Wb) 0.6 2.54 4 3 2.5 2 1.5 1 0.5 0 2.5 4 4 Figure 18. Experimental results: Evolution of the electrical rotor speed for: (a) basic DTC, (b) FDTC. 0.6 2 x 10 (b) 1 1.5 2.5 2 0 -5 1.995 2.5 x 10 2 2.005 4 (b) Figure 19. Experimental results: Amplitude of the estimated stator ﬂux for the: (a) basic DTC, (b) FDTC. the basic DTC in terms of ripples. Therefore, the good functionality of the hardware architecture in the XSG and then the generation of the VHDL code are validated. The calculated ﬂux and torque ripples of the basic DTC and the FDTC have been archived in Table 5. It is clearly shown that the proposed FDTC approach is featured by good performances relative to the basic DTC by reducing the ﬂux and torque ripples. Table 6 presents a comparative study between the proposed FDTC and others existing schemes using two criteria such as: possibility of controller design and complexity of implementation and tuning. Referring to the simulation and the experimental results, it can be seen that the FDTC provides better 2.01 4 x 10 -5 0 0.5 1 1.5 2 2.5 x 10 4 (b) Figure 21. Experimental results of the stator current (isα) for the: (a) basic DTC, (b) FDTC. Table 5. Torque and ﬂux ripples for the basic DTC and DTFC. Stator ﬂux magnitude (Wb) Electromagnetic torque (N.m) Conventional DTC FDTC Max-Min 0.02 1.6 Max-Min 0.01 0.85 results in terms of ripples, compared to the conventional DTC. The four DTC approaches presented in Table 6 oﬀer similar performances in terms of dynamic. However, the implementation and tuning of the FDTC is sampler compared with the DTC- JOURNAL: EUROPEAN POWER ELECTRONICS AND DRIVES 13 Table 6. Comparative study between the proposed FDTC and others existing schemes. Conventional DTC Low Low Complexity of implementation and tuning Possibility of controller design SVM-PI and the DTC-SVM-SMC , due to the diﬃculty of the adequate choice of the gains parameters of the Proportional-Integral (PI) and sliding mode controllers, in addition the proposed FDTC is a sensorless control strategy which consequently reduces the inputs number and the system cost. The DTC-SVM-PI and the DTC-SVM-SMC  are based on two PI controllers and two sliding mode controllers, respectively. These controllers are diﬃcult in design, which made the FDTC easier to implement and to design. During the hardware FPGA implementation of the FDTC architecture, the obtained execution time is archived in Table 7. The computing time TFDTC of the FDTC approach is equal to 0.73μs. The analogue to digital conversion time tADC is equal to 2.2μs, using the analogue to digital converter ADS 8509. To determine the total execution time it is necessary to add the tADC time to the TFDTC. Finally, the total execution time of the FDTC is equal to 2.93 µs. The sampling period is equal to 50µs which is very big relative to the execution time. This is due to the high computation speed of the FPGAs thanks to their parallel processing. To get a control with high performances, it is desired to choose a very low sampling period, but in our case we are limited by the used inverter which requires a sampling period not less than 50µs. Table 7. Performance of the FPGA in terms of computing time. Module Cycles Acquisition of ADC values 36 + Conversion time Concordia transformation 6 Stator Flux and Torque 15 Estimator Sector calculation 32 Fuzzy logic control 20 Tex ¼ 2:2 þ 0:06 þ 0:15 þ 0:32 þ 0:2 ¼ 2:93μs Execution time (µs) 2.2 0.06 0.15 0.32 0.2 DTC-SVM-PI  High High DTC-SVM-SMC  High High FDTC Low Medium For more information about the FPGA in terms of processing speed, a comparative study relative to the dSP is presented and illustrated by Figure 22. Referring to the paper of , the estimated computation time is equal to 50 µs with a sampling period equal to 60µs using the DSP (dSPACE 1104 based on DSPTMS320F240). Paper of  presents an experimental implementation on a DSP of a DTC approach with a sampling period equal to 100µs. Using the DSP, the execution time is much higher to that obtained by a Xilinx FPGA which can execute the FDTC with 5µs. The obtained experimental results are similar to those obtained in theory; which conﬁrms the good performances of the IM controlled by an FDTC approach, implemented on a Xilinx FPGA. The high processing speed of the FPGA oﬀers a control with good performances, overcoming the DSP limitations mentioned in , essentially, the execution time which must reduced. In paper  the execution time inﬂuence is demonstrated; with an execution time equal to 6.5µs the stator current THD is equal to 8%. This rate is increased to 21% with an execution time equal to 50µs. To sum up, the ﬂux and torque hysteresis bands are the only gains to be adjusted in conventional DTC. The inverter switching frequency and the current waveform are greatly inﬂuenced by them. Therefore, the magnitude of the hysteresis band should be determined based on reasonable guidelines which can avoid excessive inverter switching frequency and current harmonics in the whole operating region. However, in the proposed FDTC the hysteresis controllers are replaced by a fuzzy logic system and applied to an IM with power equal to 1.5kW. The membership functions are depending on the parameters F1, F2, T1, and T2. These parameters can be chosen by the experience of the designer and optimized by simulations under diﬀerent conditions of speed and torque. For (a) k 5 10 15 20 25 30 35 40 45 k+1 Time (µs) k 5 10 15 20 25 30 35 40 45 k+1 Time (µs) (b) : A/D Conversion. : The execution time. Figure 22. Diagram of sequential timing for: (a) Xilinx FPGA Virtex 5, (b) DSP (e.g. dSPACE 1104. . .). 14 S. KRIM ET AL. others induction motors with high powers, the FDTC can be tuned by the parameters F1, F2, T1, and T2. 7. Conclusion This paper presents a hardware implementation of the FDTC approach on the FPGA. The intelligent technique based on the fuzzy logic has been put forward to overcome the basic DTC limitations, like the stator ﬂux and the torque ripples, as well as the harmonic stator current waves. In the FDTC approach, the switching table and the hysteresis controllers used in the basic DTC have been replaced by a fuzzy logic system. The hardware FPGA implementation of the proposed approach, has been developed, designed and simulated using the XSG tool. The VHDL code and the bitstream ﬁle have been automatically generated. The obtained simulation results have shown that the FDTC control strategy has better performances relative to the basic DTC. Actually, in the suggested control strategy, the ﬂux and the torque ripples are signiﬁcantly reduced. This is due to the fact that when using the fuzzy logic system, the selected voltage vector is more convenient. It has been shown experimentally that the proposed FDTC oﬀers satisfactory results in terms of torque and ﬂux ripples. The FPGA performance in terms of computation speed has been presented and discussed. Abdellatif Mtibaa is currently Professor in Micro-Electronics and Hardware Design with Electrical Department at the National School of Engineering of Monastir and Head of Circuits Systems Reconﬁgurable ENIM-Group at Electronic and microelectronic Laboratory. He holds a Diploma in Electrical Engineering in 1985 and received his PhD degree in Electrical Engineering in 2000. His current research interests include System on Programmable Chip, high level synthesis, rapid prototyping and reconﬁgurable architecture for real-time multimedia applications. Dr. Abdellatif Mtibaa has authored/coauthored over 150 papers in international journals and conferences. He served on the technical program committees for several international conferences. He also served as a co-organizer of several international conferences. E-mail: [email protected] Mohamed Faouzi Mimouni received his Mastery of Science and DEA from ENSET, Tunisia in 1984 and 1986, respectively. In 1997, he obtained his Doctorate Degree in Electrical Engineering from ENSET, Tunisia. He is currently Full Professor of Electrical Engineering with Electrical Department at the National School of Engineering of Monastir. His speciﬁc research interests are in the area Power Electronics, Motor Drives, Solar and Wind Power generation. Dr. Med Faouzi MIMOUNI has authored/coauthored over 100 papers in international journals and conferences. He served on the technical program committees for several international conferences. E-mail: [email protected] Disclosure statement No potential conﬂict of interest was reported by the authors. References Notes on contributors Saber Krim received the Electrical Engineering Diploma, the Master, and the Ph.D. degrees in 2011, 2013, and 2017, respectively, all in electrical engineering from the National Engineering School of Monastir, University of Monastir, Tunisia. He is a member of the Research Unit of Industrial Systems study and Renewable Energy, University of Monastir. His current research interests include rapid prototyping and reconﬁgurable architecture for real-time control applications of electrical systems. E-mail: [email protected] Souﬁen Gdaim received the degree in Electrical Engineering from National School of Engineering of Sfax, Tunisia in 1998. In 2007 he received his M.S degree in electronic and real-time informatic from Sousse University and received his PhD degree in Electrical Engineering in 2013 from ENIM, Tunisia. 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