nanotechnology-quantum-information-theory-and-quantum-computing

Tuesday. August E", ZOO2
IEEE-NAN0 2002
T A 5 Duantum mmDUtirYl
Nanotechnology - Quantum Information Theory - and Quantum Computing
Sergey Edward Lyshevski
Department of Electrical Engineering
Rochester Institute of Technology
Rochester, NY 14623-5603
Abslracl- Significant progress has been made in various
applications of nanotechnology, and much efforts have been
concentrated on the theory of nanocomputers. There are the
need to examine nanocomputer architectures which include
the following major components: the arithmetic-logic unit,
the memory unit, the inputloutput unit, and the control unit.
The recent results illustrate that novel logic and memory
nanoscale integrated circuits can be fabricated and
implemented. This progress ais primarily due to the
application of nanotechnology. Fundamental and applied
results researched in this paper further expand the horizon
of nanocomputer theory and nanotechnology practice. It is
illustrated that novel nanocomputer architectures and
organizations must be discovered and examined to ensure the
highest level of efficiency, flexibility and robustness.
I. INTRODUCTION
First-, second-, third-, and fourth- generations of
computers emerged, and tremendous progress has been
achieved. The [email protected]@4 (2.4 GHz) processor was
built using advanced Intel' NetBurstm microarcbitecture.
This processor ensures high-performance processing, and
is fabricated using 0.13 micron technology. The processor
is integrated with high-performance memory systems, e.g.,
8KB L1 data cache, 12K clops L1 Execution Trace Cache,
256 KB L2 Advanced Transfer Cache and 512 KB
Advance Transfer Cache.
The fifth generation of computers will be built using
emerging nanoICs. Currently, 50 nm technologu is
emerged to fabricate high-yield high-performance ICs
with billions of transistors on a single 1 cm2 die.
Synthesis, integration and implementation of new
affordable high-yield nanoICs are critical to meet Moore's
first law. Figure 1 illustrates the first and second Moore
laws. Despite of the fact that some data and foreseen
trends can be viewed as controversial and subject to
adjustments, the major trends and tendencies are obvious,
and most likely cannot be seriously argued and disputed.
1990
2wO
2010
2020
YCU
Figure 1. Moore's laws
High-performance computers architectures, novel
organizations, pipelining, parallel processing, ICs
hardware miniaturization and software optimization have
advanced for CMOS-based computers. However, the
fundamental physical limits are reached [I-41. As an
alternative to current computers and classical theory of
computation, quantum computers were proposed in the
1970s by Richard Feyman, Paul Benioff and Charles
Bennett [l]. Quantum computing ensures fast computation
using interacting quantum states in atoms, molecules or
photons (in conventional computers, transistors switch due
to the electron flow). To simulate a state vector in a 2"dimensional Hilbert space, classical computers manipulate
vectors containing of order 2" complex numbers, whereas
a quantum computer requires n qubits reducing memory
requirements. Tremendous challenges are needed to be
overcome, however, significant fundamental and
experimental progress has been made [5,6]. For example,
an IBM quantum complex which contains seven
programmed (magnetic field) and detected (nuclear
magnetic resonance) qubits (five fluorine and two carbon13
atoms)
was
researched.
The
dicarbonylcyclopentadienyl iron molecule CllHSF5OzFe
forms a seven qubits complex. This complex can be used
to form quantum logic gates.
This paper describes the method for implementing the
quantum logic gates to perform quantum computing. Due
to a variety of unsolved problems in quantum computing,
another viable paradigm in design of nanocomputers is
introduced. In particular, this paper focuses on threedimensional computer architectures using nanoICs made
using nanotechnology. We study the application of
nanoscale devices and examine different computer
architectures.
The elementary quantum logic gates are
I = lO)(Ol ')(I1 (identity)
+I
and N=10)(1(+/1)(01(NOT)
This paper formulates and solves some long-standing
fundamental and applied problems in design, analysis, and
optimization of nanocomputers. The fundamentals of
nanocomputer architectronics are reported, and the basic
organizations and topologies are examined progressing
from the general system-level consideration to the
nanocomputer
subsystem/unit/device-level
study.
NanoICs are examined using nanoscale field-effect
transistors (NFET).
In contrast to the classical information theory (only
two logic gates result for a single bit, e.g., identity and
NOT), there are an infmite number of single-qubit
quantum gates (e.g., A = ( O ) + \ l ) ~ l+(io)
I
-1l)~OI) due to
the quantum superposition. The possible unitary operators
for a pair of qubits are expressed as
lo)(ol @I+Il)([email protected] U ,
where I and U are the single-qubit identity and controlled
gate.
11. QUANTUM COMPUTING
Logical operations require multiple qubits. Two-qubit
gate is
Consider quantum logic gates which perform
elementary quantum operations. The state of an isolated
system is represented by a vector I (1)) in the Hilbert
space. The position and momentum Hermitian operators X
and P in the X-eigenbasis have the following matrix
elements
] x') .1
(x
The universal quantum gate and any unitary nxn
matrix can be formed using a controlled-NOT (XOR) gate
and a general single-bit gate
= x6(x-x')
1
and (x P I X ' ) = - i A G ' ( x - x ' ) .
The Schrodinger equation is
d
if"-$ ( t ) )=
(O),
Using the conditional S(Y1X) and mutual
A'(X;Y)=S(+S(YlX) entropies, we have if X+Y+Z then
S(X,z)SS(X,Y)This
. is the data processing inequality. The
channel capacity Cis found to be
where H i s the quantum Hamiltonian operator.
The Hadamard-type gate in the computational basis
ao)3lo)l
and
C = max S ( X ; Y ) .
IP(N
is
the
schematically
representation
I x ) + [ ~ ] ~ ( - l ) " l x ) + l l - x ) forthestate Ix) with&,
Let a qubit evolves as lO)+lo)
The transient dynamics is studied. It was illustrated
that the initial and final states are related by phase angles,
is
1.
e.g., eie and
e'' .
I (t)) = e!(')l-( I ) ) such that
the phase change of the initial state I (0)) is given as
For the state, we have
and ll)+eimll).
Then, the phase quantum logic gate is
0 = f ( r )- f(0) '
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Tuesday. August 27. 2002
TA!% Ouantum mmputing
H = H , + 2nhJS, C
3S, ,
The evolution of the quantum system is given as
and the energy level can be examined
Though
the
quantum
computing
theory
straightforwardly formulated, formidable challenges to
implement quantum computing remain. Therefore, we
concentrate our attention on other feasible direction. In
particular, devising nanocomputers using nanoICs
fabricated utilizing nanotechnology advantages.
Thus, 6' is a function of the Hamiltonian and state
changes, e.g.,
I(
I
B = -1 ' (t)l H (t))dt+ i ] ( ( t ) l $ I-(t))dt.
h,
0
III. NANOCOMPUTER
ARCHITECTURE AND
NANACOMPUTERARCHITECTRONICS
A single qubit density matrix is parameterized as
p =+(I + s .
0 )=
+ s,l+s,
+is,
where s is the Bloch vector,
Using the Rabi vector
=
1"l
sy
s, --Isy
The critical problems in the design of nanocomputers
are focused on devising, designing, analyzing, optimizing
and fully utilizing hardware and software. The current ICs
are very large scale integration circuits (VLSI). Though 90
nm fabrication technologies have been developed and
implemented by the leading computer manufacturers
(Dell, IBM, Intel, Hewlett-Packard, Motorola, Sun
Microsystems, Texas Instruments, etc.), and billions of
transistors can be placed on a single multilayered die, the
VLSI technology approaches the physical limits.
1-s,
.
J
1s.
we have
a,
H=+A(Q,I+Q.cT).
Thus,
Alternative affordable, high-yield and robust
technologies are sought, and nanotechnology promises
further far-reaching revolutionary progress. It is
envisioned that nanotechnology will lead to threedimensional nanocomputers with novel computer
architectures to attain the superior overall performance
level. Compared with the existing most advanced
computers, in nanocomputers the execution time,
switching frequency and size will be decreased by the
order of millions, while the memory capacity will be
increased by the order of millions. However, significant
challenges must be overcome. Many difficult problems
such as
1. novel nanocomputer architectures,
2. advanced organizations and topologies,
3. high-fidelity modeling,
4. data-intensive analysis,
5 . heterogeneous simulations,
6. optimization,
7. control, adaptation and reconfiguration,
8. self-organization,
9. robustness,
IO. utilization,
as well as other problems must be addressed, researched
and solved. Many of the above mentioned problems have
not been even addressed yet.
iA-dP = [ H , p ] ,
dt
and
ds
- =
dt
~ x s .
The Hamiltonian is exuressed as
The two-spin Hamiltonian with two noninteractive
half-spin particles S, and S, is
Hu = AoJ, @Ib+AobIa
@Sbz.
H, =fh
l
0
o,-oa
0
o
0
-o,+oa
O
0
I
For interactive system,
311
A nanocomputer architecture integrates the following
major systems: input - output, memory, arithmetic and
logic, and control units. The input unit accepts information
from electronic devices or other computers through the
cards (electromechanical devices, such as keyboards, can
he also interfaced). The information received can be stored
in the memory, and then, manipulated and processed by
the arithmetic and logic unit (ALU). The results are output
using the output unit. Information flow, propagation,
manipulation, processing, and storage are coordinated by
the control unit. The arithmetic and logic unit, integrated
with control unit, is called the processor or central
processing unit (CPU). Input and output systems are called
the input-output unit (U0 unit). The memory unit, which
integrates memory systems, stores programs and data.
Figure 2. Nanocomputer organization
There are two main classes of memory calledprimary
(main) and secondary memory. In nanocomputers, the
primary memory is implemented using nanoICs that can
consist of billions of nanoscale storage cells (each cell can
store one bit of information). These cells are accessed in
groups of fixed size called words. The main memory is
organized such that the contents of one word can be stored
or rehieved in one hasic operation called a memory cycle.
To provide a consistent direct access to any word in the
main memory in the shortest time, a distinct address
number is associated with each word location.
IV. NANOCOMPUTERS
AND NANOICS
PERFORMANCE
Current computers constantly irreversibly erase
temporary results, and thus, the entropy changes. The
average instruction execution speed (in millions of
instructions executed per second Ips) and cycles per
instruction are related to the time required to execute
instructions as given by
NanoICs can he effectively used to implement the
additional memory systems to store programs and data
forming secondary memory.
Ti*s,=lK.lnck,
where the clock frequencyf,,oct depends mainly on the ICs
or nanoICs used and the fabrication technologies applied.
The execution of most operations is performed by the
ALU. In the ALU, the logic nanogates and nanoregisters
used to perform the hasic operations (addition, subtraction,
multiplication, and division) of numeric operands, and the
comparison, shifting, and alignment operations of general
forms of numeric and nonnumeric data. The processors
contain a number of high-speed registers. which are used
for temporruy storage of operands. Register, as a storage
device for words, is a key sequential component, and
registers are connected. Each register contains one word of
data and its access time at least 10 times faster than the
main memory access time. A register-level system
consists of a set of registers connected by combinational
data-processing and data-processing nanoICs.
Tbe quantum mechanics implies an upper limit on the
frequency at which the system can switch from one state
to another. This limit is found as the difference between
the total energy E of the system and ground state energy
EO,e.g.,
4
f , 2 -(E - E o ) ,
h
..
where h is the Planck constant, h=6.626~10"~J-sec or
J/HZ.
An isolated nanodevice, consisting of a single
electron at a potential of IV above its ground state,
contains 1 eV of energy (leV=1.602~10-~~
J) and,
therefore, cannot change its state faster than
Figure 2 illustrates the possible nanocomputer
organization, and, in general, three-dimensional
nanocomuputer architectronics must he examined using
the major units reported.
f , <[email protected]
4
h
312
)U
1 . 6 0 2 ~ 1 0 -=' ~I X I O ' ~ Hz.
-6.626~10~"
In general, nanoICs ensure high density, superior
bandwidth, high switching frequency, low power, et cetera
[7-lo]. It is envisioned that in the near future
nanocomputers will allow one to increase the computing
speed by a factor of millions compared with the existing
CMOS. Three-dimensional multiple-layered high-density
nanoIC assemblies, shown in Figure 3, are envisioned to
be used
Hence, the switching frequency is 1 ~ 1 0 ' Hz.
~
Correspondingly, the switching frequency of nanoICs can
be significantly increased compared with 'the currently
used CMOS ICs.
In asymptotically reversible nanocomputers, the
generated entropy is
S=b/f,
where b is the entropy coefficient ( b varies from 1x10' to
1x106 hits/GHz for ICs, and from 1 to IO bitslGHz for
quantum FETs): f is the length of time over which the
operation is performed.
Correspondingly, the minimum entropy and
processing (operation) rate for quantum devices are S=l
biWoperation and r,=lx1026 operation/sec-cm2, while
CMOS technology allows one to achieve S=1x106
bitsloperation and re=3.5x10l6operation/sec-cm2.
Using the number of instructions executed (N), the
number of cycles per instruction C
(),
and the clock
frequency (h,,~),
the program execution time is
Figure 3. Three-dimensional multiple-layered highdensity nanoIC assemblies (crossbar switching, logic
or memory arrays), 3nm wide parallel (six-atomwide) erbium disilicide (Er&) nanowires (HewlettPickard [7, IO]), and carbon nanotube array
In general, the hardware defines the clock frequency
j & ~ ,the software influences the number of instructions
executed N, while the nanocomputer architecture defines
the number of cycles per instruction Cpl.
One of the major performance characteristic for
computer systems is the time that takes to execute a
program. Suppose A',,,,,is the number of the machine
instructions needed to be executed. A program is written
in high-level language, translated by compiler into
machine language, and stored. An operating system
software routine loads the machine language program into
the main memory for execution. Assume that each
machine language instruction requires Ns,epbasic steps for
execution. If basic steps are executed at the constant rate
of Rr [stepslsec], then, the time to execute the program is
V. NANOICS
In addition to molecular wires [7, 10, 111 and
molecular electronics [8], different nanodevices (switches,
logics, memories, etc.) can be implemented using the
illustrated in Figure 3 three-dimensional nanoelectronics
arrays. It must be emphasized that the extremely higbfrequency logic gates can he fabricated using carbon
nanotubes, which are from 1 to 10 nm in diameter. P- and
n-type carbon nanotube field-effect transistors (CNFETs)
with single- and multi-wall carbon nanotubes as the
channel were fabricated and tested [12-141. The atomic
force microscope image of a single-wall CNFET (50 nm
total length) and CNFET are documented in Figure 4.a.
Carbon nanotube strnchue can be utilized to devise
and built different transistors with distinct characteristics
utilizing different phenomena [12-141. For example,
twisted carbon nanotubes can be used. Carbon nanotubes
can be grown on the surface using chemical vapor
deposition, deposited on the surface from solvent, etc.
The main goal is to minimize T,. Optimal memory and
processor design allows one to achieve this goal. The
access to operands in processor registers is significantly
faster than access to the main memory. The application of
different memory systems results in a memory hierarchy
concept.
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IEEE-NAN0 2002
Photolithography can be used to attain the devicelevel structural and functional integration connecting
source, drain, gate, etc. One concludes that different
transistors topologies and configurations are available, and
these results are reported in 112-143. Taking note of this
fact, we use NFET to synthesize and analyze the nanoICs.
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The carbon nanotube inverter, formed using the series
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zero because one of the CNFETs is cut off. When the
input
voltage
vary
in
the
region
Yhrechold
<K a < -
1
Yhmshdd
1,
3.
4.
5.
6.
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I
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IO
11
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samao a-*
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13
14
15
16
Vd.
@)
Figure 4. (a) Carbon nanotube FETs;
@) inverter with CNFETs
17
The recent results reported in 115-171 allow one to
conclude that high-yield, affordable and high-performance
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