compatible lateral bipolar transistors in cmos technology

COMPATIBLE LATERAL BIPOLAR TRANSISTORS
IN CMOS TECHNOLOGY :
MODEL AND APPLICATIONS
THESE No 817 (1989)
PRESENTEE AU DEPARTEMEM D'ELECTRICITE
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
POUR L'OBTENTION DU GRADE DE DOCTEUR ES SCIENCES TECHNIWES
PAR
XAVIER ARREGUIT
lnghnieur hlectricien diplM6 EPFL
de nationaliteespagnole
aCCePt& sur proposition du jury :
Prof. E.A. Viiîoz. rapporteur
Prof. M. Declerco.corappwteur
B. Gilbert. corapporteur
Lausanne. EPFL
1989
RESUME
Tirant partie de ces principales caractéristiques, comme par exemple la
possibilité de combiner sur un même circuit intégré des parties numériques et
analogiques à très faible consommation et d'utiliser des structures de très
faibles dimensions, la technologie CMOS a pris de nos jours une part
dominante du marché des circuits intégrés. Bien qu'il soit possible
d'implémenter la plupart des circuits analogiques en technologie CMOS,
certains d'entre eux tirent avantage des performances des transistors
bipolaires. Par exemple, les circuits translinéaires qui sont basés sur les
propriétés de la caractCristique exponentielle du transistor, permettent de
réaliser des transformations non-linéaires de grandeurs analogiques
(multiplicateur, élévation à une puissance variable, etc.). Un transistor MOS en
faible inversion peut être envisagé pour la réalisation de tels circuits.
Toutefois, en technologie CMOS, il est plus avantageux de tirer parti des
possibilités nouvelles offertes par le transistor bipolaire latéral compatible
(TBLC) et le transistor bipolaire au substrat (tensions de décalage des paires
différentielles environ 10 fois plus faible, meilleur rapport
transconductance/capacité à courant donnt, bruit I/f nettement plus faible).
Suite à une approche théorique, la relation entre le courant de collecteur et la
tension griiie-base du TBLC a été mise en évidence et a permis d'aboutir a un
modèle analytique simple et précis. Cet effet résiduel de la grille sur les
caractéristiques électriques du TBLC peut être éliminé à l'aide de tensions
grille-base beaucoup plus négatives que le potentiel de Flat-Band. Pour éviter
le besoin dans ce cas d'une source de tension supplémentaire plus négative que
celle disponible sur le circuit, une méthode basée sur le principe d'injection de
charges sur une grille flottante a été présentée.
L'application de ce modéle aux circuits a démontré la possibilité d'utiliser
l'effet résiduel de la grille du TBLC pour apparier les transistors sur au moins
3 décades de courant. Cette technique combinée avec le développement de
structures cascodes appropriées, permet l'amélioration des performances des
circuits analogiques. Elle a été appliquée avec succès pour compenser la
vi
RESUME
tension de décalage des étages d'entrée d'amplificateurs différentiels et les
erreurs dues à un mauvais appariement de transistors dans les circuits
translinéaires. Limitée par une sensibilité résiduelle de l'effet de grille à la
température, cette compensation permet une précision d'environ 0.1% à 0.3%
sur une gamme de température de 100°K,ce qui correspond tout de même à
un facteur 5 à 10 gagné sur la précision de circuits analogiques utilisant le
TBLC en technologie CMOS.
CONTENTS
CONTENTS
.
1 INTRODUCTION ...................................................................... 1
Re ferences ................................................................................
3
.
2 BIPOLAR TRANSISTORS IN CMOS TECHNOLOGIES ........5
2.1. Introduction .......................................................................
5
2.2. Bipolar and CMOS technologies ...........................................5
2.3. CMOS compatible vertical bipolar m s i s t o r (CVBT)........... 10
2.4. CMOS compatible lateral bipolar transistor (CLBT).............11
2.4.1. The MOST in the bipolar mode .............................. 11
2.4.2. CLBT layout .........................................................14
References ..............................................................................
17
.
3 CLBT THEORY .......................................................................
19
3.1. Introduction ..................................................................... 19
3.2. Terminal current denvation ...............................................
20
3.2.1 .Two.diensional idealized stmctucture and hypothesis 20
3.2.2. Residual gate effect in accumulation ..........................22
3.2.3. Collector Current ....................................................
26
3.2.4. Components of the base current ................................31
36
3.3. Cumnt gains ...................................................................
3.4. Early effect ......................................................................
40
3.5. Effects at high eminer current ...........................................43
3.6. Effects of the temperature ................................................44
References ............................................................................. -46
.
4 CLBT MODEL .........................................................................49
:
4.1. introduction ......................... ...........................................49
4.2. Large-signal mode1 ........................................................... 50
4.2.1. Basic Ebers-MOUmode1.........................................50
4.2.2. Second-order effects and charge effects mode1 .........56
4.2.3. Computer simulation .............................................59
4.3. Smail-Signal mode1 ........................................................... 63
4.3.1. CLBT and residual gate transconductances ...............63
4.3.2. Input and output conductances ................................ 66
4.3.3. Capacitances ........................................................
-67
4.3.4. Frequency response ............................................... 68
4.3.5. Noise sources........................................................ 69
4.4. Scaling and new technologies ............................................-71
References .............................................................................. 75
.
5 PERFORMANCE ENHANCEMENT OF THE CLBT ............77
5.1. Introduction .....................................................................77
5.2. Cascode circuits................................................................ 79
5.3. Gate bias compensation ...................................................... 84
5.4. CLBT gate bias .................................................................86
5.5. CLBT's mismatch compensation .........................................87
5.5.1. Current sources and mirrors ..................................88
5.5.2. Diffenntial pairs ...................................................91
References ..............................................................................93
CONTENTS
6
.
CMOS ANALOG CIRCUITS USING THE CLBT ................95
6.1. Introduction .....................................................................
95
97
6.2. Translinear circuits in CMOS .............................................
6.2.1. Definition and principle .........................................97
6.2.2. CMOS implernentation ........................................... 98
6.2.3. Fourquadrant multiplier .....................................103
6.2.4.Precision compressor gain controller .....................114
6.2.5.Current range limitation of the trirnming technique . I l 8
6.3. Future trends and conclusion............................................120
References ............................................................................
121
.
7 CONCLUSION ......................................................................123
APPENDICES ...........................................................................125
CHAPTER
INTRODUCTION
Due to its main advantages, like versatility in combining digital and analog
circuits on the sarne chip, low-power consumption, smaii-geometry transistors,
CMOS is today the dominant technology for the design of VLSI circuits. Even
though it is already possible to implement most of the analog functional blocks
in CMOS technologies, some of them require bipolar transistors, for they
retain many advantages over those of MOS transistors, among which a larger
capability to drive capacitive loads, larger transconductance at a given current,
lower llf noise, better matching. The library of analog circuits can be
extended by using the various advantages of bipolar and MOS transistors. For
this reason, BICMOS technologies have been presented combining both types
of transistors on the same chip. Due to a higher number of process layers and
steps in the BICMOS technology, a cheaper approach lies in using bipolar
devices that are realizable with existing CMOS technologies.
It has been shown in 1969 [l] that any standard CMOS process is compatible
with the fabrication of a bipolar transistor of one type without recourse to
additional process steps, namely an n-p-n bipolar transistor in a p-weii process
or a p-n-p bipolar in a n-well process. Two possibilities of implernenting the
bipolar transistor have been presented, the first one is a compatible vertical
bipolar transistor (CVBT) using the substrate as the collector, a separate well
as the base and a diffusion as the emitter [2][3][4].Because the vertical bipolar
transistors will have a common coiiector in the substrate, the applications of
tiiese devices are strictly limited to common collector configurations. The
second possibility is to implement a second diffusion in the weli that is used as
a collector. A compatible lateral bipolar transistor (CLBT) can thus be detined
and is combined with a vertical bipolar transistor. Therefore, the new device
can be represented as a two-collector bipolar structure. Lin et al. did not use
the MOS gate to implement the lateral bipolar transistor. In 1982, Vittoz [SI
has shown that an n-MOS transistor can be operated as a lateral n-p-n bipolar
transistor simply by biasing the gate to p-well voltage with a sufficiently
negative value and forward biasing the source junction. Pure bipolar mode of
operation is thus achieved with the flow of carriers pushed away below the
surface of the device. The lateral bipolar transistor is combined with a vertical
bipolar transistor and a 5-terminal structure (emitter, base, collector, substrate
and gate) can be defined. Although this study refers to the implementation of
npn bipolar transistors in a CMOS p-well technology, the following results are
equaliy valid for pnp in an n-well bulk, if appropriate changes in the signs of
the applied voltages and currents are made. Since 1982, the library of analog
circuits has been extended by using the various advantages of the compatible
lateral bipolar transistor [6]-[14].
Models and applications of vertical and lateral Bipolar transistors and MOS
transistors are widely presented in the literature. However, the purpose of this
text is to present a simple model of the 5-terminal CLBT taking into account
its particular characteristics that are different than those of well known lateral
transistors in bipolar technologies (especially the residual gate effect on the
lateral coiiector current) and then to discuss its potential applications in analog
circuit design. Especial emphasis will be put on the possibility of using the
residual gate effect on the CLBT collector current to compensate transistors
mismatch.
To understand the limitations of bipolar transistors in CMOS, chapter 2 will
recall the main differences between bipolar and CMOS technologies and the
operating pinciples of bipolar and MOS transistors. Chapter 3 wiil deal with
the physics of the 5 terminal device and a large- and small-signal model will be
derived in chapter 4. In order to enhance the performances of the CLBT, basic
circuits compensating Early and gate effects and their applications to device
mismatch compensation will be presented in chapter 5. And finally, chapter 6
will present some applications of the CLBT, emphasizing especially the
possibility of using the residual gate effect to implement'accurate translinear
circuits.
References
[ l ] H.C. Lin et ai., "Complementary MOS-Bipolar Transistor Structure", IEEE Transactions
on Electron Devices, Vol. ED-16. No.1 l.pp.945-951, November 1969.
[2] M.Baflew et al., "CMOS Compatible, Self-Biased Bipolar Transistor airned at detecting
Maximum Temperanin in a Silicon Integrated Circuit", Elecmnics Lcttcrs, vo1.24,No. 16,
pp.1022-1024.4th August 1988.
[3] E.A:Vittoz, O.Neyroud, "A Low-Voltage CMOS Bandgap Reference", IEEE JSSC,
vol.SC-14. No. 3, pp.573-577. June 1979.
(41 Y.P.Tsividis, R.W.Ulmer, "A CMOS Voltage Reference", IEEE JSSC,vol.SC-13, No.
6, pp.774-778. December 1978.
[SI E.A. Vinoz, "MOS Transistors Operatcd in the Laterai Bipolar Mode and their Application
in CMOS", IEEE JSSC, vol.SC-18, No 3, June 1983.
(61 L.Tze-Leung Tse, Precision CMOS Operationai Amplifier", Memorandum No. UCBIERL
M84198.28 November 1984.
171 E.A.Vittoz, "Micropower Techniques" in "Design of MOS VLSI Circuits for
Telecornmunications". Y.Tsividis and P. Antognetti, editors,pp. 104-144, Prentice-Hall.
1985.
[8] M.G.Degrauwe et al.,"CMOS Voltage References Using Lateral Bipalar Transistors",
IEEE JSSC. vol.SC-20. No. 6.pp.1151-1157 ,December 1985.
191 Z.Hong,H.Melchior, "Four-Quadrant Multiplier Core with Lateral Bipolar Transistors in
CMOS Technology", Elecuonics Letters, Vol.21, No.2. pp. 72-74, 17th January 1985.
[IO] C.A.Laber et al., "Design Consideration for a High-Performance 31m CMOS Analog
Standard-Ce11Library", iEEE JSSC, vol.SC-22, No. 2,pp.181-189. April 1987.
[Il] X.Arreguit, E.A Vittoz, M.Merz, " Precision Compressor Gain Controller in CMOS
Technology", IEEE JSSC, vol.SC-22, No. 3, June 1987.
[12] M.G.Degrauwe et al.,"iDAC: An Interactive Design Tool for Analog CMDS Circuits",
IEEE JSSC, vol.SC-22. No 6, pp. 11061116, December 1987.
[13] X.Arreguit, E.A Vittoz, "Performance Enhancement of Compatible Lateral Bipolar
Transistors for High-Precision CMOS Analog Design", Founeenth Euopean Solid-State
Circuits Conference, Manchester. September 21-23.1988.
[14] T.W. Pan. A.A.Abidi, "A 50 dB Variable Gain Amplifier Using Parasitic Bipolar
Transistors in CMOS", IEEE JSSC, Vo1.24, No.4, pp.951-961, August 1989.