Fast-Transient LDO with Enhanced Level-Shifted FVF and Dynamic Compensation

Article
A Fast-Transient LDO with Enhanced Level-Shifted
FVF and Dynamic Compensation
Zhan Shi 1,*, He Huang 1, Tianyang Wang 2, Yang Zhou 3, Xiaomin Wei 4, Chunjuan Bo 1 and
Zhongfu Liu 1,*
1 College of Information and Communication Engineering, Dalian Minzu University, Dalian 116600, China
2 Zhangjiang Laboratory, Shanghai 201210, China
3 Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
4 School of Computer Science, Northwestern Polytechnical University, Xi’an 710072, China
* Correspondence: [email protected] (Z.S.); [email protected] (Z.L.)
Abstract
To meet the fast-response and wide load-current requirements of X-ray detector readout chips, a
Low-Dropout regulator (LDO) based on an improved Level-Shifted Flipped Voltage Follower (LS
FVF) is proposed in a 130-nm CMOS. A fast Flipped Voltage Follower (FVF)-based feedback loop is
introduced to improve transient response, while a level shifter is introduced to relax the dc operating-
point coupling between the pass-transistor gate and the control transistor drain at light loads. To
further enhance response speed, dynamic current-source biasing, which senses output-voltage
variations through capacitive coupling, is proposed, and it is capable of adaptively increasing the LS
FVF driving capability during large load transients. A positive-feedback auxiliary circuit is proposed
to further accelerate the charging and discharging of the pass-transistor gate. To maintain stability
over the 0–400 mA load range, dynamic pole-zero compensation is combined with Miller
compensation to track load-dependent poles and preserve sufficient phase margin across operating
conditions. Post-layout simulations with a 200 pF load capacitor and a 0–400 mA load-current step
show, an overshoot of 100.4 mV and an undershoot of 50.5 mV, with recovery times of 0.2 µs and 0.12
µs, respectively. The proposed LDO achieves a capacitance-normalized transient figure of merit of
0.113 ps, demonstrating a favorable trade-off among performance parameters.
Keywords: LDO; FVF; fast transient response; dynamic biasing; pole-zero compensation
1. Introduction
As X-ray imaging systems evolve toward higher frame rates, greater throughput, and higher
levels of integration, detector readout ASICs typically integrate large-scale pixel arrays, multichannel
analog front ends, analog-to-digital converters, and high-speed digital processing modules [1–6].
During data acquisition and readout, the simultaneous activation of numerous digital circuits and
rapid switching between operating states can induce large and abrupt variations in the supply load
current. The digital power-management circuitry of the ASIC must therefore provide a fast transient
response while maintaining stable operation under such conditions. Meanwhile, the readout ASIC
also imposes stringent constraints on the area and power consumption of the power-management
circuitry. To address these requirements, this work presents an LDO implemented in a 130-nm CMOS
process, operating from a 1.5 V input to provide a 1.2 V output with a 200 pF load capacitance. The
proposed LDO achieves fast transient response and stable operation over a load-current range of 0–
400 mA.
Conventional LDOs typically employ an Error Amplifier (EA) to drive the power transistor and
regulate the output voltage through negative feedback, as illustrated in Figure 1. However, in high-
load-current applications, the power transistor generally requires a large device size, resulting in
substantial gate parasitic capacitance. This parasitic capacitance, together with the relatively high
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equivalent output resistance of the EA, results in a large gate charging and discharging time constant
and consequently limits the load-transient response speed [7–9]. Therefore, accelerating the charging
and discharging of the gate of the large power transistor and mitigating the transient-response
limitation imposed by its parasitic gate capacitance are key challenges in achieving fast transient
performance in high-load-current LDOs.
EA
VREF
VFB
VIN
VOUT
MP
R1
R2
CL
Figure 1. Architecture of the conventional LDOs.
To address the aforementioned challenges, Flipped Voltage Follower (FVF)-based LDOs, as
shown in Figure 2, have aracted considerable aention owing to their fast feedback path and low
equivalent impedance [10–13]. In a conventional FVF, M1 directly senses variations in the output
voltage, while the current through M2 modulates the current delivered by the pass transistor MP,
allowing load disturbances to bypass the slow feedback path associated with the bandwidth-limited
conventional EA and thereby improving the transient response. However, conventional FVFs still
suffer from two major limitations when operating over a wide load-current range. First, the gate
voltage of the pass transistor MP and the drain voltage of the control transistor M1 are coupled; at
light loads, VPG must increase to reduce the overdrive voltage of MP, which may force M1 into the
triode region and consequently cause a deviation in the output voltage. Second, the conventional FVF
provides only small transient charging and discharging currents to VPG, resulting in a limited slew
rate at VPG and consequently constraining the transient response speed.
VCTRL
VOUT
VIN
MP
VPG
M1
M2
CL
R1
R2
VFB
EA
VREF
VFB
VBN1 MN
Figure 2. Basic FVF-based LDO architecture.
To address the first issue, the shared node between the two branches can be decoupled [14–17].
Albezzano et al. [14] introduced a common-gate stage into the fast feedback loop to form a Cascoded
FVF, which redistributes the internal node voltages and enables M1 to maintain an appropriate
operating condition over a wider load current range. However, the voltage level shift provided by
this structure is relatively limited, approximately equal to the overdrive voltage of the common-gate
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transistor. To further increase the voltage level shift, a source follower can be employed [15] to form
a Level-Shifted FVF (LS FVF). Under a small overdrive voltage condition, its DC voltage level shift
can be approximately equal to the threshold voltage. Cai et al. [16] further modified the source
follower in the LS FVF into a Super Source Follower (SSF), forming an SSF FVF, which achieves the
same voltage level shift as the LS FVF while providing a lower output impedance. However, the SSF
FVF requires the output pole to be located at a low frequency to ensure stability, which limits the
maximum load current and imposes a minimum load capacitance requirement. To further extend the
load current range, Zhu et al. [17] combined the Cascoded FVF and SSF FVF to develop a Buffered
FVF (BFVF), which provides an enhanced voltage shift. However, this circuit exhibits degraded
stability under no-load conditions. Considering that the application requires a wide load current
range, including the no-load condition, the Cascode FVF, SSF FVF, and Buffered FVF structures are
not adopted in this design. Instead, the LS FVF structure is employed.
To address the second limitation, the transient response can be improved by increasing the
charging and discharging speed of the node of the pass-transistor gate [18–20]. Lu et al. [18]
introduced dynamic biasing into the FVF to rapidly adjust the bias current of the FVF loop in response
to load-current variations, thereby improving the transient response. In this scheme, a common-gate
MOS transistor converts variations in the output voltage into current variations, which are then
mirrored to modulate the FVF bias current, enabling rapid adjustment of the gate voltage of the large
pass transistor and alleviating the gate slew-rate limitation inherent in fixed-bias implementations.
However, the load-dependent variation of the internal poles in this topology is relatively complex,
posing considerable challenges to stability design over a wide load-current range. To further improve
the transient response, Boanloo et al. [19] employed a push–pull technique to enhance the gate slew
rate of the pass transistor in the FVF. This approach employs cross-coupled common-gate branches
to establish two output-voltage feedback paths. The resulting feedback signals control the push–pull
stage to provide larger bidirectional charging and discharging currents, thereby mitigating the slew-
rate limitation caused by the limited drive current in conventional FVFs. However, this method
requires additional gain stages and signal paths, increasing the number of internal dynamic nodes
and substantially complicating frequency compensation and stability design across the entire load
range. In addition to the above approaches, Pappiah et al. [20] incorporated a Slew-Rate Enhancer
(SRE) into an FVF LDO, where capacitive coupling senses variations in the FVF control voltage and
dual current mirrors directly charge and discharge the parasitic gate capacitance of the pass transistor,
thereby reducing the output-voltage deviation caused by load transients and shortening the recovery
time. However, this design was validated over a narrow load-current range of 0–50 mA, and its
transient driving capability for a large pass transistor under load currents of several hundred
milliamperes has not yet been sufficiently demonstrated. Considering the stringent chip area
constraint and the wide load current range of 0–400 mA in this application, the design combinates
dynamic biasing, push-pull driving, and capacitive coupling techniques to enhance the transient
response speed.
In addition, frequency compensation of the LDO over a wide load-current range represents
another major design challenge, which can be addressed using techniques such as pole spliing, and
dynamic compensation [21–23].
In summary, although numerous improvements to FVF-based LDOs have been proposed to
extend the load-current range and enhance the transient response, several limitations remain. To
meet the requirements of the digital power supply in X-ray detector readout ASICs for fast transient
response and a wide load-current range, this work proposes an LDO based on an improved LS FVF
architecture implemented in a 130-nm CMOS process, as shown in Figure 3. In the proposed design,
the source follower in the LS FVF relaxes the coupling between the DC operating points and forms a
fast local feedback loop, while its low output impedance enhances the capability to drive the gate of
the large power PMOS transistor. Capacitive coupling is further employed to sense transient
variations in the output voltage and dynamically adjust the LS FVF bias current, thereby providing
the fast feedback loop with enhanced drive capability during load transients. Meanwhile, a positive-
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4 of 19
feedback auxiliary circuit is proposed to accelerate the transient response of the gate voltage of MP.
Moreover, to maintain stability over the entire load-current range, a dynamic pole-zero compensation
scheme is adopted, in which the compensation network adjusts the pole and zero locations according
to the load condition to accommodate variations in the system poles.
VIN
CIN
VOUT
VPG CL
MP
EA
VREF
M1
I1
Dynamic
Pole-Zero
Compensation
Level
Shifter
R
R
Fast Loop
Slow Loop
Capacitive-
Coupled
Dynamic Biasing
VCTRL
VFB
Positive Feedback
Auxiliary
Figure 3. Block diagram of the proposed LS FVF-based fast-transient LDO.
The remainder of this paper is organized as follows: Section 2 analyzes and designs the key
modules, including the LS FVF fast loop, dynamic biasing circuit, positive feedback auxiliary circuit,
and EA. Section 3 establishes a dual-loop small-signal model, analyzes the system poles and zeros as
well as the dynamic pole-zero compensation mechanism, and presents the frequency-compensation
design of the LDO. Section 4 presents the LDO layout and post-layout simulation results and
compares its performance with prior work in terms of DC characteristics, load-transient response,
Power-Supply Rejection Ratio (PSRR), and other key metrics. Finally, Section 5 concludes the paper.
2. Proposed LDO Architecture
2.1. LS FVF Fast Loop Analysis and Design
In this application, the current load varies from 0 to 400 mA, resulting in a wide variation in the
gate voltage of the power transistor MP. However, the biasing condition of the conventional FVF is
difficult to accommodate such a wide gate voltage range, which may drive the control transistor M1
out of the saturation region and degrade the normal operation of the feedback loop. To address this
issue, a level shifter consisting of MLS and MLSP is incorporated into the FVF to form an LS FVF, as
shown in Figure 4. By decoupling the gate of MP from the drain of M1, the proposed structure
alleviates the a forementioned limitation and enables all transistors to maintain appropriate operating
conditions over a wide load range. Furthermore, the source-follower-based level shifter introduced
in the LS FVF further reduces the equivalent impedance at the gate node VPG of the power transistor,
thereby decreasing the charging and discharging time constant associated with the large gate
parasitic capacitance and improving the gate speed of MP. A quantitative analysis of the low-output-
impedance characteristic of the LS FVF is presented below.
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© 2026 by the author(s). Distributed under a Creative Commons CC BY license.