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A VHDL based Moore and Mealy FSM example for education
Conference Paper · August 2017
DOI: 10.1109/SIPROCESS.2017.8124583
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A VHDL Based Moore and Mealy FSM Example for Education
Sultana Alsubaei1, S. M. Qaisar1, W. Alhalabi2
1Electrical and Computer Engineering Department, Effat University, Jeddah, KSA
2Computer Science Department, Effat University, Jeddah, KSA
e-mail:
1
[email protected],
1
[e-mail]
Abstract—With recent technological advancements, modern
societies are becoming more and more dependent on the
automated machines. It is in order to cope with their fast-going
lives. Modern automated machines adapt their sequence of
actions depending on their environment and events. The FSM
(Finite state machine) is used to mathematically express those
sequences of actions or instructions. In this article two FSM
machines types, Moore and Mealy, are discussed. Showing
different results in order to demonstrate the importance of
FSM modeling. An edge detector circuit is designed by
employing both Moore and Mealy machines. It is a FSM design
example, can be used for students concepts building and
demonstration. These designs are implemented in VHDL. A
comparison is also made based on both implementations.
Keywords-FSM;, automation; VHDL;, Xilinx-ISE;, timing
diagram; computer aided design
I. INTRODUCTION
Because of ever wanted features, the DSP (Digital Signal
Processing) has replaced the analog processing in most of the
modern systems [1]–[3]. A smart digital signal processing
design can lead towards an efficient solution and vice versa
[1]–[3].
Information in digital systems is classified as, data or
control information [4]. Data is known as discrete element
of information that can be altered in order to preform
arithmetic, logic and other data-processing tasks which is
implemented with digital components such as decoders,
adders and counters [5]. While control information provides
command signals that supervises the operations held in the
data section to ensure the desired output [4], [5].
There are two distinct modules of all digital processing
system. One is dealing with the performance of data
processing by designing the suitable digital circuit. The other
part deals with the design of the operation supervisor, the
control circuit [5].
The control logic uses status conditions from the data
processor to serve as decision variables to determine the
sequence of control signals. The control logic provides a
sequence of time signals, which is essential for operation
initiation in the data processor, and also the determination of
the next state of the control subsystem [6].
Finite state machine FSM [7]–[9] or also known as finite-
state automaton FSA [10], [11]. The word automaton
expresses a machine that functions based on already stored
and determined coded instructions, with a wide range of
programmed capabilities based on different circumstances
[10], [11]. It simplifies the meaning of FSM to be a
mathematical model of computation that is based on a
hypothetical machine that consists of a finite number of
states [7]–[9]. Only one machine state can be active at a
given instant. It is done as a function of the inputs
combination, previous sate and the system memory elements
status [7].
The FSM can be modeled by either FSM model
designing or by ASM (Algorithmic State Machines) method,
which is mainly used for designing FSMs and for digital
integrated circuits diagram representation by flowcharts
methodology [12], [13]. ASM shares conceptual similarities
with FSM modeling except that ASM is easier for
understanding due to its informality as shown on Figure 1,
illustrating modulo three counters [14]. ASM can be
compiled by using ASM++ compiler. Moreover, certain
other interesting state machine synthesizers examples are
available in the literature [15], [16].
Figure 1. Modulo three counters
II. THE FSM PRINCIPLE
The FSM is typically used as a type of control system
where knowledge is represented in the states and actions are
constrained by rules [17]. The general FSM model is shown
on Figure 2.
Figure 2, illustrates the form and function of a state
machine. Usually drawn as a bubble-and-arrow diagram.
State is a uniquely identifiable set of values measured at
various points in a digital system. Where next State is the
state to which the state machine makes the next transition,
determined by the inputs present when the device is clocked.
Branch explains the change from present state to next state.
For any given state, there is a finite number of possible next
states. On each clock cycle, the state machine branches to
the next state. One of the possible next states becomes the
new present state, depending on the inputs present on the
clock cycle [7], [17].
2017 IEEE 2nd International Conference on Signal and Image Processing
978-1-5386-0969-9/17/$31.00 ©2017 IEEE

Figure 2. The general FSM model
Figure 3. Moore state machine diagram [17].
There are two main categories of FSM. The first one is
deterministic FSM, meaning that for a given input and the
current state, the state transition can be predicted [17]. The
second type is Non-deterministic finite state machine. In this
case, for a given input and current state the state transition is
not predictable [17]. The non-deterministic finite state
machine is employed in the case of event driven systems
control units design [18], [19], [25], [26].
The deterministic and non-deterministic FSMs are further
classified as transducers, acceptors, classifiers and
sequencers [20]. In the automat and control applications, two
FSM types named as Mealy and Moore machines are
frequently employed. A brief description of the Moore and
Mealy machines is provided in the following subsections.
A. The Moore Machines
The Moore machine is a FSM whose output is
determined only as a function of the present state [7], [17].
The output has no relation with the input. The Moore
machine principle is illustrated with the help of a diagram,
shown on Figure 3 [17].
In Figure 3, the Moore State machine output is shown
inside the State bubble, because the output remains the same
as long as the state machine remains in that state. The output
can be arbitrarily complex but must be the same every time
the machine enters in that state [17].
B. The Mealy Machines
In the case of Mealy machine the output is determined as
a function of the current input and present state [7], [17].
Therefore, it is capable of generating a variety of different
output patterns for the same state. It is done as a function of
the inputs present on the triggering edge of clock [17]. The
Mealy machine principle is illustrated with the help of a
diagram, shown on Figure 4 [17]. The Outputs are shown on
transitions since they are determined in the same way as is
the next state.
Figure 4. Mealy state machine diagram [17].
III. ILLUSTRATING EXAMPLE
In order to illustrate the FSM design process a Rising
Edge Detector circuit is designed. This circuit is frequently
employed in a variety of modern applications and act as a
signal level or state change indicator [21]–[23]. This circuit
generates a one clock cycle pulse, a tick, when the input
signal changes its logic from low to high. This functionality
is frequently employed to indicate the low-to-high transition
of a slow time-varying input signal. The circuit is designed
by employing both Moore and Mealy machines. These
designs are implemented in VHDL. A comparison of both
implementations is also made.
The state machine diagram of a Moore machine based
edge detector implementation is shown on Figure 5.
Figure 5. The state machine diagram of Moore machine based edge
detector [24].
In Figure 5, the zero and one states show that the input
signal has been low and high for a while. The rising edge
occurs when the input changes to high in the zero state. The
FSM moves to the edge state and the output, tick, is asserted
in this state.

The state machine diagram of a Mealy machine based
edge detector is shown on Figure 6. The zero and one states
have similar meaning. When the FSM is in the zero state and
the input changes to high, the output is asserted immediately.
The FSM moves to the one state at the rising edge of the next
clock and the output is de-asserted.
Figure 6. The state machine diagram of Mealy machine based edge detector
[24].
For both Moore and Mealy machine based designs, the
circuit are implemented in VHDL and are synthesized with
the Xilinx-xst for the XC6LXT240T component from the
Virtex-6 family. The circuit block diagram is shown on
Figure 7. The Moore machine based circuit technology
schematic and the Mealy machine based circuit RTL
(Register Transfer Level) schematic are respectively shown
on Figures 8 and 9.
Figure 7. The edge detector Block Diagram, generated with Xilinx-ISE.
Figure 8. The Moore machine based edge detector technology schematic.
Figure 9. The Mealy machine based edge detector RTL schematic.
Both implemented circuits functionality is also verified
with the Xilinx-ISim. The timing simulation results obtained
for the Moore and the Mealy based edge detectors are shown
respectively on Figures 10 and 11.
Figure 10: The Moore machine based edge detector Timing Diagram.
Figure 11. The Mealy machine based edge detector Timing Diagram.
Figures 10 and 11 show that both Moore and Mealy
machine based designs can generate a short tick at the rising
edge of the input signal. However, there are still certain
understandable differences. The Mealy machine-based
design requires fewer states and responds faster (cf. Figures
5, 6, 8 and 9), but the width of its output may vary and input
glitches may be passed to the output [24].The choice
between the two designs depends on the system module,
employs the output of edge detector. Most of the time the
subsystem is a synchronous system that shares the same
clock signal, employed by the edge detector. In this case, the
edge detector output is sampled only at the rising edge of the
clock, the width and glitches do not matter as long as the
output signal is stable around the edge [24]. As the Mealy
machine based circuit responds faster than the Moore

machine based circuit. Therefore, the Mealy machine based
edge detectors are preferred for the synchronous system
implementations. However, in the case of asynchronous
system implementations, the employment of Mealy machine
based edge detectors can lead towards the system instability
[24].Therefore, in this case, because of a consistent width
tick generation, the Moore based edge detectors employment
is preferred over the Mealy based counter circuits [24].
IV. CONCLUSION
In recent era, we are becoming more dependent on the
automated machines. Modern automated machines adapt
their sequence of actions depending on their environment
and events. The FSM (Finite state machine) is extensively
employed for a systematic design and mathematical
representation of the sophisticated automates. In this context,
an introduction of the FSM principle has been made. The
FSM categories like deterministic and non-deterministic
FSMs are discussed. Moore and Mealy machines based FSM
design principles are described. An edge detector has been
designed based on Moore and Mealy machines for students
concepts building and demonstration. These designs have
been implemented in VHDL. The circuits are successfully
synthesized with the Xilinx-XST for the XC6LXT240T
component from the Virtex-6 family. The synthesized circuit
block diagram has been presented. Moreover, the Moore
machine based circuit technology schematic and the Mealy
machine based circuit RTL schematics have also been shown.
The designed circuits functionality is also verified with the
help of Xilinx-ISim based timing simulations. The
simulation results have been shown on Figures 10 and 11. It
confirms a proper functionality of the designed edge
detectors. A comparison between both Moore and Mealy
machines based edge detector implementations has been
made. It has been shown that for the implemented edge
detectors, the Mealy machine based implementation is faster
than the Moore machine one. However, the Mealy machine
based implementation can only be employed in the
synchronous systems. On other hand, the Moore machine
based implementation is suitable for both synchronous and
asynchronous systems. Moore and Mealy based machines
design of other elementary circuits like period counter,
frequency counter, code converters, etc. is a prospect.
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