Algorithms for Model-checking Flat Counter Systems

Université Paris Diderot
Sorbonne Paris Cite
École Doctorale Paris Centre
Laboratoire
d’Informatique
Algorithmique:
Fondements et
Applications
Thése de doctorat
Discipline : Informatique
présentée par -
Amit Kumar Dhar
Algorithms For Model-Checking
Flat Counter Systems
(Algorithmes pour le model-checking de systèmes à compteurs plats)
Dirigée par -
Stéphane Demri et Arnaud Sangnier
Soutenue le 11 Decembre 2014 devant un jury composé de:
Alain Finkel Professor, ENS de Cachan Président
Ranko Lazi´c Associate Professor, The University of Warwick Rapporteur
Anca Muscholl Professor, Université Bordeaux Rapporteur
Radu Iosif CNRS Researcher, Verimag Examinateur
Stéphane Demri Senior Researcher, CNRS, ENS Cachan Directeur de thése
Arnaud Sangnier Assistant Professor, Université Paris Diderot Directeur de thése

ii

iii

iv

ABSTRACT (ENGLISH)
Keywords: Formal verification, Model-checking, Infinite state systems,
Flat counter systems, Temporal logics, Presburger arithmetic, Stutter-
ing theorem, Complexity bounds.
Automated systems have become a part and parcel of our daily
life with increasingly more of our daily activities being controlled or
dependent on one or more automated systems. These systems being
increasingly sophisticated and complicated, a relevant question to ask
is about the reliability of such systems. Formal verification provides
us with a better way to show reliability of such system compared to
simulation or manual testing due to large number of possible scenar-
ios that can occur during the execution of the system.
One of the ways to perform formal verification of automated sys-
tem is by model-checking. It consists of developing algorithm to check
whether a suitably expressive model, representing the executions of
the automated system satisfies a specification or not. For expressing
the specification we use specific logics suitable in expressing the spec-
ification. With increasing expressiveness of model, model-checking
problem quickly approaches undecidability even for simple proper-
ties like whether the system can reach a bad state or not.
In the thesis, we deal with models called “Flat Counter Systems”
which can be seen as programs manipulating integer variables (also
called counters) whose control structure is restricted. Regarding the
logic for specifications, we extend traditional temporal logic (like LTL,
FO, CTL etc.) with the ability to express properties on the values of
the counters during the execution. This results in specifications that
can state more expressive properties.
We provide, for each class of specifications, algorithms with opti-
mal complexity for solving the problem of model-checking flat counter
systems. Our approach is based on a more general methodology and
thus allows reuse of the results for other specifications.
v