CC1 2023 AS4

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-- Company:
-- Engineer:
--
-- Create Date: 24.11.2023 08:29:22
-- Design Name:
-- Module Name: AS4 - AS4_arc
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if
using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if
instantiating

-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity AS4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC);
end AS4;
architecture AS4_arc of AS4 is
signal b_int : std_logic_vector(3 downto 0);
signal rs_int : std_logic_vector(2 downto 0);
component xor2 is port (i0,i1 : in std_logic; o :
out std_logic);
end component;
component add1c is port (x,y,re : in std_logic;
s,rs : out std_logic);
end component;
begin
inst_xor21 : xor2 port map (i0=>sel, i1=>b(0),
o=>b_int(0));
inst_xor22 : xor2 port map (i0=>sel, i1=>b(1),
o=>b_int(1));
inst_xor23 : xor2 port map (i0=>sel, i1=>b(2),
o=>b_int(2));

inst_xor24 : xor2 port map (i0=>sel, i1=>b(3),
o=>b_int(3));
inst_add1c1 : add1c port map (x=>a(0),
y=>b_int(0), re=>sel, s=>s(0), rs=>rs_int(0));
inst_add1c2 : add1c port map (x=>a(1),
y=>b_int(1), re=>rs_int(0), s=>s(1), rs=>rs_int(1));
inst_add1c3 : add1c port map (x=>a(2),
y=>b_int(2), re=>rs_int(1), s=>s(2), rs=>rs_int(2));
inst_add1c4 : add1c port map (x=>a(3),
y=>b_int(3), re=>rs_int(2), s=>s(3), rs=>c);
end AS4_arc;