cf industrial data sheet en

_______________________________________________________________________________________________
Technical Specification
Industrial Compact Flash Card
Release Date: June 2005
Version: 1.4
_______________________________________________________________________________________
SCM PC-Card GmbH
Sperl-Ring 4
D-85276 Pfaffenhofen
Tel: +49 8441 788 810
Fax: +49 8441 788 900
www.scm-pc-card.de
S-CN CompactFlash Card Industrial Application
Preliminary
S-CN CompactFlash Card
Industrial Application
Product Specification
June 2005
S-CN : Single-Level-Cell-NAND
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Document History
Version
Description
1
New issue
1. Supported flash kind for block
size.
2.Capacity appearance modify
2
3.Checking Product UDMA
function (announce not supported
multi word DMA)
3
1.Update AC Characteristics
4
1.
2.
3.
4.
5.
6.
TCADO-SCF-000018.4
Power Consumptions
Environment conditions
MTBF
R/W Test
Temp Flow Chart
PCB No
2/139
Date
Apr. 2004
Approved by
Debby Chang
August. 2004
Xeras Xiang
December 2004
Ethan Cheng
June 2005
Verlaine Lin
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S-CN CompactFlash Card Industrial Application
Contents
INDUSTRIAL APPLICATION.............................................................................................................................................................................1
1.
INTRODUCTION.........................................................................................................................................................................................7
1.1
GENERAL DESCRIPTION ........................................................................................................................................................................7
1.2
FEATURES ...............................................................................................................................................................................................8
2.
PRODUCT SPECIFICATION...................................................................................................................................................................9
2.1
OPERATION AND ENVIRONMENT DESCRIPTION ....................................................................................................................................9
2.2
PHYSICAL DESCRIPTION ......................................................................................................................................................................10
3.
PRODUCT MODEL ..................................................................................................................................................................................11
3.1
4.
PART NUMBER DEFINITION .................................................................................................................................................................11
SUPPORT FLASH MEDIA......................................................................................................................................................................12
4.1
SUPPORTED NAND FLASH TYPE .......................................................................................................................................................12
4.2
LOGICAL FORMAT PARAMETERS (CHS) ............................................................................................................................................12
5.
BLOCK DIAGRAM...................................................................................................................................................................................14
5.1
CONTROLLER ARCHIVE.......................................................................................................................................................................14
5.2
FLASH CARD ARCHIVE........................................................................................................................................................................14
6.
SPECIFICATION AND FEATURES .....................................................................................................................................................15
6.1
ELECTRICAL SPECIFICATION ...............................................................................................................................................................15
6.1.1
Absolute Maximum Ratings..........................................................................................................................................................15
6.1.2
General DC Characteristic...........................................................................................................................................................15
6.1.3
DC Electrical Characteristics for 5 Volts Operation..................................................................................................................15
6.1.4
DC Electrical Characteristics for 3.3 Volts Operation...............................................................................................................16
6.1.5
Attribute Memory Read Timing Specification .............................................................................................................................16
6.1.6
Configuration Register(Attribute Memory)Write Timing Specification ....................................................................................17
6.1.7
Common Memory Read Timing Specification.............................................................................................................................17
6.1.8
Common Memory Write Timing Specification ............................................................................................................................18
6.1.9
I/O Input (Read) Timing Specification .........................................................................................................................................19
6.1.10
I/O Input (Write) Timing Specification ...................................................................................................................................20
6.1.11
True IDE Mode I/O (Read/Write) Timing Specification........................................................................................................21
6.1.12
True IDE Ultra DMA Mode I/O (Read/Write) Timing Specification ...................................................................................23
6.1.12.1
Ultra DMA Data-In Burst Initiation Timing............................................................................................................................................ 24
6.1.12.2
Sustained Ultra DMA Data-In Burst Timing........................................................................................................................................... 25
6.1.12.3
Ultra DMA Data-In Burst Host Pause Timing ........................................................................................................................................ 25
6.1.12.4
Ultra DMA Data-In Burst Device Termination Timing.......................................................................................................................... 26
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6.1.12.5
Ultra DMA Data-In Burst Host Termination Timing.............................................................................................................................. 26
6.1.12.6
Ultra DMA Data-In Burst Host Termination Timing.............................................................................................................................. 27
6.1.12.7
Sustained Ultra DMA Data-Out Burst Timing........................................................................................................................................ 27
6.1.12.8
Ultra DMA Data-Out Burst Device Pause Timing ................................................................................................................................. 28
6.1.12.9
Ultra DMA Data-Out Burst Device Termination Timing....................................................................................................................... 28
6.1.12.10
Ultra DMA Data-Out Burst Host Termination Timing........................................................................................................................... 29
6.2
POWER MANAGEMENT .......................................................................................................................................................................29
6.2.1
Normal Mode.................................................................................................................................................................................29
6.2.2
Power down Mode ........................................................................................................................................................................29
6.3
7.
PHYSICAL SPECIFICATION ...................................................................................................................................................................30
6.3.1
CompactFlash CF Type I..............................................................................................................................................................30
6.3.2
CompactFlash CF Type II.............................................................................................................................................................30
PIN ASSIGNMENT....................................................................................................................................................................................31
7.1
COMPACTFLASH PIN TYPE..................................................................................................................................................................31
7.2
SIGNAL DESCRIPTION ..........................................................................................................................................................................33
8.
CIS AND FUNCTIONS CONFIGURATION REGISTERS.............................................................................................................38
8.1
CONFIGURATION OPTION REGISTER (200H) .....................................................................................................................................38
8.2
CARD CONFIGURATION AND STATUS REGISTER (ADDRESS 202H) .................................................................................................39
8.3
PIN REPLACEMENT REGISTER (ADDRESS 204H) ..............................................................................................................................40
8.4
SOCKET AND COPY REGISTER (ADDRESS 206H) ..............................................................................................................................40
8.5
CARD INFORMATION STRUCTURE (CIS) ............................................................................................................................................41
9.
ATA SPECIFIC REGISTER DEFINITIONS.......................................................................................................................................55
9.1
MEMORY MAPPED ADDRESSING ........................................................................................................................................................55
9.2
CONTIGUOUS I/O MAPPING ADDRESSING .........................................................................................................................................56
9.3
OVERLAPPING I/O MAPPING ADDRESSING........................................................................................................................................57
9.4
TRUE IDE MODE .................................................................................................................................................................................57
9.5
ATA REGISTERS ...................................................................................................................................................................................58
9.5.1
Data Register .................................................................................................................................................................................58
9.5.2
Error Register ................................................................................................................................................................................58
9.5.3
Feature Register.............................................................................................................................................................................59
9.5.4
Sector Count Register....................................................................................................................................................................59
9.5.5
Sector Number Register ................................................................................................................................................................59
9.5.6
Cylinder Low Register...................................................................................................................................................................60
9.5.7
Cylinder High Register..................................................................................................................................................................60
9.5.8
Drive Head Register......................................................................................................................................................................61
9.5.9
Status Register................................................................................................................................................................................62
9.5.10
Alternate Status Register..........................................................................................................................................................62
9.5.11
Device Control Register...........................................................................................................................................................63
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9.5.12
10.
Drive Address Register ............................................................................................................................................................63
ATA COMMANDS................................................................................................................................................................................64
10.1
CHECK POWER MODE - 98H OR E5H ................................................................................................................................................64
10.2
EXECUTE DRIVE DIAGNOSTIC - 90H..................................................................................................................................................65
10.3
ERASE SECTOR(S) - C0H.....................................................................................................................................................................66
10.4
FORMAT TRACK - 50H.........................................................................................................................................................................67
10.5
IDENTIFY DRIVE – ECH ......................................................................................................................................................................68
10.6
IDLE - 97H OR E3H..............................................................................................................................................................................69
10.7
IDLE IMMEDIATE - 95H OR E1H..........................................................................................................................................................70
10.8
INITIALIZE DRIVE PARAMETERS - 91H...............................................................................................................................................71
10.9
READ BUFFER - E4H ...........................................................................................................................................................................72
10.10
READ LONG SECTOR(S) - 22H OR 23H...............................................................................................................................................73
10.11
READ MULTIPLE - C4H .......................................................................................................................................................................74
10.12
READ SECTORS(S) – 20H OR 21H.......................................................................................................................................................75
10.13
READ VERIFY SECTOR(S) – 40H OR 41H...........................................................................................................................................76
10.14
RECALIBRATE - 1XH ...........................................................................................................................................................................77
10.15
REQUEST SENSE - 03H ........................................................................................................................................................................78
10.16
SEEK - 7XH..........................................................................................................................................................................................79
10.17
SET FEATURE - EFH.............................................................................................................................................................................80
10.18
SET MULTIPLE MODE - C6H...............................................................................................................................................................81
10.19
SET SLEEP MODE - 99H OR E6H ........................................................................................................................................................82
10.20
STANDBY - 96H OR E2H......................................................................................................................................................................83
10.21
STANDBY IMMEDIATE 94H OR E0H ...................................................................................................................................................84
10.22
TRANSLATE SECTOR - 87H..................................................................................................................................................................85
10.23
WEAR LEVEL - F5H.............................................................................................................................................................................86
10.24
WRITE BUFFER - E8H..........................................................................................................................................................................87
10.25
WRITE LONG SECTOR(S) 32H OR 33H...............................................................................................................................................88
10.26
WRITE MULTIPLE - C5H .....................................................................................................................................................................92
10.27
WRITE MULTIPLE WITHOUT ERASE – CDH.......................................................................................................................................93
10.28
WRITE SECTOR(S) - 30H OR 31H........................................................................................................................................................94
10.29
WRITE SECTOR(S) WITHOUT ERASE - 38H.........................................................................................................................................95
10.30
WRITE VERITY - 3CH..........................................................................................................................................................................96
11.
ERROR POSTING.....................................................................................................................................................................................97
12.
IDENTIFY DRIVE INFORMATION...............................................................................................................................................99
13.
ATA PROTOCOL OVERVIEW ..................................................................................................................................................... 103
13.1
PIO DATA IN COMMANDS ................................................................................................................................................................ 103
13.2
PIO DATA OUT COMMANDS ............................................................................................................................................................ 103
13.3
NON DATA COMMANDS ................................................................................................................................................................... 103
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14. ULTRA DMA DATA-IN COMMANDS................................................................................................................................................... 104
14.1. INITIATING AN ULTRA DMA DATA-IN BURST.......................................................................................................................................... 104
14.2. THE DATA-IN TRANSFER ........................................................................................................................................................................... 104
14.3. PAUSING AN ULTRA DMA DATA-IN BURST ............................................................................................................................................. 105
14.3.1. Device pausing an Ultra DMA data-in burst ............................................................................................................................... 105
14.3.2. Host pausing an Ultra DMA data-in burst ................................................................................................................................... 105
14.3.3. Terminating an Ultra DMA data-in burst ..................................................................................................................................... 105
14.3.3.1. Device terminating an Ultra DMA data-in burst............................................................................................................................................. 105
14.3.3.2. Host terminating an Ultra DMA data-in burst................................................................................................................................................. 106
14.4. ULTRA DMA DATA-OUT COMMANDS ..................................................................................................................................................... 108
14.4.1. Initiating an Ultra DMA data-out burst........................................................................................................................................ 108
14.4.2. The data-out transfer ...................................................................................................................................................................... 108
14.4.3. Pausing an Ultra DMA data-out burst.......................................................................................................................................... 109
14.4.3.1 Host pausing an Ultra DMA data-out burst...................................................................................................................................................... 109
14.4.4. Terminating an Ultra DMA data-out burst................................................................................................................................... 109
14.4.4.1 Host terminating an Ultra DMA data-out burst................................................................................................................................................ 109
14.4.4.2 Device terminating an Ultra DMA data-out burst............................................................................................................................................ 110
14.5. ULTRA DMA CRC RULES.........................................................................................................................................................................111
15. SECURITY CF ...............................................................................................................................................................................................113
16.SYSTEM ENVIRONMENTAL SPECIFICATIONS............................................................................................................................. 138
16.1 TEMPERATURE TEST FLOW ...................................................................................................................................................................... 138
16.2ALTITUDE TEST .......................................................................................................................................................................................... 139
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1. Introduction
1.1 General Description
The S-CN CompactFlash Card uses NAND-Type flash memory devices, which leads to its
remarkable high performance and comes with capacities from 256 MB to 6GB unformatted.
Compliant with ISA (Industrial Standard Architecture) bus interface standard, the S-CN CompactFlash
Card performs sequential read/write for each sector (512 bytes) count. It also conforms to CompactFlash
Specification and is designed with precision mechanics to enable host devices to read/write from the
CompactFlash interface into Flash Media. It can operate with a 3.3V or 5V single power from the host
side.
The card provides extraordinary memory medium for PC or any other electric equipment and digital
still camera, and, in particular, the S-CN CompactFlash Card has been approved through various
compatibility tests to be used in numerous portable desktop, notebook computers and personal handheld
devices such as handheld audio recorders, PDAs, Palm sized PCs, Handheld PCs and Auto PCs under
industrial environment.
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1.2 Features
—
PC Card compliant
Conforms to CompactFlash standard
Compatible with PCMCIA ATA specification
Support CIS implemented with attribute memory
Compatible with all PC Card Services and Socket Services
—
PCMCIA ATA / IDE interface
ATA command set compatible
Support for 8-bit or 16-bit host data transfer
Program and auto-wait-state initiation for compatibility with any IORDY supporting host
Compatibility with host ATA disk I/O BIOS, DOS/Windows file system, utilities, and application
software
—
Extremely rugged and reliable
Advanced defect block management
Support background erased operation
—
3.3/5 Volt power supply, very low power consumption
●
Zero-power data retention, no batteries required
●
Internal self-diagnostic program operates at VCC power on
●
Auto sleep mode
—
—
High reliability based on internal ECC (Error Correcting Code) function
Zero-power data retention, no batteries required
—
3 variations of mode access
●
Memory card mode
●
I/O card mode
●
True IDE mode
- PIO Mode 4
- UDMA mode 2
Not supported Multi word DMA formatted.
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2. Product Specification
2.1 Operation and environment description
5V ± 10%
3.3V ± 5%
Read Mode: 40mA (Max)
Write Mode: 60mA (Max)
5V
Standby Mode:6.5mA(Approach alues)
Read/ Write Peak: 100mA
Typical Power
Consumptions:
Read Mode: 20mA (Max)
Write Mode: 35 mA (Max)
3.3V
Standby Mode: 1mA (Approach values)
Read/ Write Peak: 100mA
Extended Temp.
-20°C to +85°C
Operating Temperature
Industrial Temp.
-40°C to +85°C
Extended Temp.
-40°C to +90°C
Storage Temperature
Industrial Temp.
-50°C to +90°C
Humidity Operation
5% to 95% (Non-condensing )
Environment conditions
Humidity Non-operation 5% to 95% (Non-condensing )
Shock Operation
3000-G (Max.)
Shock Non-operation
3000-G (Max.)
Vibration Operation
30-G (Peak to peak to maximum)
Vibration Non-operation 30-G (Peak to peak to maximum)
DOS
Operation System supported
Compatibility (Microsoft
Windows 98
Windows ME
Product)
Windows NT
Windows 2000
Windows XP
Operating Voltage
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2.2 Physical description
1.Weight and Measures
(unit: m)
2. Storage Capacities
3. Performance
Type I
Type II
Weight: 15 g
Pin-Pitch: 1.27 mm
Weight: 23 g
Pin-Pitch: 1.27 mm
Capacity
Data Transfer Rates
Error Correction
ECC
R/W Test
TCADO-SCF-000018.4
LxWxH
36.4 x 42.8 x 5.0 (mm)
256MB – 6GB
To/from Flash memory
(burst mode):
up to 20 Mbytes/sec
To/from host (burst mode):
up to 8 Mbytes/sec
1.2 ms
3,000,000 hours
More than 3 bit error correction per
second read
High reliability based on internal
ECC function
Testdisk:
1,000,000 Read/Write cycles
Data Access Time
MTBF
4. Reliability
LxWxH
36.4 x 42.8 x 3.3 (mm)
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3. Product Model & Ordering Information
CFA = Compact Flash Card
CFA-XXXX-13T-00-CP
XXXX: 032M
064M
128M
256M
512M
001G
002G
003G
004G
006G
008G
32Mbyte
64Mbyte
128Mbyte
256Mbyte
512Mbyte
1GByte
2GByte
3GByte
4GByte
6GByte
8GByte
T:
C
I
Commercial Temp. Range
0 / +70° Cel
Industrial Temp. Range
-40 / +85° Cel
CP:
Full Metal Housing
TCADO-SCF-000018.4
Type I
Type I
Type I
Type I
Type I
Type I
Type I
Type I
Type I
Type II
Type II
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4. Support Flash Media
4.1 Supported NAND Flash Type
4-1-1. Small block size of 16KB
Unit: bits
Flash Capacity
128 Mega
256 Mega
512 Mega
2.7V to 3.6V
Operation Voltage
4-1-2. Large block size of 128KB
Unit: bits
Flash Capacity
1 Giga
2 Giga
4 Giga
8 Giga
2.7V to 3.6V
Operation Voltage
4.2 Logical Format Parameters (CHS)
—
—
CF Type I (3.3mm)
Card Capacity*1
Unit: Bytes
Card Density*4
Cylinder
Heads
Sectors/Track*2
Total
Sectors/Card*3
Capacity*5
256M
992
16
32
512M
1007
16
63
507904
1,015,056
260,046,848 519,708,672
Unit: Bytes
*4
Card Density
Cylinder
Heads
Sectors/Track*2
Total
Sectors/Card*3
Capacity*5
TCADO-SCF-000018.4
1GB
2015
16
63
2GB
4030
16
63
3GB
6046
16
63
4GB
8061
16
63
2,031,120
4,062,240
6,094,368
8,125,488
3,120,316,416
4,160,249,856
1,039,933,440 2,079,866,880
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—
CF Type II (5.0mm)
Card Density*4
Cylinder
Heads
Sectors/Track*2
Total
Sectors/Card*3
Capacity*5
Notes:
1.
2.
3.
4.
5.
6GB
12092
16
63
12,188,736
6,240,632,832
These data are written in Identify table.
Total tracks =number of head x number of cylinder.
Total sector/Card = sector/track x number of head x number of cylinder
Those are general unformatted capacity of all cards.
It’s the logical address capacity including the area which is used for file system.
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5. Block Diagram
5.1 Controller Archive
Reset
Power
on
CompactFlash
Interface
Frequency Provider
Color
Control
Host
Interface
CIS CCR
Task
x51 Turbo base Micro processor
Data transfer
Control
Data buffer
ECC Logic
Flash
Memory
Interface
Control/
Status
NAND
Type
Flash
Memory
CIS: Card Information Structure
CCR: Card Configuration Register
ECC: Error Correcting Code
5.2 Flash Card Archive
Power IC
Host Interface
TCADO-SCF-000018.4
Reset IC
According Card Capacity From
Range 25MHz ~ 38MHz
Controller
Flash Memory
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6. Specification and Features
6.1 Electrical Specification
6.1.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
RATING
UNITS
VCC
Power supply
-0.3 to 6
V
VIN
Input voltage
-0.3 to VCC + 0.3
V
VOUT
Output voltage
-0.3 to VCC+ 0.3
V
TSTG
Storage temperature
-50 to 90
℃
Topr
Operating temperature
-40 to 85
℃
6.1.2 General DC Characteristic
SYMBOL
CIN
COUT
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input capacitance
15
pF
Output capacitance
15
pF
6.1.3 DC Electrical Characteristics for 5 Volts Operation
SYMBOL
PARAMETER
CONDITIONS
VIN
Input voltage
0
VCC
Power supply
4.5
TSTG
Storage temperature
TOPR
Operating temperature
VIL
Input low voltage
CMOS
VIH
Input high voltage
CMOS
VOL
Output low voltage
IOL=8mA
VOH
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Output high voltage
IOH=-8mA
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MIN
TYP
MAX
UNITS
VCC
V
5.5
V
-50
90
℃
-40
85
℃
0.8
V
5.0
2.4
V
0.4
VCC – 0.8
V
V
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S-CN CompactFlash Card Industrial Application
6.1.4 DC Electrical Characteristics for 3.3 Volts Operation
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
V
3.6
V
VIN
Input voltage
0
VDD
Power supply
3.0
TSTG
Storage temperature
-50
90
℃
TOPR
Operating temperature
-40
85
℃
VIL
Input low voltage
CMOS
0.6
V
VIH
Input high voltage
CMOS
VOL
Output low voltage
IOL=8mA
VOH
Output high voltage
IOH=-8mA
3.3
2.4
V
0.4
VDD – 0.8
V
V
6.1.5 Attribute Memory Read Timing Specification
Attribute Memory Read Timing
300 ns
Item
Symbol
IEEE Symbol
Read Cycle Time
tc(R)
tAVAV
Address Cycle Time
Card Enable Access Time
Output Enable Access Time
Output Disable Time from CE
Output Disable Time from OE
Address Setup Time
Output Enable Time from CE
Output Enable Time from OE
Data Valid from Address Change
ta(A)
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
tsu (A)
ten(CE)
ten(OE)
tv(A)
tAVQV
300
tELQV
300
tGLQV
150
tEHQZ
100
tGHQZ
100
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300
tAVGL
30
tELQNZ
5
tGLQNZ
5
tAXQX
0
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S-CN CompactFlash Card Industrial Application
6.1.6 Configuration Register(Attribute Memory)Write Timing Specification
Configuration Register(Attribute
Memory)Write Timing
250 ns
Item
Symbol
IEEE Symbol
Min ns
tc(W)
tAVAV
250
Write Pulse Width
tw(WE)
tWLWH
150
Address Setup Time
tsu(A)
tAVWL
30
Write Recovery Time
trec(WE)
tWMAX
30
tsu(D-WEH)
tDVWH
80
th(D)
tWMDX
30
Write Cycle Time
Data Setup Time for WE
Data Hold Time
Max ns
6.1.7 Common Memory Read Timing Specification
Item
Symbol
IEEE Symbol
ta(OE)
tGLQV
125
tdis(OE)
tGHQZ
100
Address Setup Time
tsu(A)
tAVGL
30
Address Hold Time
th(A)
tGHAX
20
CE Setup before OE
tsu(CE)
tELGL
0
CE Hold following OE
th(CE)
tGHEH
20
Wait Delay Falling from OE
tv(WT-OE)
tGLWTV
35
Data Setup for Wait Release
tv(WT)
tQVWTH
0
Wait Width Time
tw(WT)
tWTLWTH
Output Enable Access Time
Output Disable Time from OE
Min ns
Max ns
350 (3000 for
CF+)
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6.1.8 Common Memory Write Timing Specification
Item
Symbol
IEEE Symbol
Min ns
Data Setup before WE
tsu(D-WEH)
tDVWH
80
Data Hold following WE
th(D)
tWMDX
30
tw(WE)
tWLWH
150
Address Setup Time
tsu(A)
tAVWL
30
CE Setup before WE
tsu(CE)
tELWL
0
Write Recovery Time
trec(WE)
tWMAX
30
th(A)
tGHAX
20
th(CE)
tGHEH
20
Wait Delay Falling from WE
tv(WT-WE)
tWLWTV
WE High from Wait Release
tv(WT)
tWTHWH
Wait Width Time
tw (WT)
tWTLWTH
WE Pulse Width
Address Hold Time
CE Hold following WE
Max ns
35
0
350 (3000 for
CF+)
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6.1.9 I/O Input (Read) Timing Specification
Item
Symbol
IEEE Symbol
Data Delay after IORD
td(IORD)
tlGLQV
Data Hold following IORD
th(IORD)
tlGHQX
0
IORD Width Time
tw(IORD)
tlGLIGH
165
Address Setup before IORD
tsuA(IORD)
tAVIGL
70
Address Hold following IORD
thA(IORD)
tlGHAX
20
CE Setup before IORD
tsuCE(IORD)
tELIGL
5
CE Hold following IORD
thCE(IORD)
tlGHEH
20
REG Setup before IORD
tsuREG(IORD)
tRGLIGL
5
REG Hold following IORD
thREG(IORD)
tlGHRGH
0
INPACK Delay Falling from IORD
tdfINPACK(IORD)
tlGLIAL
0
INPACK Delay Rising from IORD
tdrINPACK(IORD)
tlGHIAH
45
IOIS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
Wait Delay Falling from IORD
tdWT(IORD)
tlGLWTL
35
Data Delay from Wait Rising
td(WT)
tWTHQV
0
tw(WT)
tWTLWTH
Wait Width Time
Min ns
Max ns
100
45
350 (3000 for
CF+)
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6.1.10 I/O Input (Write) Timing Specification
Item
Symbol
IEEE Symbol
Min ns
Max ns
Data Setup before IOWR
tsu(IOWR)
tDVIWH
60
Data Hold following IOWR
th(IOWR)
tlWHDX
30
IOWR Width Time
tw(IOWR)
tlWLIWH
165
Address Setup before IOWR
tsuA(IOWR)
tAVIWL
70
Address Hold following IOWR
thA(IOWR)
tlWHAX
20
CE Setup before IOWR
tsuCE(IOWR)
tELIWL
5
CE Hold following IOWR
thCE(IOWR)
tlWHEH
20
REG Setup before IOWR
tsuREG(IOWR)
tRGLIWL
5
REG Hold following IOWR
thREG(IOWR)
tlWHRGH
0
IOIS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
Wait Delay Falling from IOWR
tdWT(IOWR)
tlWLWTL
35
IOWR high from Wait high
tdrIOWR(WT)
tWTJIWH
tw(WT)
tWTLWTH
0
Wait Width Time
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0605V4
S-CN CompactFlash Card Industrial Application
6.1.11 True IDE Mode I/O (Read/Write) Timing Specification
True IDE Mode I/O
(Read/Write Timing
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
item
Specification)
t0
Cycle time (min)
(ns)
(ns)
(ns)
(ns)
(ns)
600
383
240
180
120
70
50
30
30
25
Address Valid to -IORD/-IOWR
t1
setup (min)
t2
-IORD/-IOWR (min)
165
125
100
80
70
t2
-IORD/-IOWR (min) Register (8 bit)
290
290
290
80
70
t 2i
-IORD/-IOWR recovery time (min)
-
-
-
70
25
t3
-IOWR data setup (min)
60
45
30
30
20
t4
-IOWR data hold (min)
30
20
15
10
10
t5
-IORD data setup (min)
50
35
20
20
20
t6
-IORD data hold (min)
5
5
5
5
5
30
30
30
30
30
90
50
40
n/a
n/a
60
45
30
n/a
n/a
20
15
10
10
10
0
0
0
0
35
35
35
35
35
1250
1250
1250
1250
250
t6Z
t7
t8
t9
tRD
-IORD data tristate (max)
Address valid to -IOCS16 assertion
(max)
Address valid to -IOCS16 released
(max)
-IORD/-IOWR to address valid hold
Read Data Valid to IORDY active
(min), if IORDY initially low after tA
tA
tA IORDY Setup time
tB
IORDY Pulse Width (max)
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6.1.12 True IDE Ultra DMA Mode I/O (Read/Write) Timing Specification
Name
UDMA
UDMA
UDMA
UDMA
UDMA
Mode 0 (ns)
Mode 1 (ns)
Mode 2 (ns)
Mode 3 (ns)
Mode 4 (ns)
Min
Max
Min
Max
Min
Max
Min
Max
Min
t2CYCTYP
240
160
120
90
60
CYC
112
73
54
39
25
t2CYC
tDS
tDH
tDVS
tDVH
tCS
tCH
tCVS
tCVH
tZFS
tDZFS
tFS
tLI
tMLI
tUI
tAZ
tZAH
tZAD
230
15.0
5.0
70.0
6.2
15.0
5.0
70.0
6.2
153
10.0
5.0
48.0
6.2
10.0
5.0
48.0
6.2
0
0
70.0
48.0
115
7.0
5.0
31.0
6.2
7.0
5.0
31.0
6.2
0
31.0
86
7.0
5.0
20.0
6.2
7.0
5.0
20.0
6.2
0
20.0
57
5.0
5.0
6.7
6.2
5.0
5.0
6.7
6.2
0
6.7
tENV
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
20
75
160
0
20
0
230
150
0
20
0
10
20
0
0
20
50
TCADO-SCF-000018.4
200
150
170
150
0
20
0
10
10
20
0
20
0
70
20 70
70
125
20
60
100
20
20
0
20
50
0
20
0
130
100
10
20
0
70
20
60
100
20
0
20
50
120
100
10
20
0
55
20
60
100
20
0
20
50
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0
20
0
Max
55
20
0
20
50
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S-CN CompactFlash Card Industrial Application
6.1.12.1 Ultra DMA Data-In Burst Initiation Timing
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6.1.12.2 Sustained Ultra DMA Data-In Burst Timing
6.1.12.3
Ultra DMA Data-In Burst Host Pause Timing
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6.1.12.4 Ultra DMA Data-In Burst Device Termination Timing
6.1.12.5 Ultra DMA Data-In Burst Host Termination Timing
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6.1.12.6 Ultra DMA Data-In Burst Host Termination Timing
6.1.12.7 Sustained Ultra DMA Data-Out Burst Timing
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6.1.12.8 Ultra DMA Data-Out Burst Device Pause Timing
6.1.12.9 Ultra DMA Data-Out Burst Device Termination Timing
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6.1.12.10 Ultra DMA Data-Out Burst Host Termination Timing
6.2 Power Management
6.2.1 Normal Mode
The host can reduce the power consumption of the card by changing its status with the following Power
Command.
Sleep mode consumes the lowest power. Response time for the card to change from sleep mode to the active
state is about 30 ms or less.
Standby mode, the response time is about 5ms or less. This is due to the interface of the card that accepts the
command although can't access the media immediately
Idle mode, the card can respond and access the media immediately. The card needs longer time in this mode
than in its active mode in order to active several circuits that were not used in the active mode.
Active mode, the card can respond and access the media immediately, and the commands are processed with
no delay.
6.2.2 Power down Mode
This card can set itself into Power Down mode. To enable this mode, it is needed to use the Information
Change command, which is a vender unique command. The advantage of using this mode is the ability to
move automatically into Sleep mode after command completion.
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6.3 Physical Specification
6.3.1 CompactFlash CF Type I
6.3.2 CompactFlash CF Type II
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7. Pin Assignment
7.1 CompactFlash Pin Type
PC Card Memory Mode
No. Pin Name
I/O
1
GND
2
D03
I/O
3
D04
I/O
4
D05
I/O
5
D06
I/O
6
D07
I/O
7
CE1#
I
8
A10
I
9
OE#
I
10
A09
I
11
A08
I
12
A07
I
13
VCC
14
A06
I
15
A05
I
16
A04
I
17
A03
I
18
A02
I
19
A01
I
20
A00
I
21
D00
I/O
22
D01
I/O
23
D02
I/O
24
WP
O
25
CD2#
O
26
CD1#
O
27
D11
I/O
28
D12
I/O
29
D13
I/O
30
D14
I/O
TCADO-SCF-000018.4
PC Card I/O Mode
No. Pin Name
I/O
1
GND
2
D03
I/O
3
D04
I/O
4
D05
I/O
5
D06
I/O
6
D07
I/O
7
CE1#
I
8
A10
I
9
OE#
I
10 A09
I
11 A08
I
12 A07
I
13 VCC
14 A06
I
15 A05
I
16 A04
I
17 A03
I
18 A02
I
19 A01
I
20 A00
I
21 D00
I/O
22 D01
I/O
23 D02
I/O
24 IOIS16#
O
25 CD2#
O
26 CD1#
O
27 D11
I/O
28 D12
I/O
29 D13
I/O
30 D14
I/O
31/139
True IDE Mode
No. Pin Name
I/O
1
GND
2
D03
I/O
3
D04
I/O
4
D05
I/O
5
D06
I/O
6
D07
I/O
7
CS0#
I
8
A10
I
9
ATASEL#
I
10 A09
I
11 A08
I
12 A07
I
13 VCC
14 A06
I
15 A05
I
16 A04
I
17 A03
I
18 A02
I
19 A01
I
20 A00
I
21 D00
I/O
22 D01
I/O
23 D02
I/O
24 IOCS16#
O
25 CD2#
O
26 CD1#
O
27 D11
I/O
28 D12
I/O
29 D13
I/O
30 D14
I/O
0605V4
S-CN CompactFlash Card Industrial Application
PC Card Memory Mode
31
D15
I/O
32
CE2#
I
33
VS1#
O
34
IORD#
I
35
IOWR#
I
36
WE#
I
37
RDY/BSY#
O
38
VCC
39
CSEL#
I
40
VS2#
O
41
RESET
I
42
WAIT#
O
43
INPACK#
O
44
REG#
I
45
BVD2
I/O
46
BVD1
I/O
47
D08
I/O
48
D09
I/O
49
D10
I/O
50
GND
PC Card I/O Mode
31 D15
I/O
32 CE2#
I
33 VS1#
O
34 IORD#
I
35 IOWR#
I
36 WE#
I
37 IREQ
O
38 VCC
39 CSEL#
I
40 VS2#
O
41 RESET
I
42 WAIT#
O
43 INPACK#
O
44 REG#
I
45 SPKR#
I/O
46 STSCH#G
I/O
47 D08
I/O
48 D09
I/O
49 D10
I/O
50 GND
True IDE Mode
31 D15
32 CS1#
33 VS1#
34 IORD#
35 IOWR#
36 WE#
37 INTRQ
38 VCC
39 CSEL#
40 VS2#
41 RESET#
42 IORDY
43 RFU*1
44 RFU*1
45 DASP#
46 PDIAG#
47 D08
48 D09
49 D10
50 GND
I/O
I
O
I
I
I
O
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
Note: 1. RFU is Reserved for Feature Use
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7.2 Signal Description
Signal Name
Description
I/O Pin
VCC
5V , 3.3V
(PC Card Memory Mode)
(PC Card I/O Mode)
(True IDE Mode)
13,38
GND
Ground.
(PC Card Memory Mode)
(PC Card I/O Mode)
(True IDE Mode)
1,50
A0-A10
These address lines along with the #REG signal are
(PC Card Memory Mode) used to select the I/O port address registers within the
card, the memory mapped port address registers
within the Card, a byte in the card's information
structure and its configuration control and status
registers.
A0-A10
This signal is the same as the PC Card Memory Mode
(PC Card I/O Mode)
signal.
A0-A10
In True IDE Mode only A0-A2 are used to select the
(True IDE Mode)
one of eight registers in the ATA Task File, the other
address lines should be grounded.
I 8,10,11,12,
14,15,16,17,
18,19,20
D0-D15
These lines carry the Data, Commands and Status
I/O 2,3,4,5,6,
(PC Card Memory Mode) between the host and controller. D00 is the LSB of the
21,22,23,27,
(PC Card I/O Mode)
even byte of the word. D08 is the LSB of the odd byte
28,29,30,31,
of the word.
47,48,49
D0-D15
In True IDE Mode, all Task File operations occur in
(True IDE Mode)
the byte mode on the low order D00-D07 while all
data transfers are 16 bits using D00-D15.
CD1#, CD2#
These Card Detect pins are connected to ground on
(PC Card Memory Mode) this card and used by the host to determine that the
(PC Card I/O Mode)
card is fully inserted into the socket.
(True IDE Mode)
O 25,26
VS1#,VS2#
Voltage Sense Signals.
(PC Card Memory Mode)
(PC Card I/O Mode)
(True IDE Mode)
O 33,40
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Signal Name
CSEL#
(PC Card Memory Mode)
CSEL#
(PC Card I/O Mode)
CSEL#
(True IDE Mode)
Description
This signal is not used for this mode.
I/O
Pin
I 39
This signal is not used of this mode.
This internally pulled up signal is used to configure
this card as a Master or a Slave. When this pin is
grounded, this card is Master. When this pin is open,
this card is Slave.
CE1#,CE2#
These signals are used both to select the card and to
I
(PC Card Memory Mode) indicate to the card whether a byte or a word
(PC Card I/O Mode)
operation is being performed. #CE2 always accesses
the odd byte of the word. #CE1 accesses the even
byte or the odd byte of the word depending on A0 and
#CE2.
7,32
CS0#, CS1#
(True IDE Mode)
In the True IDE Mode, #CS0 is the chip select for the
Task File Registers while #CS1 is used to select the
Alternate Status and the Device Control Register.
BVD1
(PC Card Memory Mode)
STSCHG#
(PC Card I/O Mode)
This signal is asserted high as the BVD1 signal since I/O
a battery is not used with this card.
This signal is asserted low to alert the host to changes
in the RDY/#BSY and Write Protect states, while the
I/O interface is configured. The Card Configure and
Status Register will control it.
In the True IDE Mode, this I/O is the Pass Diagnostic
signal in the Master/Slave handshake protocol.
46
This signal is always driven to a high state in Memory I/O
Mode since a battery is not required for this card.
This signal is always driven to a high state in I/O
Mode since this card does not support the audio
function.
In the True IDE Mode, this I/O is the Disk
Active/Slave Present signal in the Master/Slave
handshake protocol.
45
PDIAG#
(True IDE Mode)
BVD2
(PC Card Memory Mode)
SPKR#
(PC Card I/O Mode)
DASP#
(True IDE Mode)
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Signal Name
Description
OE#
(PC Card Memory Mode)
OE#
(PC Card I/O Mode)
|ATASEL#
(True IDE Mode)
This is an Output Enable Strobe generated I 9
by the host interface. It is used to read
data from the card in Memory Mode and
to read CIS and configuration registers.
In I/O Mode, this signal is used to read the
CIS and configuration registers.
To enable True IDE Mode, this signal
should be grounded.
RESET
(PC Card Memory Mode)
When the signal is high, the signal Resets
the card.
RESET
(PC Card I/O Mode)
When the signal is high, the signal Resets
the card.
RESET#
(True IDE Mode)
In the True IDE Mode, the signal is the
active low hardware reset from the host.
REG#
(PC Card Memory Mode)
This signal is used during Memory Cycle I 44
to distinguish between Common Memory
and Attribute Memory accesses. High for
Common Memory and Low for Attribute
Memory.
REG#
(PC Card I/O Mode)
This signal must be low during I/O Cycles
when the I/O address is on the Bus.
RFU
(True IDE Mode)
In the True IDE Mode, this signal is not
used and should be connected to VCC by
the host.
WE#
(PC Card Memory Mode)
This signal is driven by the host and used I 36
for generating memory write cycle to the
registers of the card when the card is
configured in the Memory mode.
In I/O mode, this signal is used for writing
the configuration registers.
In the True IDE Mode, this signal is not
used and should be connected to VCC by
the host.
WE#
(PC Card I/O Mode)
WE#
(True IDE Mode)
TCADO-SCF-000018.4
I/O Pin
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I 41
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S-CN CompactFlash Card Industrial Application
WAIT#
(PC Card Memory Mode)
(PC Card I/O Mode)
This signal is driven low by the card to O 42
notify the host to delay completion of the
memory of I/O cycle that is in progress.
IORDY
(True IDE Mode)
In the True IDE Mode, this signal may be
used as IORDY.
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Signal Name
I/O Pin
Description
INPACK#
(PC Card Memory Mode)
INPACK#
(PC Card I/O Mode)
O 43
This signal is not used in this mode.
The Input Acknowledge signal is asserted when the card is
selected and responds to an I/O read cycle at the address on the
address bus.
In the True IDE mode, this signal is not used.
RFU
(True IDE Mode)
IORD#
(PC Card Memory Mode)
IORD#
(PC Card I/O Mode)
I
34
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto the bus from the card when the card is
configured to use the I/O interface.
In the True IDE mode, the signal is the same as the I/O Mode.
IORD#
(True IDE Mode)
IOWR#
(PC Card Memory Mode)
IOWR#
(PC Card I/O Mode)
I
35
O 37
In the Memory Mode, this signal is set high when card is
ready to accept a new data transfer operation and held low
when the card is busy.
I/O Operation. After the card has been configured for I/O
Mode, this signal is used as Interrupt Request.
In the True IDE Mode, this signal is the active high Interrupt
Request to the host.
O 24
Memory Mode, the card doesn't have a write protect switch.
This signal is held low.
I/O Mode, A low signal indicates that a 16 bits or odd byte
only operation can be performed by the addressed port.
In the True IDE Mode, this signal is asserted low when this
device is expecting a word data transfer cycle.
IREQ#
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
WP
(PC Card Memory Mode)
IOIS16#
(PC Card I/O Mode)
IOCS16#
(True IDE Mode)
TCADO-SCF-000018.4
This signal is not used in this mode
The I/O Write strobe is used to clock I/O data on the Data bus
into the card controller registers when the card is configured to
use the I/O interface.
In the True IDE Mode, this signal is the same as the I/O mode.
IOWR#
(True IDE Mode)
RDY/BSY#
(PC Card Memory Mode)
This signal is not used in this mode.
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8. CIS and Functions Configuration Registers
Configuration register specifications
This card supports four Configuration registers for the purpose of the configuration and observation of
this card. These registers can be used in memory and I/O card mode. In True IDE mode, these register
can not be used.
8.1 Configuration Option Register (200H)
This register is used for the configuration of the card and allows issuing software reset through this
register.
<Reset value = 00H>
D7
D6
D5
SRESET
LevlREQ INDEX
R/W
R/W
D4
D3
D2
D1
D0
R/W
Index
Those bits are used for selecting an operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Rest, this data is “000000” for the Memory mode
card interface recognition.
LevlREQ This bit sets to “0” when pulse mode interrupt is selected, and sets to “1” when level mode
interrupt is selected.
SRESET Setting this bit to “1”, places the card in the reset state (Card Hard Reset).This operation is
equal to Hard Reset, except this bit is not cleared. Card configuration status is reset and the
card internal initialized operation starts when Card Hard Reset is executed, so next access to
the card should be the same sequence as the power on sequence.
Index Bits Assignment
INDEX bits
Task File register address
Mapping mode
5
4
3
2
1
0
0
0
0
0
0
0
OH to FH, 400h to 7FFH
Memory mode
0
0
0
0
0
1
xx0H to xxFH
Independent I/O mode
0
0
0
0
1
0
0
0
0
0
1
1
TCADO-SCF-000018.4
1F0H to 1F7H, 3F6H to
3F7H
170H to 177H, 376H to
377H
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Primary I/O mapped
Secondary I/O mapped
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S-CN CompactFlash Card Industrial Application
8.2 Card Configuration And Status Register (Address 202H)
This register is used for observing the card state.
<Reset value = 00H>
D7
D6
D5
D4
D3
D2
D1
D0
CHGED
SIGCHG
IOIS8
0
0
PWD
INTR
0
R
R/W
R/W
---
---
R/W
R
---
INTR
PWD
IOIS8
SIGCHG
CHGED
INTERRUPT: When set, indicates that the #IREQ pin is low. When clear, indicates that the
#IREQ pin is high. This bit state is available whether I/O card interface has been configured
or not. If interrupts are disabled by the #IEN bit in the Device Control Register, this bit is
zero.
POWER DOWN: When set, the card enters sleep state (Power Down mode). When clear,
the card transfers to idle state (active mode).
I/O IS 8 bit: When set, indicates that the data bus width of the host is 8 bits (D0-D7). When
clear, indicates that the data bus width of the host is 16 bits (D0-D15).
SIGNAL CHGED: This bit is set and reset by the host to enable and disable a state-change
signal from the Status Register, the CHANGED bit control pin 46 and the CHANGED
Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46
(#STSCHG) signal will be held high while thie card is configured for I/O.
Indicated that one or both of the pin Replacement Register (204H) Crdy, or CWProt bits are
set to one (1). When changed bit is set, #STSCHG pin 46 is held low if the SIGCHG bit is a
one (1) and the card is configured for I/O interface.
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8.3 Pin Replacement Register (Address 204H)
This register is used for providing the signal state of #IREQ signal when the card configured I/O card interface.
<Reset value = 0CH>
D7
D6
D5
D4
D3
D2
D1
D0
0
0
CRDY
0
1
1
RRDY
RWProt
R/W
0
--RWProt
PRDY
CEProt
CRDY
R/W
---
READ WRITE PROTECT: this bit indicates the write protect status. When set, indicates
write protect. When cleared indicates write is enable.
This bit is used to determine the internal state of the RDY/BSY signal. This bit may be used
to determine the state of the Ready/Busy as this pin has been reallocated for use as interrupt
Request on an I/O card.
This bit is set to one (1) when RWProt changes state. This bit may be written by the host.
CARD READY: This bit is set to one (1) when the READY bit changes state. This bit may
be written by the host.
8.4 Socket and Copy Register (Address 206H)
This register is used for identification of the card from other cards. The host can read and write this
register. The host shall set this register before the card’s Configuration Option Register is set.
<Read, Reset value = 00H>
DRV#
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
DRV#
0
0
0
0
---
---
---
R/W
---
---
---
---
DRIVE NUMBER: This bit is set by the host and compared to the DRV bit (D4), in the
ATA Drive/Head Register. In this way, host can perform the card’s master/slave
organization.
TCADO-SCF-000018.4
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8.5 Card Information Structure (CIS)
The CIS is attribute information of the card and its characteristics, which includes information about the
type of card and the manufacturer. The CIS is allocated in the beginning of the attribute memory, between
addresses 0 and 255. The data is allocated in the even addresses only. The Host uses these registers to
initialize and configure the card.
Address
Data
7
000H
01H
CISTPL_JEDEC
Device info tuple
Tuple code
002H
04H
TPL_LINK
Link length is 4 byte
Link to next tuple
004H
02H
Device type W Device speed
Device type= DH: I/O device
Device type, WPS, speed
006H
79H
6
5
4
3
2
1
0 Description of contents
P
WPS=1:No WP
S
Device Speed=7: ext speed
EXT Speed
Speed
CIS function
400 ns if not wait
Extended speed
2k byte of address space
Device size
Mantissa exponent
008H
01H
1x
2k units
00AH
FFH
List end marker
End of device
End marker
00CH
1CH
CISTP_DEVICE_OC
Other conditions device info tuple
Tuple code
00EH
04H
TPL_LINK
Link length 4 bytes
Link to next tuple
010H
02H
EXT Reserved Vcc MWAIT
3V, wait is not used
Other conditions info field
012H
DBH
Device type W Device speed
Device type= DH: I/O device
Device type, WPS, speed
P
WPS=1:No WP
S
Device Speed=1:250 ns
2k units
2k byte of address space
Device size
014H
01H
1x
016H
FFH
List end marker
End of device
END marker
018H
18H
CISTPL_JEDEC_C
JEDEC ID common memory
Tuple code
01AH
02H
TPL_LINK
Link length is 2 bytes
Link to next tuple
01CH
DFH
Manufacturer’s ID code
JEDEC ID of PC Card ATA
01EH
01H
PCMCIA JEDEC device code
2nd byte of JEDEC ID
020H
20H
CISTPL_MANFID
Manufacturer’s ID code
Tuple code
022H
04H
TPL_LINK
Link length is 4 bytes
Link to next tuple
024H
45H
026H
00H
028H
01H
Low byte of product code
02AH
04H
High byte of product code
02CH
15H
CISTPL_VERS_1
TCADO-SCF-000018.4
PCMCIA’s manufacturer’s
JEDEC ID Code
Low byte of PCMCIA
manufacturer’s code
manufacturer’s ID
Low byte of manufacturer’s ID
code
High byte of PCMCIA
Code of 0 because other byte is
High byte of manufacturer’s ID
manufacturer’s code
JEDEC 1 byte manufacturer’s ID
code
For PC CARD ATA
Low byte of product code
High byte of product code
Level 1 version/product info
41/139
Tuple code
0605V4
S-CN CompactFlash Card Industrial Application
Address
Data
7
6
5
4
3
2
1
02EH
1AH
T
P
L
_
L
I
N
030H
04H
T P P L V 1 _ M A J O R PCMCIA2.0/JEIDA4.1
Major version
032H
01H
T P P L V 1 _ M I N O R PCMCIA2.0/JEIDA4.1
Minor version
034H
43H
‘C’
036H
46H
‘F’
038H
20H
‘’
03AH
43H
‘C’
03CH
61H
‘a’
03EH
72H
‘r’
040H
64H
‘d’
042H
00H
Null terminator
044H
43H
‘C’
046H
46H
‘F’
048H
41H
‘A’
04AH
20H
‘’
04CH
XXH
‘X’
04EH
XXH
‘X’
050H
XXH
‘X’
052H
XXH
‘X’
054H
4DH
‘M’
056H
42H
‘B’
058H
20H
‘‘
05AH
43H
‘C’
05CH
4BH
‘K’
05EH
52H
‘S’
060H
00H
Null terminator
062H
FFH
L i s t
064H
21H
C I S T P L _ F U N C I D Function ID tuple
Tuple code
066H
02H
T
Link to next tuple
068H
04H
TPLFID_FUNCTION=04H Disk function, may be silicon, may be
P
e n d
L
_
0 Description of contents
CIS function
K Link length is 26 bytes
Link to next tuple
m a r k e r End of device
L
I
N
K Link length is 2 bytes
Info string 1
Info string 2
According for card capacity.
END marker
PC card function code
removable
06AH
01H
Reserved
R
P R=0: No BIOS ROM
System initialization byte
P=1: Configure card at power on
TCADO-SCF-000018.4
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Address
Data
7
6
06CH
22H
C I S T P L _ F U N C E Function extension tuple
Tuple code
06EH
02H
T
Link to next tuple
070H
01H
Disk function extension tuple type Disk interface type
Extension tuple type for disk
072H
01H
D i s k i n t e r f a c e t y p e PC card ATA interface
Interface type
074H
22H
C I S T P L _ F U N C E Function extension tuple
Tuple code
076H
03H
T
Link to next tuple
078H
02H
Disk function extension tuple type Single drive
Extension tuple type for disk
07AH
0CH
Reserve
V No Vpp< Silicon, single drive
Basic ATA option
V=0: No Vpp required
Parameter byte 2
P
P
5
L
L
4
_
_
3
L
L
D
2
I
I
U
1
N
N
S
0 Description of contents
K Link length 2 bytes
K Link length is 3 bytes
CIS function
S=1: Silicon
U=1: Unique serial#
D=0: Single drive on card
07CH
0FH
R I E N P 3 P 2 P 1 P 0 P0: Sleep mode supported
P1: Standby mode supported
Basic ATA option parameter
byte 2
P2: Idle mode supported
P3: Drive auto power control
N: Some config excludes 3X7
E: Index bit is emulated
I: Twin IOIS 16# datd reg only
R: Reserved
07EH
1AH
C I S T P L _ C O N F I G Configuration tuple
Tuple code
080H
05H
T
Link to next tuple
082H
01H
RFS
P
L
_
L
RMS
I
N
K Link length is 5 bytes
R A S RFS: Reserved
Size of fields byte TPCC_SZ
RMS: TPCC_RMSK size-1=0
RAS:TPCC_RADR size-1=1
1 byte register mask
2 b2 byte config base address
084H
03H
T P C C _ L A S T Entry with config index of 03H is
Last entry of config registers
final entry in table
086H
00H
T P C C _ R A D R ( L S B ) Configuration registers are located at
Location of config registers
200H in REG space
088H
02H
TCADO-SCF-000018.4
TPCC_RADAR(MSB)
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Address
Data
7
6
5
4
3
2
1
0 Description of contents
CIS function
08AH
0FH
Reserved
S
P
C
I I: Configuration index
Configuration registers present
C: configuration and status
mask TPCC_RMSK
P: Pin replacement
S: Socket and copy
08CH
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
08EH
08H
T
P
Link to next tuple
090H
C0H
I
D Configuration Index Memory mapped I/O configuration
L
_
L
I
N
K Link length is 8 bytes
I=1: Interface byte follows
Configuration table index byte
TPCE_INDX
D=1: Default entry
Configuration index=0
092H
40H
W R P B Interface type W=0: Wait not used
R=1: Ready active
Interface description field
TPCE_IF
P=0: WP not used
B=0: BVD1and BVD2 not used
IF type=0: Memory interface
094H
A1H
M
MS
IR
IO
T
P M=1: Misc info present
MS=01: Memory space info single
Feature selection
TPCE_FS
2-byte length
IR=0: No interrupt info present
IO=0: No I/O port info present
T=0: No toming info present
P=1: Vcc only info
096H
01H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
098H
55H
TCADO-SCF-000018.4
X
Mantissa
E x p o n e n t Nominal voltage=5V
44/139
Vcc nominal value
0605V4
S-CN CompactFlash Card Industrial Application
Address
Data
7
6
5
4
3
2
1
0 Description of contents
09AH
08H
Length in 256 bytes pages (LSB) Length of memory space is 2 KB
CIS function
Memory space description
structures (TPCE_MS)
09CH
00H
Length in 256 bytes pages (MSB)
09EH
20H
X
R
P
R O
A
T X=0: No more misc fields
R: Reserved
Miscellaneous features field
TPCE_MI
P=1: Power down supported
RO=0: Not read only mode
A=0: Audio not supported
T=0: Single drive
0A0H
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
0A2H
06H
T
P
Link to next tuple
0A4H
00H
I
D Configuration Index Memory mapped I/O configuration
L
_
L
I
N
K Link length is 6 bytes
I=0: No interface byte
Configuration table index
TPCE_INDX
D=0: No Default entry
Configuration index=0
0A6H
01H
M
MS
IR
IO
T
P M=0: No misc info
MS=00: No memory space inflo
Feature selection byte
TPCE_FS
IO=0: No I/O port info present
T=0:No timing info present
P=0: Vcc only info
0A8H
21H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0AAH
B5H
X
0ACH
1EH
X
TCADO-SCF-000018.4
Mantissa
E x p o n e n t Nominal Voltage=3.0V
E x t e n s i o n +0.3 V
45/139
Vcc nominal value
Extension byte
0605V4
S-CN CompactFlash Card Industrial Application
Address Data
7
0AEH
X Mantissa Exponent
4DH
6
5
4
3
2
1
0 Description of contents
Max average current over 10 msec is
CIS function
Max. average current
45 mA
0B0H
1BH
CISTPL_CFTABLE_ENTRY
Configuration table entry tuple
Tuple code
0B2H
0AH
TPL_LINK
Link length is 10 bytes
Link to next tuple
0B4H
C1H
I D Configuration INDEX
Contiguous I/O mapped ATA registers Configuration table index byte
configuration
TPCE_INDX
I=1: Interface byte follows
D=1: Default entry
Configuration index=1
0B6H
41H
W R P B Interface type
W=0: Wait not used
Interface description field
R=1: Ready active
TPCE_IF
P=0: WP not used
B=0: BVS1 and BVS2 not used
IF type=1: I/O interface
0B8H
99H
M MS IR IO T P
M=1: Misc info present
Feature selection byte
MS=00: No memory space info
TPCE_FS
IR=1: Interrupt info present
IO=1: I/O port info present
T=0: No timing info present
P=1:Vcc only info
0BAH
01H
R DI PI AI SI HV LV NV
Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0BCH
55H
X Mantissa Exponent
Nominal Voltage=5V
Vcc nominal value
0BEH
64H
R S E IO AddrLine
S=1: 16-bit hosts supported
I/O space description field
E=1: 8-bit hosts supported
TPCE_IO
IO AddrLine:4 lines decoded
TCADO-SCF-000018.4
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Address Data
7
6
5
4
3
2
1
0 Description of contents
CIS function
0C0H
S
P
L
M
V
B
I
N S=1: Share logic active
Interrupt request description
F0H
P=1: Pulse mode IRQ supported
structure TPCE_IR
L=1: Level mode IRQ supported
M=1: Bit mask of IRQ present
V=0: No vender unique IRQ
B=0: No bus error IRQ
I=0: No IO check IRQ
N=0: No NMI
0C2H
FFH
IRQ IR IR IR IR IR OR IRQ0 IRQ level to be routed 0 to 15
Mask extension byte 1
7
TPCE_IR
Q
6
0C4H
FFH
Q
5
Q
4
Q
Q
Q recommended
3
2
1
IRQ IR IR IR IR IR OR IRQ8 Recommended routing to any
Mask extension byte 2
15
TPCE_IR
Q
Q
Q
Q
Q
Q “normal, maskable” IRQ
14 13 12 11 10 9
0C6H
20H
X
R
P
R O
A
T X=0: Nomore misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P=1: Power down supported
RO=0: Not read only mode
A=0: Audi not supported
T=0: Single drive
TCADO-SCF-000018.4
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Address
Data
7
6
5
0C8H
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
0CAH
06H
T
P
Link to next tuple
0CCH
01H
I
D Configuration index Contiguous I/O mapped ATA registers Configuration table index byte
L
4
_
3
L
2
I
1
N
0 Description of contents
K Link length is 6 bytes
configuration
CIS function
TPCE_INDX
I=0: No Interface byte
D=0: No Default entry
Configuration index=1
0CEH
01H
M
MS
IR
IO
T
P M=0: No Misc info present
MS=00: No memory space info
Feature selection byte
TPCE_FS
IR=0: No Interrupt info present
IO=0: No I/O port info present
T=0: No timing info present
P=1:Vcc only info
0D0H
21H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0D2H
B5H
X
0D4H
1EH
X
0D6H
4DH
X
M a n t i s s a E x p o n e n t Nominal voltage =3.0V
E x t e n s i o n +0.3V
M a n t i s s a E x p o n e n t Max average current over 10 msec is
Vcc nominal value
Extension byte
Max. average current
45mA
TCADO-SCF-000018.4
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Card Industrial Application
Address
Data
7
6
5
0D8H
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
0DAH
0FH
T
P
Link to next tuple
0DCH
C2H
I
D Configuration index Contiguous I/O mapped ATA registers Configuration table index byte
L
4
_
3
L
2
I
1
N
0 Description of contents
K Link length is 15 bytes
configuration
CIS function
TPCE_INDX
I=1: Interface byte follows
D=1: Default entry follows
Configuration index=2
0E0H
41H
W R P B Interface type W=0: Wait not used
R=1: Ready active
Interface description field
TPCE_IF
P=0: WP not used
B=0: BVS1 and BVS2 not used
IF type=1: I/O interface
0E2H
99H
M
MS
IR
IO
T
P M=1: Misc info present
MS=00: No memory space info
Feature selection byte
TPCE_FS
IR=1: Interrupt info present
IO=1: I/O port info present
T=0: No timing info present
P=1:Vcc only info
0E4H
01H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0E6H
55H
TCADO-SCF-000018.4
X
Mantissa
E x p o n e n t Nominal Voltage=5V
49/139
Vcc nominal value
0605V4
S-CN CompactFlash Card Industrial Application
Address
Data
7
6
5
4
3
2
1
0 Description of contents
0E8H
EAH
R S E I O A d d r L i n e R=1: Range follows
S=1:16-bit hosts supported E=1: 8-bit
CIS function
I/O space description field
TPCE_IO
hosts supported
IO AddrLines: 10 lines decoded
0EAH
61H
0ECH
FOH
1st I/O base address(LSB)
0EEH
01H
1st I/O base address(MSB)
0F0H
07H
1st I/O length-1
1st I/O range length
0F2H
F6H
2nd I/O base address(LSB)
2nd I/O range address
0F4H
03H
2nd I/O base address(MSB)
0F6H
01H
2nd I/O length-1
0F8H
EEH
S P L M
I R Q l e v e l S=1: Share logic active
P=1: Pulse mode IRQ supported
1st I/O range address
2nd I/O range length
Interrupt request description
structure TPCE_IR
L=1: Level mode IRQ supported
M=0: Bit mask of IRQ present
IRQ level is ORQ 14
0FAH
20H
X
R
P
R O
A
T X=0: Nomore misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P=1: Power down supported
RO=0: Not read only mode
A=0: Audi not supported
T=0: Single drive
TCADO-SCF-000018.4
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Address
Data
7
6
5
0FEH
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
0FCH
06H
T
P
Link to next tuple
100H
02H
I
D Configuration index ATA primary I/O mapped
L
4
_
3
L
2
I
1
N
0 Description of contents
K Link length is 15 bytes
configuration
CIS function
Configuration table index byte
TPCE_INDX
I=0: No Interface byte
D=0: No Default entry
Configuration index=2
102H
01H
M
MS
IR
IO
T
P M=0: No Misc info
MS=00: No memory space info
Feature selection byte
TPCE_FS
IR=0: No Interrupt info present
IO=0: No I/O port info present
T=0: No timing info present
P=1: Vcc only info
104H
21H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
106H
B5H
X
108H
1EH
X
10AH
4DH
X
M a n t i s s a E x p o n e n t Nominal voltage =3.0V
E x t e n s i o n +0.3V
M a n t i s s a E x p o n e n t Max average current over 10 msec is
Vcc nominal value
Extension byte
Max. average current
45mA
10CH
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
10EH
0FH
T
P
Link to next tuple
110H
C3H
I
D Configuration index ATA secondary I/O mapped
L
_
L
I
N
K Link length is 15 bytes
configuration
Configuration table index byte
TPCE_INDX
I=1: Interface byte follow
D=1: Default entry
Configuration index=3
TCADO-SCF-000018.4
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S-CN CompactFlash Card Industrial Application
Address
Data
7
6
5
4
3
2
1
0 Description of contents
114H
41H
W R P B Interface type W=0: Wait not used
R=1: Ready active
CIS function
Interface description field
TPCE_IF
P=0: WP not used
B=0: BVS1 and BVS2 not used
IF type=1: I/O interface
112H
99H
M
MS
IR
IO
T
P M=1: Misc info present
MS=00: No memory space info
Feature selection byte
TPCE_FS
IR=1: Interrupt info present
IO=1: I/O port info present
T=0: No timing info present
P=1:Vcc only info
116H
01H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
118H
55H
X
Mantissa
E x p o n e n t Nominal Voltage=5V
11AH
EAH
R S E I O A d d r L i n e R=1: Range follows
S=1:16-bit hosts supported E=1: 8-bit
Vcc nominal value
I/O space description field
TPCE_IO
hosts supported
IO AddrLines: 10 lines decoded
11CH
61H
LS
AS
N
r a n g e LS=1: Size of lengths is 1 byte
I/O range format description
AS=2: Size of address is 2 bytes
N Range=1: Address range-1
11EH
70H
1st I/O base address(LSB)
120H
01H
1st I/O base address(MSB)
122H
07H
1st I/O length-1
1st I/O range length
124H
76H
2nd I/O base address(LSB)
2nd I/O range address
126H
03H
2nd I/O base address(MSB)
128H
01H
2nd I/O length-1
TCADO-SCF-000018.4
52/139
1st I/O range address
2nd I/O range length
0605V4
S-CN CompactFlash Card Industrial Application
Address
Data
7
6
5
4
12CH
EEH
S P L M
3
2
1
0 Description of contents
I R Q l e v e l S=1: Share logic active
P=1: Pulse mode IRQ supported
CIS function
Interrupt request description
structure TPCE_IR
L=1: Level mode IRQ supported
M=0: Bit mask of IRQ present
IRQ level is ORQ 14
12AH
20H
X
R
P
R O
A
T X=0: Nomore misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P=1: Power down supported
RO=0: Not read only mode
A=0: Audi not supported
T=0: Single drive
12EH
1BH
CISTPL_CFTABLE_ENTRY Configuration table entry tuple
Tuple code
130H
06H
T
P
Link to next tuple
132H
03H
I
D Configuration index ATA secondary I/O mapped
L
_
L
I
N
K Link length is 6 bytes
configuration
Configuration table index byte
TPCE_INDX
I=0: No Interface byte
D=0: No Default entry
Configuration index=3
134H
01H
M
MS
IR
IO
T
P M=0: No Misc info
MS=00: No memory space info
Feature selection byte
TPCE_FS
IR=0: No Interrupt info present
IO=0: No I/O port info present
T=0: No timing info present
P=1: Vcc only info
136H
21H
R DI PI AI SI HV LV NV Nominal voltage only follows
Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
TCADO-SCF-000018.4
53/139
0605V4
S-CN CompactFlash Card Industrial Application
Address
Data
7
6
5
4
140H
B5H
X
138H
1EH
X Extension
142H
4DH
X
3
2
1
0 Description of contents
M a n t i s s a E x p o n e n t Nominal voltage =3.0V
+0.3V
M a n t i s s a E x p o n e n t Max average current over 10 msec is
CIS function
Vcc nominal value
Extension byte
Max. average current
45mA
144H
14H
146H
00H
148H
FFH
TCADO-SCF-000018.4
CISTPL_NO_LINK
CISTPL_END
No link control tuple
Tuple code
Link is 0 bytes
Link to next tuple
End of tuple
Tuple code
54/139
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S-CN CompactFlash Card Industrial Application
9. ATA Specific Register Definitions
As we described the adapter provides several kinds of addressing modes, Memory mode, I/O mode, and
True IDE. Below are described the procedures access for accessing each mode the Task File registers.
9.1 Memory Mapped Addressing
Memory Mapped Addressing
#REG
1
1
1
1
1
1
1
1
1
Offset
0H
1H
2H
3H
4H
5H
6H
7H
8H
A10
0
0
0
0
0
0
0
0
0
1
9H
0
1
DH
1
1
1
1
EH
FH
8H
9H
TCADO-SCF-000018.4
A4 – A9
X
X
X
X
X
X
X
X
X
A3
0
0
0
0
0
0
0
0
1
A2
0
0
0
0
1
1
1
1
0
A1
0
0
1
1
0
0
1
1
0
A0
0
1
0
1
0
1
0
1
0
X
1
0
0
1
0
X
1
1
0
1
#OE = “0”
Even read data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status
Duplicate Even
Read Data
Duplicate Odd
Read Data
Duplicate Error
0
0
1
1
X
X
X
X
1
1
X
X
1
1
X
X
1
1
X
X
0
1
0
1
Alternate Status
Drive Address
Even Read Data
Odd Read Data
55/139
#WE = “0”
Even write data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Command
Duplicate Even
Write Data
Duplicate Odd
Write Data
Duplicate
Feature
Device Control
Reserved
Even Write Data
Odd Write Data
0605V4
S-CN CompactFlash Card Industrial Application
9.2 Contiguous I/O Mapping Addressing
Contiguous I/O Mapping Addressing
#REG
0
0
0
0
Offset
0H
1H
2H
3H
A10
0
0
0
0
0
0
0
0
0
4H
5H
6H
7H
8H
0
0
0
0
0
0
9H
0
A3
0
0
0
0
A2
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
X
X
X
X
X
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
X
1
0
0
1
DH
0
X
1
1
0
1
0
EH
0
X
1
1
1
0
0
FH
0
X
1
1
1
1
TCADO-SCF-000018.4
A4 – A9
X
X
X
X
56/139
#IORD = “0”
Even read data
Error
Sector Count
Sector
Number
Cylinder Low
Cylinder High
Drive/Head
Status
Duplicate
Even Read
Data
Duplicate Odd
Read Data
Duplicate
Error
Alternate
Status
Drive Address
#IOWR = “0”
Even write data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Command
Duplicate Even
Write Data
Duplicate Odd
Write Data
Duplicate
Feature
Device Control
Reserved
0605V4
S-CN CompactFlash Card Industrial Application
9.3 Overlapping I/O Mapping Addressing
Overlapping I/O Mapping (Primary, Secondary) Addressing
A4 – A9
Primary Secondary
#REG
A10
A3
A2
A1
A0
0
X
1FH
17H
0
0
0
0
0
0
X
X
1FH
1FH
17H
17H
0
0
0
0
0
1
1
0
0
X
1FH
17H
0
0
1
1
0
0
0
0
X
X
X
X
1FH
1FH
1FH
1FH
17H
17H
17H
17H
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
X
3FH
37H
1
1
1
0
0
X
3FH
37H
1
1
1
1
#IORD= “0”
#IOWR =“0”
Even read data Even write
data
Error
Feature
Sector Count
Sector Count
Sector
Sector
Number
Number
Cylinder Low Cylinder Low
Cylinder High Cylinder High
Drive/Head
Drive/Head
Status
Command
Alternate
Device
Status
Control
Drive Address Reserved
9.4 True IDE Mode
True IDE Mode
#CS0
#CS1
DA2
DA1
DA0
#IORD = “0”
#IOWR = “0”
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
1
X
1
1
0
0
0
0
1
1
1
1
X
X
0
X
1
1
0
0
1
1
0
0
1
1
X
X
X
X
0
1
0
1
0
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Invalid
Alternate Status
Device Address
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status
Not Used
Not Used
Not Used
Invalid
Device Control
Not Used
Data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Command
TCADO-SCF-000018.4
57/139
0605V4
S-CN CompactFlash Card Industrial Application
9.5 ATA Registers
9.5.1 Data Register
The Data register is a 16-bit register used to transfer data blocks between the ATA data buffer and the host.
In addition, the Format Track command uses this register to transfer the sector-information. Setting this
mode requires calling the Set Features command.
bit-7
D7
bit-6
D6
bit-5
D5
bit-4
D4
bit-3
D3
bit-2
D2
bit-1
D1
bit-0
D0
bit-15
D15
bit-14
D14
bit-13
D13
bit-12
D12
bit-11
D11
bit-10
D10
bit-9
D9
bit-8
D8
9.5.2 Error Register
The Error Register contains additional information about the source of an error. The information in the
register is only valid when an error is indicated in ERR-bit (bit-0 = 1) of the Status Register. This register is
valid when the BSY bit in Status register and Alternate status register are set to “0”(Ready).
bit-7
BBK
BBK
UNC
MC[0]
IDNF
MCR[0]
ABRT
T0NF[0]
AMNF
TCADO-SCF-000018.4
bit-6
UNC
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
MC[0]
IDNF
MCR[0] ABRT
T0NF[0] AMNF
Bad Block mark detected in the requested sector ID field - Not
supported
Non-Correctable data error encountered
Removable media access ability has changed - not supported (is 0)
Requested sector ID-field Not Found
Media Change Request indicates that the removable-media drive's
latch has changed, indicating that the user wishes to remove the
media - not supported (is 0)
Drive status error or Aborted invalid command
Track 0 Not Found during a Recalibrate command - Not
supported
Address Mark Not Found after finding the correct ID field - Not
supported
58/139
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S-CN CompactFlash Card Industrial Application
9.5.3 Feature Register
This register enables drive-specific features. See the Set Features or Get/Set Features command
descriptions.
bit-7
bit-6
Feature byte
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
9.5.4 Sector Count Register
The Sector Count Register contains the number of data sectors requested to be transferred during a read or
write operation between the host and the adapter. A zero register value specifies 256 sectors. The
command was successful if this register is zero at command completion. If the request is not completed,
the register contains the number of sectors left to be transferred.
This register’s initial values is “01H”
Some commands (e.g. Initialize Drive Parameters or Format Track) may redefine the register’s contents.)
bit-7
bit-6
Sector count byte
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
9.5.5 Sector Number Register
In the CHS (Cylinder, Head, Sector) mode, the Sector Number register contains the subsequent command's
starting sector number, which can be from 1 to the maximum number of sectors per track. In LBA (logical
block address) mode, this register contains LBA bits 0-7, which are updated at command completion. See
the command descriptions for register contents at command completion (whether successful or
unsuccessful).
bit-7
bit-6
bit-5
bit-4
bit-3
SN7
SN6
SN5
SN4
SN3
LBA7
LBA6 LBA5
LBA4
LBA3
SN0 – SN7
Sector number byte (8-bits)
LBA0 – LBA7
LBA bits 0 to 7
TCADO-SCF-000018.4
59/139
bit-2
SN2
LBA2
bit-1
SN1
LBA1
bit-0
SN0
LBA0
0605V4
S-CN CompactFlash Card Industrial Application
9.5.6 Cylinder Low Register
In the CHS mode, the Cylinder Low Register contains the cylinder number low-8 bits and reflects their
status at command completion. In LBA mode, this register contains LBA bits 8-15 and reflects their status
at command completion.
bit-7
bit-6
bit-5
bit-4
bit-3
CL7
CL6
CL5
CL4
CL3
LBA15 LBA14 LBA13 LBA12 LBA11
CL0 – CL7
Cylinder Low byte (8-bits)
LBA8 – LBA15
LBA bits 8 to 15
bit-2
CL2
LBA10
bit-1
CL1
LBA9
bit-0
CL0
LBA8
9.5.7 Cylinder High Register
In the CHS mode, the Cylinder High Register contains the cylinder numbers high-8 bits and reflects their
status at command completion. In LBA mode, this register contains LBA bits 16-23 and reflects their status
at command completion.
bit-7
bit-6
CH7
CH6
LBA23 LBA22
CH0 – CH7
LBA16 – LBA23
TCADO-SCF-000018.4
bit-5
bit-4
bit-3
CH5
CH4
CH3
LBA21 LBA20 LBA19
Cylinder High byte (8-bits)
LBA bits 16 to 23
60/139
bit-2
CH2
LBA18
bit-1
CH1
LBA17
bit-0
CH0
LBA16
0605V4
S-CN CompactFlash Card Industrial Application
9.5.8 Drive Head Register
The Drive/Head Register is used to select the drive and head (heads minus 1, when executing Initialize
Drive Parameters command). It is also used to select the LBA addressing instead of the CHS addressing.
bit-7
bit-6
1
LBA
HS0-HS3/
DRV
LBA24-LBA27
LBA
TCADO-SCF-000018.4
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
1
DRV
HS3
HS2
HS1
HS0
Head number.
Drive select number. When DRV=0, the master drive is selected.
When DRV=1, the Slave drive is selected.
MSB of the LBA addressing.
Address mode select.
0 = CHS (Cylinder, Head, Sector) mode.
1 = LBA (Logical Block Address) mode.
Logical Block address interrupted as follows:
LBA07-LBA00 :Sector Number Register D7-D0
LBA15-LBA08:Cylinder Low Register D7-D0
LBA23-LBA16:Cylinder High Register D7-D0
LBA27-LBA24:Drive/Head Register HS3-HS0
61/139
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S-CN CompactFlash Card Industrial Application
9.5.9 Status Register
This register contains the adapter status. The contents of this register are updated to reflect the current
state of the adapter and the progress of any command being executed by the adapter. When the BSY bit is
equal to zero, the other bits in this register are valid. When the BSY bit is equal to one, the other bits in this
register are not valid. When the register is read, the interrupt (#IREQ pin) is cleared.
bit-7
BSY
ERR
IDX
CORR
DRQ
DSC
DWF
DRDY
BSY
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
DRDY DWF
DSC
DRQ
CORR
0
ERR
When set, indicates that an error has occurred during the previous
command execution. The bits in the Error Register indicate the
cause.
Index is not used – always set to Zero.
Indicates that a data error was corrected; transfer is not
terminated.
Data Request. When set, indicates that the adapter is ready to
transfer a word or byte of data between the host and the adapter.
Drive Seek Complete. When set, indicates that the requested
sector was found.
Drive Write Fault status. When set, indicates that an error has
occurred during write.
Indicates whether the adapter is capable of performing drive
operations (commands). This bit is cleared at power up and
remains cleared until the drive is ready to accept a command. On
error, DRDY changes only after the host reads the Status register.
This signal is set during the time the adapter accesses the
command buffer or the registers. During this time the host is
locked out from accessing the command register and buffer. As
long as this bit is set no bits in the register are valid.
9.5.10 Alternate Status Register
The Alternate Status Register contains command block status information (see Status register). Unlike the
Status register, reading this register does not acknowledge or clear an interrupt.
bit-7
BSY
bit-6
DRDY
TCADO-SCF-000018.4
bit-5
DWF
bit-4
DSC
bit-3
DRQ
62/139
bit-2
CORR
bit-1
0
bit-0
ERR
0605V4
S-CN CompactFlash Card Industrial Application
9.5.11 Device Control Register
The Device Control Register is used to control the drive interrupt request and issue an ATA soft reset to the
drive.
bit-7
--#IEN
SRST
bit-6 bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
------1
SRST
#IEN 0
INTERRUPT ENABLE: When set (0), it enables interrupts to
the host (using the #IREQ tri-state pin). When inactive (1) or
drive is not selected, it disables all pending interrupts (#IREQ in
high-Z). This bit is ignored in Memory mode.
SOFT RESET: When set, forces the ATA to perform an AT disk
control soft reset operation.
9.5.12 Drive Address Register
This register reflects the drive and its heads. This register is provides for compatibility with the AT disk
interface. It’s recommended that this register is not mapped into this host’s I/O space because of potential
conflicts on bit7.
bit-7
bit-6
High-Z #WTG
#DS0
#DS1
#HS0 - #HS3
#WTG
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
#HS3
#HS2
#HS1
#HS0
#DS1
#DS0
When set (0), it indicates that drive 0 is active and selected.
When set (0), it indicates that drive 1 is active and selected.
Negation of the head number in the Drive/Head Register.
When set (0), it indicates that a write operation is in progress,
otherwise it is inactive (1) - not supported.
Note: Addressing Mode Descriptions - The adapter, on a command by command basis, can operate in
either CHS or LBA addressing modes. Identify Drive Information tells the host whether the drive supports
LBA mode. The host selects LBA mode via the Drive/Head Register. Sector number, Cylinder Low,
Cylinder High, and Drive/Head Register bits HS3=0 contain the zero-based LBA. The drive's sectors are
linearly mapped with: LBA = 0 => Cylinder 0, head 0, sector 1. Regardless of the translation mode, a sector
LBA address does not change. LBA = (Cylinder * no of heads + heads) * (sectors/track) + (Sector - 1).
TCADO-SCF-000018.4
63/139
0605V4
S-CN CompactFlash Card Industrial Application
10. ATA Commands
10.1 Check Power Mode - 98H or E5H
This command checks the current power mode of the adapter. When this command is issued and the
adapter is in standby mode, or is being set to standby mode, or during a recovery from standby mode is
attempted, adapter sets the BSY bit in the Status register and sets the Sector Count Register to “00H”. Then
the BSY bit in the Status register is cleared. When the adapter is in the Idle mode, it sets the BSY bit in the
Status register and sets “FFH” in the Sector Count Register. Then the BSY bit in the Status register is
cleared. An interrupt is issued after the BSY bit is cleared.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Command
7
6
N/A
N/A
N/A
N/A
N/A
98H or E5H
5
4
3
2
1
0
OUTPUTS
Register
Status
Sector Count
Error
TCADO-SCF-000018.4
7
6
5
4
3
BSY
DRDY DWF DSC
DRQ
V
V
V
V
V
Power Mode Code.(00H or 80H or FFH)
BBK
UNC
MC
IDNF MCR
64/139
2
CORR
1
IDX
0
ERR
V
ABRT
V
TK0NF
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.2 Execute Drive Diagnostic - 90H
This command performs self-diagnostics on various internal components of the adapter. Results of the test
are reported in the Error Register. Note that the bit definitions for the Error Register do not apply with this
command. Instead, the value in the Error Register is a diagnostic code, defined in the table below.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
DEV
90H
OUTPUTS: The diagnostic code written into the Error Register is an 8-bit code as shown in the table
below.
Register
Status
Error
Code
01H
02H
03H
04H
05H
TCADO-SCF-000018.4
7
6
5
4
BSY
DRDY DWF DSC
V
V
V
Diagnostic code, see table below
3
DRQ
2
CORR
1
IDX
0
ERR
V
Description
No error detected
Format Media error
Sector buffer error
ECC logic error
Controlling microprocessor error
65/139
0605V4
S-CN CompactFlash Card Industrial Application
10.3 Erase Sector(s) - C0H
This command is processed as a NOP command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
[LBA mode only] The number of sectors to be formatted on the track, must be
set to FFH
[LBA mode only] LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
C0H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
V
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
V
66/139
3
DRQ
2
CORR
1
IDX
MCR
ABRT
V
TK0NF
0
ERR
V
AMNF
V
0605V4
S-CN CompactFlash Card Industrial Application
10.4 Format Track - 50H
This command is processed as a NOP command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
[LBA mode only] The number of sectors to be formatted on the track. Must be
set to FFH
[LBA mode only] LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
50H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
V
67/139
3
DRQ
2
CORR
1
IDX
MCR
ABRT
V
TK0NF
0
ERR
V
AMNF
V
0605V4
S-CN CompactFlash Card Industrial Application
10.5 Identify Drive – ECH
The Identify Drive command enables the host to receive parameter information from the adapter. When the
command is issued, the adapter sets the BSY bit, prepares to transfer the 256 words of adapter identification
data to the host, sets the DRQ bit, clears the BSY bit, and generates an interrupt. The host can then
transfer the data by reading the Data register. All reserved bits or words are all zero. See following table
for the identify drive information for this adapter
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
DEV
ECH
OUTPUTS
Register
Status
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
Error
TCADO-SCF-000018.4
68/139
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.6 Idle - 97H or E3H
Although this command is supported for backward compatibility, it has no actual function. The adapter will
always return a ‘good’ status at the completion of this command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
N/A
Time-out Parameter. This parameter is ignored by the adapter
N/A
N/A
N/A
DEV
97H or E3H
1
0
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
69/139
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.7 Idle Immediate - 95H or E1H
Although this command is supported for backward compatibility, it has no actual function. The adapter will
always return a ‘good’ status at the completion of this command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
DEV
95H or E1H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
70/139
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.8 Initialize Drive Parameters - 91H
Initialize Drive Parameters allows the host to alter the number of sectors per track and the number of heads
per cylinder. This command does not check the validity of counts of sectors and heads. If an invalid value is
set, an error will be reported when another command attempts an invalid access.
The Sector Count Register specifies the number of logical sectors per logical track, and the Device/Head
register specifies the maximum head number.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
N/A
Number of sectors
N/A
N/A
N/A
5
4
3
2
1
DEV
Max Head (no. of head = 1)
0
91H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
MC
4
DSC
V
IDNF
71/139
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
TK0NF
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.9 Read Buffer - E4H
The Read Buffer command enables the host to read the current contents of the adapter’s sector buffer. This
command has the same protocol as the Read Sector(s) command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
LBA
4
3
2
1
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
DEV
E4H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
72/139
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.10 Read Long Sector(s) - 22H or 23H
Read Long (w/ and w/o retry) is similar to the Read Sectors command, except that the content of the Sector
Count Register is ignored and only one sector is read. The 512 data bytes and 4 ECC bytes are read into the
buffer (with no ECC correction) and then transferred to the host.
The Cylinder Low, Cylinder High, Device/Head and Sector Number specify the starting sector address to
be read. The Sector Count Register shouldn’t specify a value other than 1.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
The number of sectors/logical blocks to transfer. This should be set to 01 for
compatibility
Sector[7:0] or LBA[7:0] of the sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the
sector/LBA to transfer
22H (retries enabled) or 23H (retries disabled)
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY
DRDY DWF DSC
DRQ
CORR
IDX ERR
V
V
V
V
V
V
00 if the command proceed without error, else the number of untransfered
sectors.
Sector[7:0] or LBA[7:0] of the last sector read
Cylinder[7:0] or LBA[15:8] of the last sector read
Cylinder[15:8] or LBA[23:16] of the last sector read
BBK
UNC
MC
IDNF
MCR ABRT TK0NF AMNF
V
V
V
V
73/139
0605V4
S-CN CompactFlash Card Industrial Application
10.11 Read Multiple - C4H
This command functions like the Read Sector(s) command, but instead of issuing interrupts for each sector,
interrupts are issued when a block containing the counts of sectors, defined by the Set Multiple command
is, transferred. Also, the DRQ required for the transfer only has to be set at the start of the data block and
does not affect other sectors. When the Read Multiple command is issued, the requested sectors (not the
block counts or the sector counts in a block) are written into the Sector Count Register. Errors occurring
during command execution are reported at the start of a block transfer or at the start of transfer of part of a
block. However, the transfer continues even if DRQ is set and the data is corrupted. After the data transfer,
the content of the task file with the block data containing the sectors where the error occurred is not defined.
To obtain valid error information the host has to request a re-transmission. The next block or part of a block
is transferred only if the error is correctable. For all other errors the command is aborted after transferring a
block containing an error. The Read Multiple command is supported for backward compatibility. If R/W
Multiple commands have been enabled by a previous valid Set Multiple command, the Read Multiple
command is identical to the Read Sectors operation except that several sectors are transferred as a block to
the Host without the intervening Host handshaking. The block count stands for the number of sectors to be
transferred as a block. It is established using the Set Multiple command. Although the Set Multiple, and
R/W Multiple commands are supported, the only valid block count is one.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
N/A
The number of sectors/logical blocks to transfer
Sector[7:0] or LBA[7:0] of the sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the sector/LBA to transfer
LBA
DEV
Head number or LBA
C4H
0
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY
DRDY DWF
DSC
DRQ
CORR
IDX
ERR
V
V
V
V
V
V
V
The first sector where the first unrecoverable error occurred
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
H[3:0] or LBA[27:24] last good sector transferred
LBA
DEV
BBK
UNC
MC
IDNF
MCR
ABRT
TK0NF AMNF
V
V
V
V
V
V
V
V
74/139
0605V4
S-CN CompactFlash Card Industrial Application
10.12 Read Sectors(s) – 20H or 21H
The Cylinder Low, Cylinder High, Device/Head and Sector Number or LBA registers specify the starting
sector address to be read. The Sector Count Register specifies the number of sectors to be transferred.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
N/A
The number of sectors/logical blocks to transfer
Sector[7:0] or LBA[7:0] of the sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the
sector/LBA to transfer
20H (retry enabled) or 21H (retries disabled)
0
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY
DRDY DWF DSC DRQ
CORR IDX
ERR
V
V
V
V
V
V
V
The first sector where the first unrecoverable error occurred
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
LBA
DEV H[3:0] or LBA[27:24] last good sector
transferred
BBK UNC
MC
IDNF MCR
ABRT TK0NF AMNF
V
V
V
V
V
V
V
75/139
0605V4
S-CN CompactFlash Card Industrial Application
10.13 Read Verify Sector(s) – 40H or 41H
The Read Verify Sectors command verifies one or more sectors on the card by transferring data from the
Flash media to the data buffer in the card and verifying that the ECC is correct. It is performed identically to
the Read Sectors command, except that DRQ is not asserted, and no data is transferred to the host. If an
uncorrectable error occurs, the Read Verify command will be terminated at the failing sector. The task file
registers contain the CHS, or LBA of the sector in which the error occurred.
The Cylinder Low, Cylinder High, Device/Head and Sector Number specify the starting sector address to
be verified. The Sector Count Register specifies the number of sectors to be verified.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
N/A
The number of sectors/logical blocks to verify
Sector[7:0] or LBA[7:0] of the first sector/LBA to verify
Cylinder[7:0] or LBA[15:8] of the sector/LBA to verify
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to verify
LBA
DEV
H[3:0] or LBA[27:24] of the
sector/LBA to verify
40H (retries enabled) or 41H (retries disabled)
0
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
BSY
DRDY DWF DSC
DRQ
CORR IDX
V
V
V
V
V
V
The first sector where the first unrecoverable error occurred
Sector[7:0] or LBA[7:0] of the sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
LBA
DEV
H[3:0] or LBA[27:24] of the
sector/LBA to transfer
BBK
UNC
MC
IDNF MCR ABRT TK0NF
V
V
V
V
V
V
76/139
0
ERR
V
AMNF
V
0605V4
S-CN CompactFlash Card Industrial Application
10.14 Recalibrate - 1XH
The adapter performs only the interface timing and register operations. When this command is issued, the
adapter sets BSY and waits for an appropriate length of time after which it clears BSY and issues an
interrupt. When this command ends normally, the adapter is initialized.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
3
DRQ
2
CORR
1
IDX
MCR
ABRT
V
TK0NF
0
DEV
1XH
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
77/139
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.15 Request Sense - 03H
This command requests extended error information for the previous command. The table below defines the
valid extended error codes. Those codes are placed in the Error Register.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
DEV
03H
OUTPUTS
The diagnostic code written into the Error Register is an 8-bit code as shown in the table below.
Register
Status
Error
7
6
5
BSY
DRDY DWF
V
V
Sense code, see table below
Code
00H
01H
03H
09H
20H
21H
2FH
35H, 36H
11H
18H
05H, 30H-34H, 37H, 3EH
10H, 14H
3AH
1FH
0CH, 38H, 3BH, 3CH, 3FH
TCADO-SCF-000018.4
4
DSC
V
3
DRQ
2
CORR
1
IDX
0
ERR
V
Description
No error detected
Self test OK (No error)
Write/Erase failed
Miscellaneous Error - N/A
Invalid Command
Invalid Address (requested Head or Sector invalid)
Address Overflow (address too large)
Supply or generate Voltage Out of Tolerance
Uncorrectable ECC Error
Corrected ECC Error - N/A
Self Test Diagnostic Failed
ID Not Found - N/A
Spare Sectors Exhausted
Data Transfer Error / Aborted Command
Corrupted Media Format - N/A
78/139
0605V4
S-CN CompactFlash Card Industrial Application
10.16 Seek - 7XH
This command seeks and picks up the head to track specified in the Task File registers. Actually the adapter
performs only an interface timing and register information.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
N/A
(Valid in LBA mode only) LBA[7:0] of the track
Cylinder[7:0] or LBA[15:8] of the track
Cylinder[15:8] or LBA[23:16] of the track
LBA
DEV
H[3:0] or LBA[27:24] of the track
7XH
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
V
4
DSC
V
IDNF
V
79/139
3
DRQ
V
MCR
V
2
CORR
1
IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.17 Set Feature - EFH
This command is used by the host to establish or select from the specific features listed below.(after a power
up or a hardware reset) An ATA software reset does not set the features to default. The feature code is
set to 81H, this mode is the default mode.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
Feature number according to the table below
Configuration required
N/A
N/A
N/A
DEV
EFH
2
1
0
2
CORR
1
IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
Feature Codes
Code
01H
55H
66H
81H
BBH
CCH
Description
Enable 8-bit data transfers
Disable Read Look Ahead
Disable reverting to power on defaults
Disable 8-bit data transfers
4 bytes of ECC apply on read long/write long commands
Enable reverting to power on defaults
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
80/139
3
DRQ
V
MCR
0605V4
S-CN CompactFlash Card Industrial Application
10.18 Set Multiple Mode - C6H
The Set Multiple command allows the adapter to perform Read Multiple and Write Multiple operations. It
also sets the block count (counts of sectors making up a block) for these commands. The sector count per
block is placed is the Sector Count Register. The adapter supports only blocks with one sector.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
N/A
Sector Count per Block( = 1)
N/A
N/A
N/A
DEV
C6H
3
2
1
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
81/139
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.19 Set Sleep Mode - 99H or E6H
This is the only command that allows the host to set the adapter into Sleep mode. When the adapter is set to
sleep mode, the adapter clears the BSY line and issues an interrupt. The adapter enters sleep mode and the
only method to make the adapter active again (back to normal operation) is by performing a hardware reset
or software reset.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
DEV
99H/E6H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
82/139
3
DRQ
V
MCR
2
1
CORR IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.20 Standby - 96H or E2H
This command is sets the adapter in Standby mode. If the Sector Count Register is a value other than 0H,
an Auto Power Down is enabled and when the adapter returns to the idle mode, the timer starts a
countdown. The time is set in the Sector Count Register.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
N/A
Time period value
N/A
N/A
N/A
5
4
3
2
1
0
DEV
96H or E2H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
83/139
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.21 Standby Immediate 94H or E0H
This command sets the adapter into standby mode.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
3
DRQ
V
MCR
2
CORR
1
IDX
ABRT
V
TK0NF
0
DEV
94H or E0H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
84/139
0
ERR
V
AMNF
0605V4
S-CN CompactFlash Card Industrial Application
10.22 Translate Sector - 87H
This command allows the host a method of determining the exact number of times a sector was used
(erased). The controller responds with the 512-byte buffer of information that includes the Hot Count, if
available, for the sector. This command is not supported in this adapter and will always return the Hot
Count as “00”.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
Sector Count
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
87H
OUTPUTS
The diagnostic code written into the Error Register is an 8-bit code as shown in the table below.
Register
Status
Error
Address
00H - 01H
02H
03H
04H - 06H
07H - 12H
13H
14H - 17H
18H - 1AH
1BH - 1FFH
TCADO-SCF-000018.4
7
BSY
V
BBK
V
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
V
3
DRQ
2
CORR
1
IDX
MCR
ABRT
V
TK0NF
0
ERR
V
AMNF
Information
Cylinder MSB (00H), Cylinder LSB (01H)
Head
Sector
LBA MSB (04H) - LSB (06H)
Reserved
Erased Flag (FFH) = Erased; (00H) = Not Erased
Reserved
Hot Count MSB (18H) - LSB (1AH)
Reserved
85/139
0605V4
S-CN CompactFlash Card Industrial Application
10.23 Wear Level - F5H
This command is effectively a NOP command and only implemented for backward compatibility. The
Sector Count Register will always return the value “00H”, indicating that wear leveling is not needed.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
DEV
F5H
OUTPUTS
Register
Status
Sector Count
Error
TCADO-SCF-000018.4
7
6
BSY DRDY
V
V
Always “00H”
BBK UNC
V
V
5
DWF
V
4
DSC
V
3
DRQ
V
2
CORR
1
IDX
0
ERR
V
MC
V
IDNF
V
MCR
V
ABRT
V
TK0NF
AMNF
V
86/139
0605V4
S-CN CompactFlash Card Industrial Application
10.24 Write Buffer - E8H
This command enables the host to rewrite the contents of the adapter data buffer in the adapter with the
desired data sting. This data buffer can be accessed by and read by the Read Buffer Command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
2
CORR
1
IDX
ABRT
V
TK0NF
0
ERR
V
AMNF
DEV
E8H
OUTPUTS
Register
Status
Error
TCADO-SCF-000018.4
7
BSY
V
BBK
6
DRDY
V
UNC
5
DWF
V
MC
4
DSC
V
IDNF
87/139
3
DRQ
V
MCR
0605V4
S-CN CompactFlash Card Industrial Application
10.25 Write Long Sector(s) 32H or 33H
This command operates in the same way as the Write Sector command except that it writes data and ECC
bytes for long commands directly from the sector buffer. ECC bytes for long commands are byte writes that
consist of a 4-byte fixed length data. This command can write only one sector at a time.
INPUT
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
“01h”
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
32H or 33H
OUTPUTS
TCADO-SCF-000018.4
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TCADO-SCF-000018.4
89/139
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TCADO-SCF-000018.4
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Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
BSY DRDY DWF DSC DRQ
CORR
IDX
ERR
V
V
V
V
V
V
Bit-0 if the command proceeded successfully, other – untransferred sectors
count
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
BBK UNC
MC
IDNF MCR
ABRT
TK0NF AMNF
V
V
V
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10.26 Write Multiple - C5H
This command functions in the same way as the Write Sector command. When this command is issued, the
adapter sets the BSY within 400nsec. Interrupts are not issued for every sector but after one block
consisting of the counts of sectors defined by the Set Multiple command is transferred. The DRQ required
for the transfer only has to be set at the beginning of the block and does not affect other sectors.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
Sector Count
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LB[27:24] of the starting
sector/LBA
C5H
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY DRDY DWF DSC
DRQ
CORR IDX
ERR
V
V
V
V
V
V
Bit-0 if the command proceeded successfully, other – untransferred sectors count
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
BBK UNC
MC
IDNF MCR
ABRT
TK0NF AMNF
V
V
V
V
V
V
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10.27 Write Multiple without Erase – CDH
This command is similar to the Write Multiple command with the exception that an implied erase before
using this command. Please note that before using this command it is required to erase the respective
sectors using the Erase Sector command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
Sector Count
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LB[27:24] of the starting
sector/LBA
CDH
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY DRDY DWF DSC
DRQ
CORR IDX
ERR
V
V
V
V
V
V
Bit-0 if the command proceeded successfully, other – untransferred sectors count
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
BBK UNC
MC
IDNF MCR
ABRT
TK0NF AMNF
V
V
V
V
V
V
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10.28 Write Sector(s) - 30H or 31H
This command allows the host to write the specified number (1 to 256) of sectors in the Sector Count
Register. A sector count of 0 indicates a write request of 256 sectors. The write operation starts from the
sector specified in the Sector Number register. The command ends execution by placing the cylinder, head
and sector number of the last written sector in the Task File registers.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
Sector Count
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
30H or 31H
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY DRDY DWF DSC
DRQ
CORR IDX
ERR
V
V
V
V
V
V
Bit-0 if the command proceeded successfully, other – untransferred sectors count
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
BBK UNC
MC
IDNF MCR
ABRT
TK0NF AMNF
V
V
V
V
V
V
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10.29 Write Sector(s) without Erase - 38H
This command is similar to the Write Sector command with the exception that an implied erase before
using this command. Please note that before using this command it is required to erase the respective
sectors using the Erase Sector command.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
Sector Count
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
38H
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY DRDY DWF DSC
DRQ
CORR IDX
ERR
V
V
V
V
V
V
Bit-0 if the command proceeded successfully, other – untransferred sectors count
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
BBK UNC
MC
IDNF MCR
ABRT
TK0NF AMNF
V
V
V
V
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10.30 Write Verity - 3CH
This command is similar to the Write Sector command with the exception that each sector is verified
immediately after writing.
INPUTS
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7
6
5
4
3
2
1
0
N/A
Sector Count
Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
LBA
DEV
H[3:0] or LBA[27:24] of the starting
sector/LBA
3CH
OUTPUTS
Register
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Error
TCADO-SCF-000018.4
7
6
5
4
3
2
1
0
BSY DRDY DWF DSC
DRQ
CORR IDX
ERR
V
V
V
V
V
V
Bit-0 if the command proceeded successfully, other – untransferred sectors count
Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder[15:8] or LBA[23:16] of the last good sector transferred
BBK UNC
MC
IDNF MCR
ABRT
TK0NF AMNF
V
V
V
V
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11. Error Posting
Command
BBK
Check Power Mode
Execute Drive Diagnostic
Erase Sector(s)
Format Track
Identify Drive
Idle
Idle immediate
Initialize Drive Parameter
Read Buffer
Read Multiple
Read Long Sector
Read Sector(s)
Read Verify Sectors
Recalibrate
Request Sense
Security Disable Password
Security Erase Prepare
Security Erase Unit
Security Freeze Lock
Security Set Password
Security Unlock
Seek
Set Features
Set Multiple Mode
Set Sleep Mode
Stand By
Stand By Immediate
Translate Sector
Wear Level
Write Buffer
Write Long Sector
Write Multiple
Write Multiple w/o Erase
TCADO-SCF-000018.4
9
9
9
9
9
9
9
9
9
9
Error Register
Status Register
UNC IDNF ABRT AMNF DRDY DWF DSC CORR ERR
9
9
9 9
9
9
9
9
9
9
9
9
9 9
9
9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9
9
9
9 9
9
9
9
9
9
9
9 9
9
9
9
9
9
9
9 9
9
9
9
9
9
9
9 9
9
9
9
9
9
9
9
9 9
9
9
9
9
9 9
9
9
9
9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9 9
9
9
9
9
9
9 9
9
9
9
9
9
9
9 9
9
9
9
9 9
9
9
9
9
9
9 9
9
9
9
9
9
9 9
9
9
9
9
9
9 9
9
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Write Sector(s)
Write Sector w/o Erase
Write Verify
Invalid command Code
TCADO-SCF-000018.4
9
9
9
9
9
9
98/139
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
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S-CN CompactFlash Card Industrial Application
12. Identify Drive Information
Word
0
1
2
3
4
5
6
7-8
9
10-19
20
21
22
23-26
27-46
47
48
49
Data
848AH
Note 1
0000h
Note 1
0000H
XXXXH
Note 1
XXXXH
XXXXH
XXXXH
0002H
0002H
0004H
XXXXH
XXXXH
0001H
0000H
2F00H
50
51
52
53
0000H
0200H
0000H
0003H
TCADO-SCF-000018.4
Description
General configuration bit-significant information
Number of Cylinders
Reserved
Number of Heads
Obsolete
Obsolete
Number of sectors per track
Number of sectors per card (Word 7= MSW, Word 8= LSW )
Obsolete
20 ASCII char serial number.
Obsolete
Obsolete
ECC bytes passed on Read/Write Long Commands
Firmware revision in ASCII chars.
Model Number (Vendor Unique)
Maximum Block Count=1 for Read/Write Multiple command
Reserved
Capabilities: LBA supported (bit 9).
Capabilities: LBA supported (bit 9).
15 0= interleave DMA not supported
14 0=command queuing not supported
13 1=overlap operation supported
12 0=ATA software reset required (Obsolete)
11 0=IORDY not supported
10 0=IORDY maybe enable
9 0=LBA not supported
8 0=DMA not Supported
7-0 Vendor specification
Reserved
PIO data transfer cycle timing mode
Obsolete
Translation Parameters Vaild (bit0:Word54 to 58 are valid,
bit1:Word 64 to 70 are valid)
15-3 Reserved
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Word
Data
54
55
56
57
58
59
Note 1
Note1
Note 1
Note 1
Note1
0100H
60
61
62
63
Note 1
Note 1
0000H
0001H
64
0003H
TCADO-SCF-000018.4
Description
2
1= the field reported in word 88 are valid
0= the field reported in word 88 are not valid
1
1= the field reported in word 64-70 are valid
0= the field reported in word 64-70 are not valid
0
1= the field reported in word 54-58 are valid
0= the field reported in word 54-58 are not valid
Number of Current Cylinders
Number of Current Heads
Number of Current Sectors Per Track
LSW of the Current Capacity in Sectors
MSW of the Current Capacity in Sectors
Multiple sector setting
If bit 8 is set to one, bits 7-0 reflect the number of sector currently
set to transfer on a READ/WRITE MULTIPLE command.
This filed may default to the preferred value for the device.
Command Code: C6h
LSW of the total number of user addressable LBA’s
MSW of the total number of user addressable LBA’s
Reserved
15-11 Reserved
10 1=Multiword DMA mode 2 is selected
0=Multiword DMA mode 2 is not selected
9 1= Multiword DMA mode 1 is selected
0=Multiword DMA mode 1 is not selected
8 1= Multiword DMA mode 0 is selected
0=Multiword DMA mode 0 is not selected
7-3 Reserved
2 0= Multiword DMA mode 2 and below are not supported
1 0= Multiword DMA mode 1 and below are not supported
0 1= Multiword DMA mode 0 is supported Multiword
DMA mode selected.
Advanced PIO Modes supported (bit0: PIO-3,
bit1:PIO4,supported)
15-8 Reserved
7-0
Supported
Bits 7 through 0 of word 64 of the Identify Device parameter
information is defined as the PIO data and register transfer
supported field. If this field is supported, bit 1 of word 53 shall
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Word
65
Data
01E0H (DMA
2)
0000H (PIO 4)
66
01E0H
0000H (PIO 4)
67
0078H
68
0078H
69-79
80-81
82
83
84
85
86
87
88
0000H
0000H ...
0000H
0000H
0000H
0000H
0000H
0000H
0700H
TCADO-SCF-000018.4
Description
be set to one.
Of these bits, bits 7 through 2 are Revered for future PIO
modes. Bit 0, if set to one, indicated that the device supports
PIO mode 3. All device except CFA and PCMCIA device shall
support PIO mode 3 and shall set bit 0 to one. Bit 1, if set to
one, indicated that the device support PIO mode 4.
Minimum Multiword DMA transfer cycle time per word
15-0 Cycle time in nanoseconds
If this field is supported, bit 1 of word 53 shall be set to one.
Any device that supports Multiword DMA mode 1 or above
shall support this field, and the value in word 65 shall not be
less than the minimum cycle time for the fastest DMA mode
supported by the device.
If bit 1 of word 53 is set to one because a device supports a
field in words 64-70 other than this filed and the device does
not support this filed, the device shall return a value of zero in
this field.
Manufacturer’s recommended Multiword DMA transfer cycle
time
15-0 Cycle time in nanoseconds
If this field is supported, bit 1 of word 53 shall be set to one,
Any device that supports Multiword DMA mode 1 or above
shall support this field, and the value in word 66 shall not be
less than the value in word 65.
Minimum PIO transfer cycle time without flow control
15-0 Cycle time in nanoseconds
Minimum PIO transfer cycle time with IORDY flow control
15-0 Cycle time in nanoseconds
Reserved (for feature command overlap and queuing)
Reserved for CFA
Features/Command sets supported
Feature/Command sets supported
Features/Command sets supported
Features/Command sets supported
Feature/Command sets supported
Features/Command sets supported
15-14 Reserved
13 1= Ultra DMA mode 5 is selected
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Word
89
90
91
92 - 127
128
129 - 159
160
161
162
163 - 255
Note1:
Description
0=Ultra DMA mode 5 is not selected
12 1= Ultra DMA mode 4 is selected
0=Ultra DMA mode 4 is not selected
11 1= Ultra DMA mode 3 is selected
0=Ultra DMA mode 3 is not selected
10 1= Ultra DMA mode 2 is selected
0=Ultra DMA mode 2 is not selected
9 1= Ultra DMA mode 1 is selected
0=Ultra DMA mode 1 is not selected
8 1= Ultra DMA mode 0 is selected
0=Ultra DMA mode 0 is not selected
7-6 Reserved
5 0= Ultra DMA mode 5 and below are not supported
4 1= Ultra DMA mode 4 and below are supported
3 1= Ultra DMA mode 3 and below are supported
2 1= Ultra DMA mode 2 and below are supported
1 1= Ultra DMA mode 1 and below are supported
0 1= Ultra DMA mode 0 is supported
0000H
Time required for Security erase unit completion
0000H
Time required for Enhanced security erase unit completion
XXXXH
Current Advanced power management value
0000H
Reserved
0000H
Security status
0000H
Vendor unique bytes
0000H
Power requirement description
0000H
Reserved
0000H
Key management schemes supported
0000H
Total 166 Bytes Reserved
Variable by capacity
TCADO-SCF-000018.4
Data
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13. ATA Protocol Overview
Command classes are grouped according to protocols described for command execution. For all commands,
the host must first check for BYS=0 before proceeding further. For most commands, the host should not
proceed until DRDY=1.
13.1 PIO Data In Commands
Execution includes one more 512 bytes data-sector drive-to-host transfer. If the drive presents error status, it
prepares to transfer data at the host's discretion. The host writes parameters to the Feature, Sector Count,
Sector Number, Cylinder, and Drive/Head register. The host writes the Command Register's command
code. The drive sets BSY and prepares for data transfer when a data sector is available; the drive sets
DRQ, clears BSY, and asserts interrupt. At interrupt, the host reads the Status register, the drive negates
interrupt, and the host reads one data-sector from Data Register. The drive clears DRQ. If another sector
is required, the drive sets BSY and repeats the data transfer from 4.
13.2 PIO Data Out Commands
Execution includes one or more 512 bytes host-to-drive data-sector transfers. The host writes parameters to
the Features, Sector Count, Sector Number, Cylinder, and Drive/Head Registers. The host writes the
Command register's command code. The drive sets DRQ when it can accept the first sector of data
The host writes one sector of data to the Data register. The Drive clears DRQ and sets BSY. At sector
processing complete, the drive clears BSY and asserts interrupt. If another sector transfer is required, the
drive also sets DRQ. The host reads the Status register after detecting interrupt. The drive negates the
interrupt if another sector transfer is required, the sequence repeats from 4.
13.3 Non Data Commands
Command execution involves no data transfer. The host writes parameters to the Features, Sector Count,
Sector Number, Cylinder, and Drive/Head registers. The host writes the Command register's command
code. The Drive sets BSY. When the drive completes sector processing, it clears BSY and asserts
interrupt. The host reads the Status register after detecting interrupts the drive negates the interrupt.
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14. Ultra DMA data-in commands
14.1. Initiating an Ultra DMA data-in burst
The following steps shall occur in the order they are listed unless otherwise specified.
a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst when DMACK- is negated.
Afterassertion of DMARQ the device shall not negate DMARQ until after the first negation of
DSTROBE.
c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall negate HDMARDY-.
e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1,
and DA0 negated until after negating DMACK- at the end of the burst.
f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep
DMACK- asserted until the end of an Ultra DMA burst.
g) The host shall release DD(15:0) within tAZ after asserting DMACK-.
h) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has
driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the
end of an Ultra DMA burst.
i) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-. After
negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after
receiving the first negation of DSTROBE from the device (i.e., after the first data word has been received).
j) The device shall drive DD(15:0) no sooner than tZAD after the host has asserted DMACK-, negated STOP,
and asserted HDMARDY-.
k) The device shall drive the first word of the data transfer onto DD(15:0). This step may occur when the
device first drives DD(15:0) in step (j).
l) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated
STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than tDVS after driving
the first word of data onto DD(15:0).
14.2. The data-in transfer
The following steps shall occur in the order they are listed unless otherwise specified.
a) The device shall drive a data word onto DD(15:0).
b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the
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state of DD(15:0). The device shall generate a DSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more
frequently than t2cyc for the selected Ultra DMA mode.
c) The device shall not change the state of DD(15:0) until at least tDVH after generating a DSTROBE edge to
latch the data.
d) The device shall repeat steps (a), (b), and (c) until the Ultra DMA burst is paused or terminated by the
device or host.
14.3. Pausing an Ultra DMA data-in burst
The following steps shall occur in the order they are listed unless otherwise specified.
14.3.1. Device pausing an Ultra DMA data-in burst
a) The device shall not paused an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by not generating additional DSTROBE edges. If the host is
ready to terminate the Ultra DMA burst.
c) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.
14.3.2. Host pausing an Ultra DMA data-in burst
a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by negating HDMARDY-.
c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the host negates HDMARDY- within tSR after the
device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data
words; or, if the host negates HDMARDY- greater than tSR after the device has generated a DSTROBE edge,
then the host shall be prepared to receive zero, one or two additional data words. While operating in Ultra
DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words after
negating HDMARDY-. The additional data words are a result of cable round trip delay and tRFS timing for the
device.
e) The host shall resume an Ultra DMA burst by asserting HDMARDY-.
14.3.3. Terminating an Ultra DMA data-in burst
14.3.3.1. Device terminating an Ultra DMA data-in burst
Burst termination is completed when the termination protocol has been executed and DMACK- negated. The
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device shall terminate an Ultra DMA burst before command completion.
The following steps shall occur in the order they are listed unless otherwise specified.
z The device shall initiate termination of an Ultra DMA burst by not generating additional DSTROBE edges.
z The device shall negate DMARQ no sooner than tSS after generating the last DSTROBE edge. The device
shall not assert DMARQ again until after DMACK- has been negated.
z The device shall release DD(15:0) no later than tAZ after negating DMARQ.
z The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate STOP
again until after the Ultra DMA burst is terminated.
z The host shall negate HDMARDY- within tLI after the device has negated DMARQ. The host shall continue
to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (d) and (e) may occur at the same time.
z The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host
may first drive DD(15:0) with the result of the host CRC calculation (see 9.15);
z If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data
shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall
remain asserted until the Ultra DMA burst is terminated.
z If the host has not placed the result of the host CRC calculation on DD(15:0) since first driving DD(15:0)
during (f), the host shall place the result of the host CRC calculation on DD(15:0) (see 9.15).
z The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated
DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places
the result of the host CRC calculation on DD(15:0).
z The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
z The device shall compare the CRC data received from the host with the results of the device CRC calculation.
If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the
command the device shall report the first error that occurred (see 9.15).
z The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.
z The host shall not negate STOP nor assert HDMARDY- until at least tACK after negating DMACK-.
z The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.
14.3.3.2. Host terminating an Ultra DMA data-in burst
The following steps shall occur in the order they are listed unless otherwise specified.
a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst
has been transferred.
b) b) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall
continue to negate HDMARDY- until the Ultra DMA burst is terminated.
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c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the host negates HDMARDY- within tSR after the
device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional
data words; or, if the host negates HDMARDY- greater than tSR after the device has generated a
DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three
additional data words after negating HDMARDY-. The additional data words are a result of cable round
trip delay and tRFS timing for the device.
e) The host shall assert STOP no sooner than tRP after negating HDMARDY-. The host shall not negate
STOP again until after the Ultra DMA burst is terminated.
f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No
data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) The device shall release DD(15:0) no later than tAZ after negating DMARQ.
i) The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the
host may first drive DD(15:0) with the result of the host CRC calculation .
j) If the host has not placed the result of the host CRC calculation on DD(15:0) since first driving DD(15:0)
during (9), the host shall place the result of the host CRC calculation on DD(15:0).
k) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated
DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the
host places the result of the host CRC calculation on DD(15:0).
l) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
m) The device shall compare the CRC data received from the host with the results of the device CRC
calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at
the end of the command, the device shall report the first error that occurred.
n) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.
o) The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the host has negated
DMACK-.
p) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.
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14.4. Ultra DMA data-out commands
14.4.1. Initiating an Ultra DMA data-out burst
The following steps shall occur in the order they are listed unless otherwise specified.
a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst when DMACK- is negated.
c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall assert HSTROBE.
e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1,
and DA0 negated until after negating DMACK- at the end of the burst.
f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall
keep DMACK- asserted until the end of an Ultra DMA burst.
g) The device may negate DDMARDY- tZIORDY after the host has asserted DMACK-. Once the device
has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated
DMACK- at the end of an Ultra DMA burst.
h) The host shall negate STOP within tENV after asserting DMACK-. The host shall not assert STOP until
after the first negation of HSTROBE.
i) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ
and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by
the host.
j) The host shall drive the first word of the data transfer onto DD(15:0). This step may occur any time
during Ultra DMA burst initiation.
k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device
has asserted DDMARDY-. The host shall negate HSTROBE no sooner than tDVS after the driving the
first word of data onto DD(15:0).
14.4.2. The data-out transfer
The following steps shall occur in the order they are listed unless otherwise specified.
a) The host shall drive a data word onto DD(15:0).
b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the
state of DD(15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
frequently than t2cyc for the selected Ultra DMA mode.
c) The host shall not change the state of DD(15:0) until at least tDVH after generating an HSTROBE edge to
latch the data.
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d) The host shall repeat steps (a), (b), and (c) until the Ultra DMA burst is paused or terminated by the device
or host.
14.4.3. Pausing an Ultra DMA data-out burst
The following steps shall occur in the order they are listed unless otherwise specified.
14.4.3.1 Host pausing an Ultra DMA data-out burst
a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge. If the host is ready to
terminate the Ultra DMA burst.
c) The host shall resume an Ultra DMA burst by generating an HSTROBE edge .
12.4.3.2. Device pausing an Ultra DMA data-out burst
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by negating DDMARDY-.
c) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the device negates DDMARDY- within tSR after
the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one
additional data words; or, if the device negates DDMARDY- greater than tSR after the host has generated an
HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words.
While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero, one, two or three
additional data words after negating DDMARDY-. The additional data words are a result of cable round
trip delay and tRFS timing for the host.
e) The device shall resume an Ultra DMA burst by asserting DDMARDY-.
14.4.4. Terminating an Ultra DMA data-out burst
14.4.4.1 Host terminating an Ultra DMA data-out burst
The following steps shall occur in the order they are listed unless otherwise specified.
a) The host shall initiate termination of an Ultra DMA burst by not generating additional HSTROBE edges.
b) The host shall assert STOP no sooner than tSS after the last generated an HSTROBE edge. The host
shall not negate STOP again until after the Ultra DMA burst is terminated.
c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
d) The device shall negate DDMARDY- within tLI after the host has negated STOP. The device shall not
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assert DDMARDY- again until after the Ultra DMA burst termination is complete.
e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
f) The host shall place the result of the host CRC calculation on DD(15:0)
g) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and DDMARDY-, and no sooner than tDVS after placing the result
of the host CRC calculation on DD(15:0).
h) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
i) The device shall compare the CRC data received from the host with the results of the device CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command, the device shall report the first error that occurred.
j) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-.
k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK-.
l) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.
14.4.4.2 Device terminating an Ultra DMA data-out burst
Burst termination is completed when the termination protocol has been executed and DMACK- negated. The
device shall terminate an Ultra DMA burst before command completion. The following steps shall occur in the
order they are listed unless otherwise specified.
a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA
burst has been transferred.
b) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.
c) The host shall stop generating an HSTROBE edges within tRFS of the device negating DDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the device negates DDMARDY- within tSR after the
host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one
additional data words; or, if the device negates DDMARDY- greater than tSR after the host has generated
an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words.
While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero, one, two or
three additional data words after negating DDMARDY-. The additional data words are a result of cable
round trip delay and tRFS timing for the host.
e) The device shall negate DMARQ no sooner than tRP after negating DDMARDY-. The device shall not
assert DMARQ again until after DMACK- is negated.
f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate
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STOP again until after the Ultra DMA burst is terminated.
g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) The host shall place the result of the host CRC calculation on DD(15:0).
i) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and DDMARDY-, and no sooner than t DVS after placing the
result of the host CRC calculation on DD(15:0).
j) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
k) The device shall compare the CRC data received from the host with the results of the device CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command, the device shall report the first error that occurred.
l) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-.
m) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.
n) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.
14.5. Ultra DMA CRC rules
The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra
DMA burst, and reporting any error that occurs at the end of a command.
1) Both the host and the device shall have a 16-bit CRC calculation function.
2) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.
3) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of
an Ultra DMA burst before any data is transferred.
4) For each STROBE transition used for data transfer, both the host and the device shall calculate a new
CRC value by applying the CRC polynomial to the current value of their individual CRC functions and
the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after
the Ultra DMA burst termination request has been acknowledged.
5) At the end of any Ultra DMA burst the host shall send the results of the host CRC calculation function to
the device on DD(15:0) with the negation of DMACK-.
6) The device shall then compare the CRC data from the host with the calculated value in its own CRC
calculation function. If the two values do not match, the device shall save the error. A subsequent Ultra
DMA burst for the same command that does not have a CRC error shall not clear an error saved from a
previous Ultra DMA burst in the same command. If a miscompare error occurs during one or more
Ultra DMA bursts for any one command, the device shall report the first error that occurred. If the
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device detects that a CRC error has occurred before data transfer for the command is complete, the device
may complete the transfer and report the error or abort the command and report the error.
7) For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands:
When a CRC error is detected, the error shall be reported by setting both ICRC and ABRT (bit 7 and bit 2
in the Error register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to
this error by re-issuing the command.
8) For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE
command): When a CRC error is detected during transmission of sense data the device shall complete
the command and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED
COMMAND). The device shall preserve the original sense data that was being returned when the CRC
error occurred. The device shall not report any additional sense data specific to the CRC error. The host
device driver may retry the REQUEST SENSE command or may consider this an unrecoverable error
and retry the command that caused the Check Condition.
9) For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device
shall complete the command with CHK set to one. The device shall report a Sense key of 04h
(HARDWARE ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall
report an ASC/ASCQ value of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host
drivers should retry the command that resulted in a HARDWARE ERROR.
10) A host may send extra data words on the last Ultra DMA burst of a data-out command. If a device
determines that all data has been transferred for a command, the device shall terminate the burst. A device
may have already received more data words than were required for the command. These extra words are
used by both the host and the device to calculate the CRC, but, on an Ultra DMA data-out burst, the extra
words shall be discarded by the device.
11) The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 46 describes the equations for
16- bit parallel generation of the resulting polynomial (based on a word boundary).
NOTE Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock
derived from the bus strobe. The combinational logic is then equivalent to shifting sixteen bits serially through
the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.
NOTE If excessive CRC errors are encountered while operating in an Ultra mode, the host should select a slower
Ultra mode. Caution: CRC errors are detected and reported only while operating in an Ultra mode.
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15. Security CF
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16.System Environmental Specifications
16.1 Temperature Test Flow
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16.2Altitude Test
Altitude
Altitude(relative to sea level)
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