FULL ADDER

---------------------------------------half_adder -------------------------------
library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port(
Ci : IN std_logic;
X,Y : IN std_logic;
S,Cout : OUT std_logic
);
end half_adder;
architecture arch_halfadder of half_adder is
begin
S <= X xor Y xor Ci;
Cout <= (X and Y) or (X and Ci) or (Y and Ci);
end arch_halfadder;
-------------------------------------full_adder----------------------------------------------
library IEEE; use IEEE.std_logic_1164.all; entity full_adder is
port(
Cin : IN std_logic;
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0); Res : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
end full_adder;
architecture arch_add4full of full_adder is
-- déclaration du composant add1full component half_adder is
port(
Ci : IN std_logic;
X,Y : IN std_logic;
S,Cout : OUT std_logic
);
end component half_adder;
signal Fil1,Fil2,Fil3:std_logic;
begin
-- placement des 4 aditionneurs complets
U0 : half_adder port map (Cin,A(0),B(0),Res(0),Fil1);
U1 : half_adder port map (Fil1,A(1),B(1),Res(1),Fil2);
U2 : half_adder port map(X=>A(2),Y=>B(2),S=>Res(2),
Cout=>Fil3,Ci=>Fil2);
U3 : half_adder port map (Fil3,A(3),B(3),Res(3),Cout);
end arch_add4full;