246 6. CURRENT FED TWO-INDUCTOR BOOST CONVERTER Parts of this chapter have been published in the Australian Journal of Electrical & Electronic Engineering in 2004 and in the Proceedings of AUPEC 2003, 2004 and 2005, APEC 2005 and PESC 2005. Chapter 2 has shown that MIC implementations with an unfolding stage are able to avoid the complex circuit design and the high switching losses associated with the PWM control technique in the dc-ac inversion stage. It has been shown in Chapter 3 that a buck conversion stage must be used as the current source for the two-inductor boost converter so that the rectified sinusoidal waveforms can be generated at the output and an unfolder can be employed in the dc-ac inversion stage. This chapter studies the current fed two-inductor boost converter in detail and provides the experimental results of a 100-W converter with both the hard-switched and the softswitched topologies. While this approach does result in a rather long power train, it is still possible to achieve adequate conversion efficiencies. One advantage is that the boost cell can operate at fixed duty ratio and be optimised better as the buck stage can perform most or all of the required voltage variations for the control. 6.1 Buck Conversion Stage It has been shown earlier in the thesis that under the voltage source input, a variable output voltage can be produced by varying the switching duty ratios in the hard- 247 switched two-inductor boost converter or by varying the switching frequency in the soft-switched two-inductor boost converter. However, the two-inductor boost converter is a boost derived converter and zero output voltage cannot be reached in either the hard-switched or the soft-switched forms. In order to generate the rectified sinusoidal waveforms at the output of the two-inductor boost converter, a buck conversion stage must be added. Therefore the converters in Figures 3.10 and 3.11 can be developed. Recently, multi-phase converter arrangements have been widely adopted as an efficient approach to parallel multiple converters to provide high current output [168]. Under multi-phase operation, the individual converter input and output currents with an equal phase shift, which is the quotient of 360º divided by the number of phases, are added together and the equivalent input and output current ripple frequencies will be multiplied by the number of the phases. The converter also has a smaller input or output current ripple magnitude as the current ripples in the individual phases cancel [169]. This eases the requirement on bulky input and output filter components such as inductors and capacitors. A two-phase buck converter will be employed as the current source for the two-inductor boost converter. In order to feed the output from the two-phase buck converter to the input of the two-inductor boost converter and make use of the two existing inductors in the boost converter, an interphase transformer (IPT) is utilised. The IPT is a tapped inductor, which has 1:1 turns ratio. The IPT has been previously used in the dc-dc converter 248 applications [170] and more widely in mains frequency, high pulse number rectifiers [101]. The employment of the IPT enables the equivalent switching frequency of the buck converter to be doubled without higher switching losses. The hard- switched and the soft-switched two-inductor boost converters with a two-phase buck converter are respectively shown in Figures 6.1 and 6.2. + Q1 L1 T1 Q2 E D1 L2 D3 CO1 T2 T2 S1 vC D2 Q3 Q4 D4 CO2 S2 + vO − S4 S3 − Figure 6.1 Hard-Switched Two-Inductor Boost Converter with a Two-Phase Buck Converter + Q1 L1 T1 Q2 E D1 L2 Lr T2 D3 CO1 T2 S1 vC D2 Q3 DQ1 C1 C2 DQ2 Q4 D4 CO2 − S2 + vO − S4 S3 Figure 6.2 Soft-Switched Two-Inductor Boost Converter with a Two-Phase Buck Converter The two-phase buck topology shown in Figures 6.1 and 6.2 can be further improved by using the concept of the synchronous rectifier, where the diodes are replaced by the MOSFETs. In a conventional converter which uses a diode in the load current 249 conduction path, the minimisation of the conduction power losses in the diode is difficult as the reduction of the diode forward voltage drop below a certain level presents a great challenge [171]. The synchronous rectifier is able to largely improve the converter efficiency by replacing the diode with a MOSFET, as the forward resistance of the synchronous MOSFET can be very low [172]. If the synchronous rectifier is used, dead time must be applied between the turn-on of the control and the synchronous MOSFETs to prevent “shoot-through”. A Schottky diode is placed in reverse parallel with the synchronous MOSFET in the standard design to stop the load current from flowing through the MOSFET body diode, which normally has a higher voltage drop and inferior reverse recovery characteristic. The hard-switched and the soft-switched two-inductor boost converters, which are fed from a sinusoidally modulated two-phase synchronous buck converter, will be respectively analysed in detail in the following sections. 6.2 Hard-Switched Current Fed Two-Inductor Boost Converter This section provides a detailed analysis of the hard-switched current fed twoinductor boost converter. 6.2.1 Circuit Diagram Figure 6.3 shows the hard-switched two-inductor boost converter with a two-phase 250 synchronous buck converter, where a resistive load is used. Q1 E Q2 Q5 + + + T 1 D1 v1Q6 + − L2 T2 D2 v2 − L1 + vT2p − Q3 Q4 vH − D3 CO1 S2 S1 T2 R vC D4 CO2 + vO − S4 S 3 − Figure 6.3 Hard-Switched Two-Inductor Boost Converter with a Two-Phase Synchronous Buck Converter The converter in Figure 6.3 is a three stage converter including the buck, the boost and the unfolding stages. The transfer functions of the individual stages can be respectively found as: v H ,avg = Dbuck E vC = 2nT 2 v H ,avg 1 − Dboost ⎧ vC , S1 and S 3 on vO = ⎨ ⎩− vC , S 2 and S 4 on (6.1) (6.2) (6.3) where Dbuck and Dboost are respectively the duty ratios of the buck stage MOSFETs Q1 and Q2 and the boost stage MOSFETs Q3 and Q4, nT2 is the transformer T2 turns ratio, E is the converter input voltage, vH,avg is the boost stage average input voltage over one equivalent buck stage switching period, vC is the boost stage output voltage and vO is the converter output voltage. 251 In order to produce the sinusoidal waveforms at the output of the unfolding stage, the duty ratio of the buck stage MOSFETs Dbuck needs to be modulated in a sinusoidal manner as: Dbuck = sin 2π f grid t (6.4) where fgrid is the grid frequency, which is 50 Hz in this thesis. The duty ratio of the boost stage MOSFETs Dboost needs to be a fixed value slightly greater than 50%. Therefore, the gain of the buck stage is the absolute sine function, that of the boost stage is a constant and that of the unfolding stage is ±1 depending on the pair of the switches that are on. The output voltage of the converter can be obtained by multiplying Equations (6.1) to (6.3) as: ⎧ 2nT 2 Dbuck E , S1 and S 3 on ⎪ 1− D ⎪ boost vO = ⎨ ⎪− 2nT 2 Dbuck E , S and S on 2 4 ⎪⎩ 1 − Dboost (6.5) Considering a simplified case where Dboost = 50% and the gate signal of Q1 is synchronised with that of Q3, the theoretical switching waveforms of the buck and the boost stages can be drawn in Figure 6.4, where the switching frequency of the buck stage fbuck is twice that of the boost stage fboost. Tbuck and Tboost are respectively the switching periods of the buck and the boost stages. Figures 6.4(a) and (b) 252 respectively shows the switching waveforms when Dbuck < 50% and Dbuck > 50% . The voltage after the IPT swings between zero and the half input voltage when Dbuck < 50% , while it swings between the half and the full input voltage when Dbuck > 50% . The three levels and the frequency doubling effect can be seen in vH waveform in both cases. vQ1G vQ1G vQ2G Tbuck 2Tbuck 3Tbuck 4Tbuck vQ3G Tbuck 2Tbuck 3Tbuck 4Tbuck t t vQ4G Tboost t 2Tboost vH Tboost t 2Tboost E/2 0 vT2p t vQ2G Tbuck 2Tbuck 3Tbuck 4Tbuck vQ3G Tbuck 2Tbuck 3Tbuck 4Tbuck t t vQ4G Tboost t 2Tboost vH E E/2 0 vT2p Tboost t 2Tboost t t (a) t (b) Figure 6.4 Theoretical Switching Waveforms in the Buck and the Boost Stages (a) Dbuck < 50% (b) Dbuck > 50% 6.2.2 Non-Dissipative Snubbers In order to limit the switch over voltage caused by the leakage inductance during the 253 MOSFET turn-off transition and utilise MOSFETs with low voltage ratings in the hard-switched two-inductor boost converter, voltage clamping or snubber circuits must be used. The non-dissipative snubbers, which do not require additional control circuit, are attractive solutions [173] and they have been previously applied to the hard-switched two-inductor boost converter, as shown in Figure 6.5 [112]. L2 L1 D1 T1 D2 T1 + Cs1 Ds1 E Dsr1 Ds2 Cs2 CO Q2 D4 Lsr1 VO − Dsr2 Q1 R D3 Lsr2 Figure 6.5 Passive Non-Dissipative Snubbers Proposed in [112] The snubber circuit uses two snubber inductors, two snubber capacitors and four diodes and is able to control the peak switch voltage at the MOSFET turn-off. The energy trapped in the snubber circuit can be also transferred in a lossless way back to the voltage source supply E at the next MOSFET turn-on under certain circumstances. In the snubber circuit shown in Figure 6.5, the snubber diode Dsr1 or Dsr2 is only forward biased between the instant when the MOSFET Q1 or Q2 turns on and the 254 instant when the resonant current in the snubber inductor Lsr1 or Lsr2 reaches zero. This is the only duration when the snubber inductors are actively involved in the operation. If the snubber inductor current in the snubber circuit for one MOSFET reaches zero before the other MOSFET turns on, the snubber inductor can be shared by the snubber circuits for both MOSFETs and only one snubber inductor is required. Figure 6.6 shows the hard-switched current fed two-inductor boost converter with the variation of the non-dissipative snubbers in Figure 6.5. + Q1 Q2 L1 T1 + Q5 D1 v1 Q6 + D2 v2 − − + vQ3 − CO1 T2 S1 − S2 R vC Cs1 Ds1 Ds2 vH D3 T2 + E L2 Cs2 + vO − +vCs1− Dsr1 Dsr2 Q3 + vs1 − Q4 Lsr D4 CO2 S4 S3 − Figure 6.6 Hard-Switched Current Fed Two-Inductor Boost Converter with NonDissipative Snubbers The snubber circuit in Figure 6.6 utilises only one snubber inductor, two snubber capacitors and four diodes. Space-saving is possible as the inductors generally have the biggest packages among the components used in the snubber circuit. As the average input voltage and current to the two-inductor boost cell follow the rectified sinusoidal waveforms, variable peak voltages across MOSFETs Q3 and Q4 exist in the converter in Figure 6.3. The snubber circuit therefore only needs to be 255 active when the buck stage duty ratio is relatively high. This avoids the energy circulation in the snubber circuit under low buck stage duty ratios or low boost cell input voltages, when the peak MOSFET voltages are within the certain level without the assistance from the snubber circuit. The energy circulation in the snubber circuit could potentially cause additional power losses and reduce the overall efficiency due to the parasitic effects in the practical circuit. The snubber circuit in Figure 6.6 can be analysed using the equivalent circuit shown in Figure 6.7. + i0 Q3 vQ3 − + vCs1 − Coss,Q3 + vs1 − Cs1 ile Lle Dsr1 iLsr Ds1 E Lsr D vd Cs2 Dsr2 Ds2 E + vCs2 − Coss,Q4 + vs2 − + vQ4 Q4 i0 − Figure 6.7 Equivalent Snubber Circuit In Figure 6.7, Lle is the transformer T2 leakage inductance reflected to the primary. The MOSFET Q3 or Q4 output capacitance is C oss ,Q 3 = C oss ,Q 4 = C oss . The current source i0 models the input inductor L1 or L2 over a high frequency switching period. The snubber capacitance is C s1 = C s 2 = C s . The voltage source vd is the output voltage across the capacitor CO1 or CO2 over a high frequency switching period reflected to the transformer T2 primary winding and the diode D corresponds to the diodes in the voltage-doubler rectifier. The arrangement of the voltage source vd and the diode D in Figure 6.7 assumes a positive current ile in the transformer T2 256 primary winding as illustrated and their polarities reverse when ile becomes negative. In the theoretical analysis, the MOSFET output capacitance Coss,Q3 or Coss,Q4 can be neglected whenever the snubber capacitor Cs1 or Cs2 is actively involved in the operation as the snubber capacitance needs to be selected to be much larger than the MOSFET output capacitance. The MOSFET output capacitance Coss,Q3 or Coss,Q4 is also neglected after the transformer primary current ile first reaches i0 or –i0 or the MOSFET Q3 or Q4 drain source voltage vQ3 or vQ4 reaches its peak in the theoretical analysis. In the practical operation, damped oscillations happen after this time. The MOSFET output capacitance and the transformer leakage inductance oscillate with damping provided by the parasitic resistances in the circuit. In the following discussion, the snubber diodes are considered as ideal components. As the input voltage and current to the boost cell vary, different snubber capacitor voltages result at the end of the snubber operational cycle. The snubber capacitor voltage at the end of the snubber operation is also the snubber capacitor voltage before the MOSFET turn-off, vCs1(0) or vCs2(0), which is less than or equal to zero due to the resonance between the snubber capacitor and inductor and is a critical parameter in determining the operation mode of the snubber circuit. It is established that the snubber circuit can operate in four modes with different initial values of vCs1 or vCs2. The operation of the snubber circuit for the MOSFET Q3 will be analysed within one switching period starting from Q3 turn-off. The range of the buck stage MOSFET duty ratio Dbuck for each operation mode will be determined in due course. Only the first mode of operation for this snubber circuit has been previously reported [112], [173]. The additional modes that arise with a wide input voltage range have 257 not been previously analysed. (i) MODE 1 ( vCs1 (0) = − E ) In Mode 1, vCs1 (0) = − E and the snubber circuit becomes active at the instant when the MOSFET Q3 turns off. In this mode, the snubber circuit returns the energy to the voltage source supply E after the MOSFET Q3 turns on. The snubber circuit in Figure 6.7 moves through six states in one switching period, which are shown in Figure 6.8. The voltage and current waveforms in the snubber circuit are shown in Figure 6.9. Before Q3 turns off at t = 0 , both Q3 and Q4 are on. The state analysis in Mode 1 is given below. It is worth mentioning that before Q3 turns on later in the cycle, the snubber inductor belongs to the snubber circuit for Q4 and operates exactly the same as in the snubber circuit for Q3. Therefore, iLsr will not be included in the analysis of the states before Q3 turns on. Also when ile finally becomes negative after Q4 turns off, the polarities of the voltage source vd and the diode D will be reversed and the transformer leakage inductance Lle, the diode D and the voltage source vd will interact with the snubber circuit for Q4. Therefore, ile will not be included in the analysis of the states after Q3 turns on. • State (a) ( 0 ≤ t ≤ t1 ) 258 This state starts when Q3 turns off at t = 0 . As vCs1 (0) = − E , the diode Ds1 is forward biased and current source i0 linearly charges the capacitor Cs1. The diodes D and Dsr1 are both reverse biased. vCs1 (0) = − E and ile (0) = 0 . The initial conditions are The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively: + i0 vQ3 − + vCs1 − + Cs1 ile vs1 E + Lle vd i0 vQ3 − − + vCs1 − + Cs1 ile vs1 E i0 vQ3 − + vCs1 − + Cs1 ile vs1 E State (b) + Lle vd i0 vQ3 − − + vCs1 − + Cs1 vs1 E i0 vQ3 − + vCs1 − + Cs1 vs1 E + i0 vQ3 Lsr − State (e) Lsr State (d) iLsr − iLsr − State (c) + vd − State (a) + Lle + vCs1 − + Cs1 vs1 E iLsr − State (f) Figure 6.8 Six States in Mode 1 Operation Lsr 259 vQ3G 0t t vCs1 1 2 t3 t4 t5 t6 t 0 t1 t2 t3 t4 t5 t6 t vQ3 0 t1 t2 vd t3 t4 t5 t6 t vs1 0 t1 t2 E t3 t4 t5 t6 t 0 t1 t2 t3 t4 t5 t6 t −E iLsr Figure 6.9 Snubber Voltage and Current Waveforms in Mode 1 Operation vCs1 (t ) = − E + i0 t Cs ile (t ) = 0 vQ 3 (t ) = i0 t Cs (6.6) (6.7) (6.8) 260 v s1 (t ) = E (6.9) This state starts when vQ3 reaches vd at t1 = C s vd . Both of the diodes Ds1 and D i0 • State (b) ( t1 ≤ t ≤ t 2 ) are forward biased and the snubber capacitance resonates with the transformer leakage inductance. The diode Dsr1 remains reverse biased. conditions are vCs1 (t1 ) = v d − E and ile (t1 ) = 0 . The initial The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile and the MOSFET Q3 drain source voltage vQ3 are respectively: where Z1 = Lle Cs vCs1 (t ) = v d − E + i0 Z 1 sin ω1 (t − t1 ) (6.10) ile (t ) = i0 − i0 cos ω1 (t − t1 ) (6.11) vQ 3 (t ) = v d + i0 Z 1 sin ω1 (t − t1 ) (6.12) is the characteristic impedance and ω1 = 1 Lle C s is the angular resonance frequency of the resonant tank made up by Cs1 and Lle. It can been seen from Equation (6.12) that the peak MOSFET voltage is limited to v d + i0 Z 1 . The snubber diode Ds1 anode voltage vs1 is given by Equation (6.9). • State (c) ( t 2 ≤ t ≤ t 3 ) 261 This state starts when ile reaches i0 at t 2 = t1 + π . The diode Ds1 becomes 2ω1 reverse biased as the current flowing through it is zero. The diode D remains forward biased and the current source i0 flows through the transformer leakage inductance and the voltage source vd. The diode Dsr1 is still reverse biased. This state is an idle state, where the snubber circuit is inactive and no resonance happens. The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively: vCs1 (t ) = v d − E + i0 Z 1 (6.13) ile (t ) = i0 (6.14) vQ 3 (t ) = v d (6.15) v s1 (t ) = E − i0 Z 1 (6.16) As the MOSFET Q3 drain source voltage has been forced higher than the steady state transformer primary voltage a parasitic oscillation can occur as the MOSFET output capacitance Coss,Q3 can ring with the transformer leakage inductance Lle. In practice this can cause Electromagnetic Interference (EMI) problems and it is often dealt with using a small RC snubber to deliver damping and a quick decay. • State (d) ( t 3 ≤ t ≤ t 4 ) 262 This state starts when Q3 turns on at t 3 = (1 − Dboost )Tboost . The diode Ds1 remains reverse biased. The diode D is forward biased until ile is discharged to zero by vd. The duration of the discharge is very short as the transformer leakage inductance is very small. The diode Dsr1 becomes forward biased in this state and the snubber inductor resonates with the snubber capacitor. The initial conditions are vCs1 (t 3 ) = v d − E + i0 Z 1 and i Lsr (t 3 ) = 0 . The snubber capacitor Cs1 voltage vCs1, the snubber inductor Lsr current iLsr, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively: vCs1 (t ) = (v d − E + i0 Z 1 ) cos ω 2 (t − t 3 ) i Lsr (t ) = where Z 2 = Lsr Cs (6.17) v d − E + i0 Z 1 sin ω 2 (t − t 3 ) Z2 (6.18) v Q 3 (t ) = 0 (6.19) v s1 (t ) = ( E − v d − i0 Z 1 ) cos ω 2 (t − t 3 ) (6.20) is the characteristic impedance and ω 2 = 1 Lsr C s is the angular resonance frequency of the resonant tank made up by Cs1 and Lsr. • State (e) ( t 4 ≤ t ≤ t 5 ) This state starts when vCs1 reaches –E at t4. The diode Ds1 becomes forward biased. The diode Dsr1 remains forward biased. The voltage source E linearly 263 discharges the snubber inductor Lsr and the energy stored in the snubber inductor is returned to the voltage supply E. The initial conditions are vCs1 (t 4 ) = − E and i Lsr (t 4 ) = v d − E + i0 Z 1 sin ω 2 (t 4 − t 3 ) . The snubber capacitor Cs1 voltage vCs1 Z2 and the snubber inductor Lsr current iLsr are respectively: vCs1 (t ) = − E i Lsr (t ) = i Lsr (t 4 ) − (6.21) E (t − t 4 ) Lsr (6.22) The snubber diode Ds1 anode voltage vs1 and the MOSFET Q3 drain source voltage vQ3 are respectively given by Equations (6.9) and (6.19). • State (f) ( t 5 ≤ t ≤ t 6 ) This state starts when iLsr reaches 0 at t 5 = t 4 + Lsr i Lsr (t 4 ) . This state is an idle E state similar to Mode 1 State (c) and the snubber circuit will become active when Q3 turns off again at t 6 = Tboost except that the snubber inductor will be earlier involved in the operation of the snubber circuit for Q4 when Q4 turns on at 3 t 6 ' = ( − Dboost )Tboost . 2 (ii) MODE 2 ( − E < vCs1 (0) < 0 and vQ 3 (t1 ) < v d ) 264 In Mode 2, − E < vCs1 (0) < 0 and the snubber circuit becomes active after the MOSFET Q3 turns off but before vQ3 reaches vd. In this mode, the snubber circuit does not return the energy to the voltage source supply E after the MOSFET Q3 turns on. The snubber circuit in Figure 6.7 moves through six states in one switching period, which are shown in Figure 6.10. The voltage and current waveforms in the snubber circuit are shown in Figure 6.11. It is worth mentioning that the duration of State (a) is extremely short therefore t1 is very close to zero. Before Q3 turns off at t = 0 , both Q3 and Q4 are on. The state analysis in Mode 2 is given below. As in Mode 1, iLsr or ile will not be included in the analysis of the states before or after Q3 turns on. • State (a) ( 0 ≤ t ≤ t1 ) This state starts when Q3 turns off at t = 0 . As vCs1 (0) > − E , the diode Ds1 is reverse biased and the current source i0 linearly charges the MOSFET Q3 output capacitance Coss,Q3. The diodes D and Dsr1 are both reverse biased. The initial conditions are vQ 3 (0) = 0 and ile (0) = 0 . The snubber capacitor voltage vCs1, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively: vCs1 (t ) = vCs1 (0) (6.23) 265 vQ 3 (t ) = i0 t C oss v s1 (t ) = −vCs1 (0) + (6.24) i0 t C oss (6.25) + i0 Coss,Q3 The transformer primary current ile is given by Equation (6.7). vQ3 − + vCs1 − + Cs1 ile vs1 E + Lle vd i0 vQ3 − − + vCs1 − + Cs1 ile vs1 E i0 vQ3 − + vCs1 − + Cs1 ile vs1 E State (b) + Lle vd i0 vQ3 − − + vCs1 − + Cs1 ile vs1 E i0 vQ3 − + vCs1 − + Cs1 vs1 E + i0 vQ3 Lsr − State (e) vd State (d) iLsr − Lle − State (c) + vd − State (a) + Lle + vCs1 − + Cs1 vs1 E iLsr − State (f) Figure 6.10 Six States in Mode 2 Operation Lsr 266 vQ3G 0 vCs1 t 0 t 0 t vs1 0 E t 0 t iLsr vQ3 vd t1 t2 t3 t4 t5 t6 Figure 6.11 Snubber Voltage and Current Waveforms in Mode 2 Operation • State (b) ( t1 ≤ t ≤ t 2 ) 267 This state starts when vs1 reaches E at t1 = C oss [E + vCs1 (0)] . The diode Ds1 i0 becomes forward biased and the current source i0 linearly charges Cs1. The diode D remains reverse biased as vQ 3 (t1 ) < v d . The diode Dsr1 also remains reverse biased. The initial conditions are vCs1 (t1 ) = vCs1 (0) and ile (t1 ) = 0 . The snubber capacitor Cs1 voltage vCs1 and the MOSFET Q3 drain source voltage vQ3 are respectively: vCs1 (t ) = vCs1 (0) + i0 (t − t1 ) Cs vQ 3 (t ) = E + vCs1 (0) + i0 (t − t1 ) Cs (6.26) (6.27) The transformer primary T2 current ile and the snubber diode Ds1 anode voltage vs1 are respectively given by Equations (6.7) and (6.9). • State (c) ( t 2 ≤ t ≤ t 3 ) This state starts when vQ3 reaches vd at t 2 = t1 + C s [v d − E − vCs1 (0)] . The states i0 of the diodes are the same as Mode 1 State (b) and the snubber capacitance resonates with the transformer leakage inductance. The initial conditions are vCs1 (t 2 ) = v d − E and ile (t 2 ) = 0 . The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile and the MOSFET Q3 drain source voltage vQ3 268 are respectively: vCs1 (t ) = v d − E + i0 Z 1 sin ω1 (t − t 2 ) (6.28) ile (t ) = i0 − i0 cos ω1 (t − t 2 ) (6.29) vQ 3 (t ) = v d + i0 Z 1 sin ω1 (t − t 2 ) (6.30) It can been seen from Equation (6.30) that the peak MOSFET voltage is again limited to v d + i0 Z 1 , where vd and i0 are smaller than those in Mode 1. The snubber diode Ds1 anode voltage vs1 is given by Equation (6.9). • State (d) ( t 3 ≤ t ≤ t 4 ) This state starts when ile reaches i0 at t 3 = t 2 + π and operates in the same way 2ω1 as Mode 1 State (c). The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively given in Equations (6.13) to (6.16). • State (e) ( t 4 ≤ t ≤ t 5 ) This state starts when Q3 turns on at t 4 = (1 − Dboost )Tboost . The states of the diodes are the same as those in Mode 1 State (d) and the snubber inductor resonates with the snubber capacitor. The initial conditions are 269 vCs1 (t 4 ) = v d − E + i0 Z 1 and i Lsr (t 4 ) = 0 . The snubber capacitor Cs1 voltage vCs1, the snubber inductor Lsr current iLsr and the snubber diode Ds1 anode voltage vs1 are respectively: vCs1 (t ) = (v d − E + i0 Z 1 ) cos ω 2 (t − t 4 ) (6.31) v d − E + i0 Z 1 sin ω 2 (t − t 4 ) Z2 (6.32) v s1 (t ) = ( E − v d − i0 Z 1 ) cos ω 2 (t − t 4 ) (6.33) i Lsr (t ) = The MOSFET Q3 drain source voltage vQ3 is given by Equation (6.19). • State (f) ( t 5 ≤ t ≤ t 6 ) This state starts when iLsr reaches 0 at t 5 = t 4 + π and the snubber circuit ω2 operates in the same way as Mode 1 State (f). (iii) MODE 3 ( − E < vCs1 (0) < 0 and vQ 3 (t1 ) = v d ) In Mode 3, − E < vCs1 (0) < 0 but the absolute value of vCs1(0) is so small that the snubber circuit is active after vQ3 reaches vd. As in Mode 2, the snubber circuit operating in this mode does not return the energy to the voltage source supply E after the MOSFET Q3 turns on. The snubber circuit in Figure 6.7 moves through 270 six states in one switching period, which are shown in Figure 6.12. The voltage and current waveforms in the snubber circuit are shown in Figure 6.13. It is worth mentioning that the durations of States (a) and (b) are both extremely short i0 vQ3 − + vCs1 − + Cs1 ile vs1 E + Lle vd i0 Coss,Q3 + Coss,Q3 therefore t1 and t2 are very close to zero and omitted in the waveforms. vQ3 − − + vCs1 − + Cs1 ile vs1 E i0 vQ3 + vCs1 − + vs1 − Cs1 ile State (b) + Lle vd i0 vQ3 E − − + vCs1 − + Cs1 ile vs1 E i0 vQ3 − + vCs1 − + Cs1 vs1 E + i0 vQ3 Lsr − State (e) vd State (d) iLsr − Lle − State (c) + vd − State (a) + Lle + vCs1 − + Cs1 vs1 E iLsr − State (f) Figure 6.12 Six States in Mode 3 Operation Lsr 271 vQ3G 0 t3 vCs1 t4 t5 t6 t 0 t3 t4 t5 t6 t vQ3 0 t3 t4 t5 t6 t 0 t3 t4 t5 t6 t 0 t3 t4 t5 t6 t iLsr vd vs1 E Figure 6.13 Snubber Voltage and Current Waveforms in Mode 3 Operation Before Q3 turns off at t = 0 , both Q3 and Q4 are on. The state analysis in Mode 3 is given below. As in Mode 1, iLsr or ile will not be included in the analysis of the states before or after Q3 turns on. 272 • State (a) ( 0 ≤ t ≤ t1 ) This state starts when Q3 turns off at t = 0 and operates in the same way as Mode 2 State (a). The transformer T2 primary current ile, the snubber capacitor Cs1 voltage vCs1, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively given by Equations (6.7) and (6.23) to (6.25). • State (b) ( t1 ≤ t ≤ t 2 ) This state starts when vQ3 reaches vd at t1 = C oss v d . The diode Ds1 remains i0 reverse biased as v s1 (t1 ) < E . The diode D becomes forward biased and the MOSFET output capacitance resonates with the transformer leakage inductance. The diode Dsr1 remains reverse biased. The initial conditions are vQ 3 (t1 ) = v d , vCs1 (t1 ) = vCs1 (0) and ile (t1 ) = 0 . The transformer T2 primary current ile and the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively: ile (t ) = i0 − i0 cos ω 3 (t − t1 ) (6.34) vQ 3 (t ) = v d + i0 Z 3 sin ω 3 (t − t1 ) (6.35) v s1 (t ) = v d − vCs1 (0) + i0 Z 3 sin ω 3 (t − t1 ) (6.36) 273 where Z 3 = Lle is the characteristic impedance and ω 3 = C oss 1 Lle C oss is the angular resonance frequency of the resonant tank made up by Coss,Q3 and Lle. The snubber capacitor Cs1 voltage vCs1 is given by Equation (6.23). • State (c) ( t 2 ≤ t ≤ t 3 ) This state starts when vs1 reaches E at t2. The diode Ds1 becomes forward biased and the snubber capacitance resonates with the transformer leakage inductance. The diode D remains forward biased and the diode Dsr1 reverse biased. The initial conditions are vCs1 (t 2 ) = vCs1 (0) and ile (t 2 ) = i0 − i0 cos ω 3 (t 2 − t1 ) . The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile and the MOSFET Q3 drain source voltage vQ3 are respectively: vCs1 (t ) = v d − E + [i0 − ile (t 2 )]Z 1 sin ω1 (t − t 2 ) − [v d − E − vCs1 (0)]cos ω1 (t − t 2 ) ile (t ) = i0 − v d − E − vCs1 (0) sin ω1 (t − t 2 ) − [i0 − ile (t 2 )]cos ω1 (t − t 2 ) Z1 (6.37) (6.38) vQ 3 (t ) = v d + [i0 − ile (t 2 )]Z 1 sin ω1 (t − t 2 ) − [v d − E − vCs1 (0)]cos ω1 (t − t 2 ) (6.39) It can been seen from Equation (6.39) that the peak MOSFET voltage is limited to v d + [vd − E − vCs1 (0)]2 + [i0 − ile (t 2 )]2 Z12 voltage vs1 is given by Equation (6.9). . The snubber diode Ds1 anode 274 • State (d) ( t 3 ≤ t ≤ t 4 ) This state starts when ile reaches i0 at t3 and operates in the same way as Mode 1 State (c). The snubber capacitor Cs1 voltage vCs1 and the snubber diode Ds1 anode voltage vs1 are respectively: vCs1 (t ) = vCs1 (t 3 ) (6.40) v s1 (t ) = v d − vCs1 (t 3 ) (6.41) The transformer T2 primary current ile and the MOSFET Q3 drain source voltage vQ3 are respectively given in Equations (6.14) and (6.15). • State (e) ( t 4 ≤ t ≤ t 5 ) This state starts when Q3 turns on at t 4 = (1 − Dboost )Tboost . The states of the diodes are the same as those in Mode 1 State (d). The initial conditions are vCs1 (t 4 ) = vCs1 (t 3 ) and i Lsr (t 4 ) = 0 . The snubber capacitor Cs1 voltage vCs1, the snubber inductor Lsr current iLsr and the snubber diode Ds1 anode voltage vs1 are respectively: vCs1 (t ) = vCs1 (t 3 ) cos ω 2 (t − t 4 ) (6.42) vCs1 (t 3 ) sin ω 2 (t − t 4 ) Z2 (6.43) i Lsr (t ) = 275 v s1 (t ) = −vCs1 (t 3 ) cos ω 2 (t − t 4 ) (6.44) The MOSFET Q3 drain source voltage vQ3 is given by Equation (6.19). • State (f) ( t 5 ≤ t ≤ t 6 ) This state starts when iLsr reaches 0 at t 5 = t 4 + π and the snubber circuit ω2 operates in the same way as Mode 1 State (f). (iv) MODE 4 ( vCs1 (0) = 0 ) In Mode 4, vCs1 (0) = 0 and the snubber circuit is not active during the converter operation. The diodes in the snubber circuit remain reverse biased at all times. As the snubber capacitor is charged to different voltage levels at the end of the snubber operation under different converter buck stage duty ratios, the operation mode of the snubber circuit is intrinsically determined by Dbuck. The border conditions of Dbuck for each operation mode are now analysed. In Mode 1, in order to have vCs1 (0) = − E , the snubber capacitor voltage vCs1 must reach –E before the snubber inductor current iLsr reaches zero in State (d). 276 According to Equation (6.18), iLsr reaches zero at t 4 ' = t 3 + π . Therefore, the ω2 border condition for the snubber circuit to operate in Mode 1 is: vCs1 (t 4 ' ) = − E (6.45) Manipulations of Equations (6.1) and (6.2) yield: vd = Dbuck E 1 − Dboost (6.46) According to Equation (6.4), if the converter average power is Pavg, the converter instantaneous power p at the converter output is: 2 p = 2 Pavg Dbuck (6.47) The converter instantaneous power can be also written at the input of the twoinductor boost cell as: p = v H ,avg ⋅ 2i0 Manipulations of Equations (6.1), (6.47) and (6.48) yield: (6.48) 277 i0 = Pavg E Dbuck (6.49) Substituting Equations (6.46) and (6.49) to (6.17) and (6.45) and replacing Dbuck with Dbuck,1, the lower border buck stage duty ratio for Mode 1 snubber operation, yield: Dbuck ,1 = 2 Pavg 1 + 2 Z1 1 − Dboost E (6.50) Therefore the condition for the snubber circuit to operate in Mode 1 is Dbuck ≥ Dbuck ,1 . If Dbuck < Dbuck ,1 , the snubber circuit starts to operate in Mode 2. It is also required that in this mode, the snubber diode Ds1 anode voltage vs1 reaches E before the MOSFET Q3 drain source voltage reaches vd in State (a). According to Equations (6.24) and (6.25), the lower border condition for the snubber circuit to operate in Mode 2 is: v d C oss [E + vCs1 (0)]C oss = i0 i0 (6.51) According to Equation (6.31), the initial snubber capacitor Cs1 voltage vCs1(0) can be 278 found as: vCs1 (0) = vCs1 (t 5 ) = E − v d − i0 Z 1 (6.52) Therefore Equation (6.51) can be simplified to: 2 E − 2v d − i 0 Z 1 = 0 (6.53) Substituting Equations (6.46) and (6.49) to (6.53) and replacing Dbuck with Dbuck,2, the lower border buck stage duty ratio for Mode 2 snubber operation, yield: Dbuck , 2 = 1 Pavg 1 Z1 + 1 − Dboost 2 E 2 (6.54) Therefore the condition for the snubber circuit to operate in Mode 2 is Dbuck , 2 ≤ Dbuck < Dbuck ,1 . If Dbuck < Dbuck , 2 , the snubber circuit starts to operate in Mode 3. It is also required that in this mode, the peak snubber diode Ds1 anode voltage vs1 be greater than E in State (b). According to Equation (6.36), the snubber diode Ds1 anode voltage vs1 reaches its peak at t 2 ' = t1 + π . As vCs1 (0) = 0 when the snubber circuit operates 2ω 3 at the border between Modes 3 and 4, the lower border condition for the snubber 279 circuit to operate in Mode 3 can be found as: v d + i0 Z 3 = E (6.55) Substituting Equations (6.46) and (6.49) to (6.55) and replacing Dbuck with Dbuck,3, the lower border buck stage duty ratio for Mode 3 snubber operation, yield: Dbuck ,3 = 1 Pavg 1 + 2 Z3 1 − Dboost E (6.56) Therefore the condition for the snubber circuit to operate in Mode 3 is Dbuck ,3 < Dbuck < Dbuck , 2 . If Dbuck ≤ Dbuck ,3 , the snubber circuit starts to operate in Mode 4, where the snubber circuit is not active at all times in the converter operation. To illustrate the snubber operation a circuit model is developed with the following parameters: • The converter input voltage E = 20 V and average power Pavg = 100 W . • The boost stage switching frequency Dboost = 0.55 . f boost = 75 kHz and duty ratio 280 • The transformer T2 leakage inductance Lle = 0.60 µH and the MOSFET Q3 Infineon SPB80N06S2L-07 output capacitance C oss = 990 pF . In the design of the snubber circuit, the leakage inductance can be considered as a fixed value once the transformer T2 is designed. Therefore the peak switch voltage over a low frequency cycle decreases with a larger snubber capacitance according to Equation (6.12) while the range of Dbuck for Mode 1 snubber operation when the snubber circuit returns the energy to the supply voltage increases with a smaller snubber capacitance according to Equation (6.50). The snubber capacitance is designed as 0.1 µF to obtain a reasonable peak switch voltage and range of Dbuck for Mode 1 snubber operation. Once the snubber capacitance is determined, the peak snubber inductor current over a low frequency cycle decreases with a larger snubber inductance according to Equation (6.18) while the time duration of the non-zero snubber inductor current decreases with a smaller snubber inductance according to Equations (6.17), (6.22), (6.32) and (6.43). The snubber inductance is initially designed as 10 µH. It is finally confirmed that the time duration of the non-zero snubber inductor current is less than half of Tboost in Modes 1 to 3 and this justifies the sharing of the snubber inductor by the two snubber circuits for Q3 and Q4. The border conditions for the four operation modes of the snubber circuit can be calculated and shown in Table 6.1. 281 Dbuck,1 Dbuck,2 Dbuck,3 0.706 0.396 0.119 Table 6.1 Border Conditions for Four Operation Modes of the Snubber Circuit The peak switch voltage when Dbuck = 1 can be calculated as 56.7 V and with a small limit on the upper value of Dbuck MOSFETs with either 55 V or 60 V voltage ratings may be considered in the circuit design. It is worth noting that the border conditions in Table 6.1 are estimations only as the calculation assumes 990 pF output capacitance of the MOSFET with 55 V voltage rating. In the practice a little more margin in the voltage rating would be required. This is a reliability issue for the practitioner and we will not further consider here. Figure 6.14 shows the theoretical waveforms when Dbuck = 1 and the snubber circuit operates in Mode 1. This mode is characterised by the MOSFET Q3 drain source voltage waveform with a small voltage slope at the turn-off due to the linear charging of the relatively large snubber capacitance. Figure 6.15 shows the theoretical waveforms when Dbuck = 0.60 and the snubber circuit operates in Mode 2. This mode is characterised by the MOSFET Q3 drain source voltage waveform with an initial large voltage slope followed by a small voltage slope at the turn-off due to the linear charging of the much smaller MOSFET output capacitance first and then the larger snubber capacitance. Snubber Inductor Lsr Current iLsr (A) 60 50 40 30 20 10 0 0 2 4 6 8 4 3.5 3 2.5 2 1.5 1 0.5 10 12 14 16 18 20 22 24 26 0 0 2 4 6 8 t (µs) 40 30 20 10 0 -10 40 30 20 10 0 -10 -20 -20 -30 -40 0 10 12 14 16 18 20 22 24 26 t (µs) Snubber Diode Ds1 Anode Voltage vs1 (V) Snubber Capacitor Cs1 Voltage vCs1 (V) MOSFET Q3 Drain Source Voltage vQ3 (V) 282 -30 2 4 6 8 10 12 14 16 18 20 22 24 26 t (µs) -40 0 2 4 6 8 10 12 14 16 18 20 22 24 26 t (µs) Figure 6.14 Theoretical Waveforms in Mode 1 Snubber Operation Figure 6.16 shows the theoretical waveforms when Dbuck = 0.35 and the snubber circuit operates in Mode 3. This mode is characterised by the MOSFET Q3 drain source voltage waveform with large voltage slopes at the turn-off almost until it reaches its peak due to the linear charging of the MOSFET output capacitance first and the resonance between the MOSFET output capacitance and the transformer leakage inductance. Then the resonance between the snubber capacitance and the transformer leakage inductance only happens in a very short time before the transformer primary current reaches i0. Snubber Inductor Lsr Current iLsr (A) 60 50 40 30 20 10 0 0 2 4 6 8 2 1.5 1 0.5 10 12 14 16 18 20 22 24 26 0 0 2 4 6 8 t (µs) 20 15 10 5 0 -5 30 20 10 0 -10 -10 -20 -15 -20 0 10 12 14 16 18 20 22 24 26 t (µs) Snubber Diode Ds1 Anode Voltage vs1 (V) Snubber Capacitor Cs1 Voltage vCs1 (V) MOSFET Q3 Drain Source Voltage vQ3 (V) 283 2 4 6 8 10 12 14 16 18 20 22 24 26 t (µs) -30 0 2 4 6 8 10 12 14 16 18 20 22 24 26 t (µs) Figure 6.15 Theoretical Waveforms in Mode 2 Snubber Operation The experimental waveforms of the snubber circuit operating in Modes 1, 2 and 3 are respectively shown in Figures 6.17 to 6.19. From top to bottom, Figures 6.17 to 6.19 respectively shows the MOSFET Q3 drain source voltage vQ3, the diode Ds1 anode voltage vs1 and the snubber inductor Lsr current iLsr. The key components used in the snubber circuit are: Snubber Inductor Lsr Current iLsr (A) 60 50 0.2 0.15 40 30 20 0.1 0.05 10 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 0 2 4 6 8 t (µs) 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 10 12 14 16 18 20 22 24 26 t (µs) Snubber Diode Ds1 Anode Voltage vs1 (V) Snubber Capacitor Cs1 Voltage vCs1 (V) MOSFET Q3 Drain Source Voltage vQ3 (V) 284 30 20 10 0 -10 -20 -30 0 2 4 t (µs) 6 8 10 12 14 16 18 20 22 24 26 t (µs) Figure 6.16 Theoretical Waveforms in Mode 3 Snubber Operation • Capacitors Cs1 and Cs2 – Kemet class X7R surface mount capacitor C0805C104K5RAC, C = 0.1 µF , Vdc = 50 V . • Inductor Lsr – Core type Siemens RM7 with 0.16 mm air gap in the centre pole, ferrite grade Siemens N48, inductor winding N L = 7 turns. • Diodes Ds1, Ds2, Dsr1 and Dsr2 – Fairchild SS26, I F = 2.0 A , V RRM = 60 V , V F = 0.7 V . 285 Figure 6.17 Experimental Waveforms in Mode 1 Snubber Operation Figure 6.18 Experimental Waveforms in Mode 2 Snubber Operation 286 Figure 6.19 Experimental Waveforms in Mode 3 Snubber Operation The buck stage duty ratios in Figures 6.17 and 6.19 are respectively Dbuck = 0.84 , Dbuck = 0.57 and Dbuck = 0.38 and these are estimated by the individual instantaneous converter output voltages captured by the oscilloscope. The characteristics of the individual operation modes can be clearly observed although the buck stage duty ratio is not a constant under the consecutive high frequency cycles in the practical converter. Some differences between the theoretical and the experimental waveforms lie on the damped oscillations after the MOSFET Q3 drain source voltage vQ3 reaches its peak due to the resonance between the MOSFET output capacitance and the transformer leakage inductance and as well 287 on the voltage source vd being not a constant due to the voltage ripple on the capacitors in the voltage-doubler rectifier of the boost cell. 6.2.3 Experimental Results In the practical implementation of the hard-switched current fed two-inductor boost converter with the power rating of 100 W, the switching frequency of the buck stage MOSFETs fbuck and that of the boost stage MOSFETs fboost are respectively selected to be f buck = 150 kHz and f boost = 75 kHz . The two-phase synchronous buck converter is based upon a commercial two-phase synchronous step-down switching regulator – Linear Technology LTC1929CG. The standard control loop is modified slightly to secure a widely variable output voltage range. Two current transformers are used to sense the control MOSFET drain current to accomplish the chip-embedded current mode control, which is critical in the converter as it prevents the IPT from saturation. The current transformers also allow the output voltage range of the control to be extended to 0 to 20 V. On the other hand, the IPT is also gapped so that it will not saturate under a certain level of unbalanced current from the two-phase buck converter. The switching timing of the two-phase buck converter is synchronised with the synchronising signal generated by the regulating pulse width modulator – Unitrode UC3526A, which is used as the switching controller for the MOSFETs in the two-inductor boost cell. 288 In order to remove the power loss related to the diode reverse recovery in the voltage-doubler rectifier, Schottky diodes are preferred instead of normal PN junction diodes. However, normal Schottky diodes are not qualified as they have only low reverse breakdown voltage ratings. Therefore, silicon carbide Schottky diodes, which have high reverse breakdown voltage ratings and near-zero reverse recovery time, are suited in this application [174]. These diodes are targeted toward the single phase boost rectifier market. This too is a 400-V boost converter design and has similar reverse recovery issues. To avoid the high side drivers and the additional control circuitry for the MOSFETs in the unfolder, electrically isolated optical MOSFET drivers – Dionics DIG-11-1530-DD are used to provide the MOSFET gate signals. The selected MOSFET driver has an output open circuit voltage of 15 V, a short circuit current of 60 µA at input current of 30 mA with 50% duty cycle and an isolation voltage of 2500 V. The MOSFET gate charging current from the integrated driver is large enough to achieve short turn-on transitions. The integrated driver also has an embedded active discharge circuit to discharge the MOSFET gate capacitance so that fast turn-off behaviours can be easily obtained. Other main components used in the converter are listed below: • MOSFETs Q1, Q2, Q5 and Q6 – International Rectifier IRF7809AV, V DS = 30 V , I D = 13.3 A , R DS (on ) = 0.009 Ω . 289 • Diodes D1 and D2 – ON Semiconductor MRBS130LT3, I F = 1.0 A , VRRM = 30 V , VF = 0.395 V . • IPT T1 – Core type Epcos EFD15 with a 0.35-mm air gap in each of the three core legs, ferrite grade Epcos N87, primary winding N p1 = 14 turns and secondary winding N s1 = 14 turns. • Inductors L1 and L2 and transformer T2 – Core type Ferroxube ETD39 with a 0.5-mm air gap in each of the two outer legs, ferrite grade Ferroxube 3F3, Structure A magnetic integration, inductor winding N L1 = N L 2 = 23 turns, primary winding N p 2 = 23 turns, secondary winding N s 2 = 98 turns. • MOSFETs Q3 and Q4 – Infineon SPB80N06S2L-07, V DS = 55 V , I D = 80 A , R DS (on ) = 0.007 Ω . • Diodes D3 and D4 – Microsemi UPSC600, I F = 1.0 A , V RRM = 600 V , V F = 1.6 V . • Capacitors CO1 and CO2 – Vishay class X7R multilayer ceramic surface mount capacitor VJ1210Y104KXCAT, C = 0.1 µF , Vdc = 200 V . • MOSFETs S1 to S4 – International Rectifier IRF830AS, V DS = 500 V , I D = 5.0 A , R DS (on ) = 1.4 Ω . Figure 6.20 shows the buck converter waveforms under static tests. From top to bottom, Figures 6.20(a) and (b) respectively shows the waveforms of v1, v2 and vH with Dbuck lower and greater than 50%. The voltage after the IPT swings between 290 zero and the half input voltage when Dbuck < 50% while it swings between the half and the full input voltages when Dbuck > 50% . In both cases, the frequency of the voltage vH after the IPT is twice that of the voltage v1 or v2. Figure 6.21 shows the waveforms of the two-inductor boost converter output voltage vC and the input voltage vH from top to bottom with the sinusoidal modulation. A three-level modulation can be clearly seen from the vH waveform although the displayed waveform is heavily aliased. The screen of the oscilloscope has a limited number of pixels therefore only the envelope of the PWM waveform is evident and asymmetry exists in the displayed vH waveform. Small voltage spikes appear every half grid frequency cycle because all four switches in the unfolder turn off for a small amount of time around the zero crossing of the sinusoidal waveform. Figure 6.22 shows the gate waveforms of the low frequency unfolder switches and the output voltage vO from top to bottom. In this case a resistive load is supplied and this is adjusted to give the rated power, 100 W average, at 240 V ac, which is equivalent to the nominal mains voltage. Figure 6.23 shows the MOSFETs Q3 and Q4 drain source voltages and the voltage across the SiC Schottky diode when the converter output voltage is close to its peak. The snubber circuit controls the maximum peak switch voltage in a low frequency cycle to around 50 V. Technically, this allows the MOSFETs with drain-source breakdown voltage ratings of 55 V to be used in the boost cell. In a commercial 291 application a large voltage margin would be desired from a reliability view point. The SiC diode voltage waveform is relatively clean although some high frequency oscillations exist due to the resonance between the transformer leakage inductance referred to the secondary and the diode junction capacitance. Figure 6.24 shows the MOSFET Q3 drain source voltage vQ3 and the diode Ds1 anode voltage vs1 from top to bottom when the snubber circuit operates in Mode 1. These have been analysed in detail in Section 6.2.2. In the hard-switched current fed two-inductor boost converter, a conversion efficiency of 92% at the rated power rating of 100 W was obtained. Both the input and the output powers were measured using the mathematical functions of a Tektronix TDS5034 four-channel oscilloscope equipped with the voltage and the current probes measuring the converter input and output voltages and currents. The current probes are Tektronix TCP202. The power loss includes the losses in all three conversion stages in the hard-switched current fed two-inductor boost converter including the buck, the boost and the unfolding stages. 292 (a) (b) Figure 6.20 Experimental Waveforms in the Two-Phase Buck Converter (a) Dbuck < 50% (b) Dbuck > 50% 293 100V Figure 6.21 Experimental Waveforms of the Sinusoidal Modulation 250V Figure 6.22 Experimental Waveforms in the Unfolder 294 250V Figure 6.23 Experimental Waveforms in the Two-Inductor Boost Cell Figure 6.24 Experimental Waveforms in the Snubber 295 A photo of the prototype hard-switched current fed two-inductor boost converter is shown in Figure 6.25. At the time of writing the converter had not been operated in a grid interactive mode. There is no obvious technical impediment. However, to do so would require the development of a suitable control system and this will require additional time. This is an area of future work. Figure 6.25 Photo of the Hard-Switched Current Fed Two-Inductor Boost Converter 6.3 Soft-Switched Current Fed Two-Inductor Boost Converter This section provides a detailed analysis of the soft-switched current fed twoinductor boost converter. 296 6.3.1 Circuit Diagram Figure 6.26 shows the soft-switched two-inductor boost converter with a two-phase synchronous buck converter, where a resistive load is used. Q1 + + T1 Q2 E Q5 + D1 v1 Q6 D2 v2 + L1 Lr − T2 D3 CO1 T2 − S1 vC vH Q3 − L2 DQ3 C1 + + vC1 vC2 − − C2 DQ4 Q4 D4 CO2 − S2 + vO − S4 S3 Figure 6.26 Soft-Switched Two-Inductor Boost Converter with a Two-Phase Synchronous Buck Converter The buck and the unfolding stages of the converter are the same as those in the hardswitched current fed two-inductor boost converter and their transfer functions are respectively given by Equations (6.1) and (6.3). The transfer function of the boost stage is determined by the converter design parameters such as the resonant inductance, capacitance and the load condition. As a constant gain is required in the boost stage, the soft-switched two-inductor boost cell is able to operate under the fixed switching frequency and switch duty ratio. Therefore, an optimised operating point, which is favourable in the power loss respect, can be selected for the boost cell as discussed in Chapter 4. However as the input voltage of the boost cell follows an absolute sine function as given by Equation (6.4), the average variable power loss over a low frequency sinusoidal 297 cycle, Ploss,avg, must be established instead so that the operating point with the minimum average power loss in the boost cell can be identified. The calculation can be performed numerically with the MATLAB program with the same set of the component parameters used in Section 4.6.1. The average power loss in Regions 1 Ploss,avg (W) and 2 are respectively drawn in Figures 6.27 and 6.28. k ∆1 Figure 6.27 Average Variable Power Loss in Region 1 Following the same process in Section 4.6.2, the circuit parameters are selected to be k = 1.1 , ∆ 1 = 0 and α d = 0 , where the average power loss is 2.33 W and the peak switch voltage is 90 V. Then the design parameters can be obtained as below: 298 The resonant inductance Lr = 1.40 µH . • The resonant capacitance C r = 15.7 nF . • The transformer T2 turns ratio nT 2 = 3.95 . Ploss,avg (W) • k ) dians a r ( αd Figure 6.28 Average Variable Power Loss in Region 2 6.3.2 Resonant Gate Drive The two-inductor boost cell in the converter shown in Figure 6.26 employs the resonant technique and ZVS can be achieved. Theoretically, the switching power losses in the main switching devices are completely removed. However, higher current and voltage stresses exist due to the resonant feature and they lead to higher 299 conduction power losses in the switching devices. In the converter design, attention has to be paid to the conduction power losses so that the reduction in the switching power losses will not be forfeited. Therefore, the resistance in the conduction paths must be minimised and MOSFETs with low drain source on resistances are desirable. A low MOSFET drain source on resistance normally demands a large die size and the MOSFET input capacitance tends to be large [175]. This results in high power losses in the drive circuit if a conventional MOSFET gate drive circuit is used. The conventional MOSFET gate drive circuit commonly employs two transistors in the totem-pole arrangement as shown in Figure 6.29. Qt Qp VDD Qb Figure 6.29 Conventional MOSFET Gate Drive Circuit In Figure 6.29, Qt and Qb are the control transistors in the gate drive circuit and Qp is the power MOSFET in the main circuit. VDD is the gate drive circuit supply voltage. While the conventional MOSFET driver is easy to use and has a compact package readily available in the integrated semiconductor chip format, it is subject to the following power loss mechanisms [176]: 300 • CV 2 loss, which is caused by the MOSFET gate capacitance charging and discharging current flowing through the drain source on resistances of the two control transistors in the driver Qt and Qb and the internal gate resistance of the power MOSFET Qp. • Cross conduction loss, which results from the shorting of the supply voltage across the two transistors Qt and Qb in the driver if their on times are overlapped to any degree. • Switching loss, which is due to the hard switching conditions of the two transistors Qt and Qb in the driver. Among these power losses, CV 2 loss is the dominant part. It is independent of the gate charge rate and will not reduce with shorter gate charging times. Therefore, a high MOSFET input capacitance requires high gate charge from the drive circuit and causes high CV 2 loss in the conventional MOSFET drivers. The drive power is exacerbated when the switching frequency is high as the power dissipation is proportional to the switching frequency. In order to reduce the power consumption in the MOSFET gate drive circuit, the resonant technique can be used and many types of the resonant gate drive circuits have been proposed [147], [176]-[181]. In [176] and [177], higher than normal charging or discharging current due to the resonant operation flows through the transistors in the drive circuit and the conduction power loss is still high. In [178][180], the power loss of the drive circuit cannot be minimised as transistors in the 301 gate drive circuit still switch under the hard-switching conditions. In [147] and [181], an ideally lossless gate drive circuit has been proposed as shown in Figure 6.30. Both of the MOSFET turn-on and turn-off are achieved by using a small inductor LG to provide current to charge and discharge the input capacitance of the MOSFET during a transition time when neither of the control transistors in the drive circuit conducts. A capacitor CG, is required to maintain a dc level equal to the average gate voltage. Qt LG Qp VDD CG Qb Figure 6.30 Resonant Transition Gate Drive Proposed in [147] and [181] In the two-inductor boost converter, the gate signals of the two MOSFETs are 180º out of phase and this allows the gate charging inductor LG to be shared by the two drive circuits and the dc level setting capacitor CG to be removed. The individual MOSFET input capacitances function as the dc level setting capacitor for each other. Figure 6.31 shows the proposed resonant transition gate drive circuit for the twoinductor boost converter. Compared with the conventional MOSFET gate drive circuit shown in Figure 6.29, only one small inductor LG is introduced between the gates of the two power MOSFETs Q3 and Q4. 302 iQ3t iQ4t Q3t Q4t Q3 VDD iQ3b Q3b + vQ3G − iG3 Q4 + vLG − iLG LG iG4 + vQ4G iQ4b Q4b VDD − Figure 6.31 Resonant Transition Gate Drive for the Two-Inductor Boost Cell Although the resonant gate drive circuit in Figure 6.31 is not significantly more complex than the conventional MOSFET gate drive circuit and the component count is not greatly higher, the control of the resonant gate drive circuit does become much more complex and this is especially true compared with that of the integrated MOSFET driver chips. The operation of the resonant transition gate drive circuit can be explained using the waveforms shown in Figure 6.32. The inductor current can be approximated as a constant during the time interval between the instant when one MOSFET gate capacitance starts being charged and the instant when the other MOSFET gate capacitance finishes being discharged. This time interval is insignificantly short compared with the entire switching period Tboost as long as the switching duty ratio Dboost is not significantly larger than 50%. Therefore the MOSFET gate capacitances are charged and discharged linearly. The MOSFETs Q3 and Q4 are considered to be fully on when the individual gate capacitance voltages are higher than half of the gate drive supply voltage VDD. During the time interval Td1, the gate capacitance of Q4 is charged. The gate 303 capacitance of Q3 is later discharged over a time interval of the same length. The two P type transistors Q3t and Q4t turn on and tie the gates of the power MOSFETs to the positive rail of the gate drive circuit power supply once the gate capacitances are charged to that level while the two N type transistors Q3b and Q4b turn on and tie the gates of the power MOSFETs to the ground once the gate capacitances are completely discharged. During the time interval Td2, when Q3 is on and Q4 is off, the inductor current linearly increases from the negative peak to the positive peak. Therefore the energy is transferred back and forth between two MOSFET gate capacitances through the inductor. vQ3G VDD vQ4G0 VDD DboostTboost Tboost t 0 vLG VDD DboostTboost Tboost t 0 DboostTboost Tboost t DboostTboost Tboost t −VDD iLG ILGp Td2 0 Td1 On Devices −ILGp Q4t Q3t Q3b Q3t Q4b Q4t Q4b Figure 6.32 Theoretical Waveforms in the Resonant Transition Gate Drive 304 Theoretically, the resonant gate drive circuit has zero power loss due to the following features: • The MOSFET input capacitance is charged and discharged by the inductor current and CV 2 loss can be removed. • A transition time or dead time of Td1 exists between the turn-on of the two transistors in the totem-pole arrangement in the gate drive circuit and the cross conduction loss can be avoided. • Both transistors in the gate drive circuit turn on or off at zero voltage or zero current and the switching power loss is absent. In the gate drive circuit design and power loss analysis, a dead time ratio ρ is defined as: ρ= Td 1 Tboost (6.57) Therefore the inductor linear charging or discharging interval can be obtained as: Td 2 = (1 − Dboost − ρ )Tboost (6.58) Assuming that the input capacitance of the MOSFET Q3 or Q4 is Ciss, the peak inductor current ILGp and the inductance LG are respectively: 305 I LGp = LG = C issV DD f boost ρ (1 − Dboost − ρ )VDD 2 I LGp f boost (6.59) (6.60) Theoretically, the resonant transition gate drive is lossless. However, the inductor current iLG also flows through the top transistor Q3t or Q4t when the gate capacitance of the MOSFET Q3 or Q4 is fully charged, through the bottom transistor Q3b or Q4b when the gate capacitance of the MOSFET Q3 or Q4 is fully discharged and through the gate of the MOSFET Q3 or Q4 during the gate charging and discharging intervals. Therefore, due to the parasitic effects, a small amount of power loss still exists and has the following origins: • The power loss in the inductor between the gates of the two MOSFETs PLG : 2 PLG = RLG I LG , rms (6.61) where RLG is the equivalent series dc plus ac resistance of LG and ILG,rms is the effective current in LG. • The conduction power loss in the four control transistors in the drive circuit PQ 34 tb ,cond : 306 PQ 34tb,cond = 2( RDS ( on ),t I Q2 3t ,rms + RDS ( on ),b I Q2 3b,rms ) (6.62) where RDS(on),t and RDS(on),b are respectively the drain source on resistances of the top and the bottom transistors and IQ3t,rms and IQ3b,rms are respectively the effective currents in Q3t and Q3b. • The conduction power loss in the gate of the two power MOSFETs PQ 34 : PQ 34 = 2 R g I G2 3,rms (6.63) where Rg is the internal gate resistance of the power MOSFET and IG3,rms is the effective charging and discharging current in the gate of Q3. • The CV 2 loss in the drive circuit of the four control transistors PQ 34 tb , drive : 2 PQ 34tb,drive = 2(Ciss ,t + Ciss ,b )VDD f boost (6.64) where Ciss,t and Ciss,b are respectively the input capacitances of the top and the bottom transistors and it is assumed that the supply voltage is also VDD in the gate drive circuit for the control transistors. If the duty ratio Dboost is not significantly larger than 50% and the zero inductor voltage period in Figure 6.32 can be neglected, the current terms in Equations (6.61) 307 to (6.63) can be respectively found as: I LG ,rms = 1 + 8ρ I LGp 3 (6.65) I Q 3t ,rms = 1 + 8ρ I LGp 6 (6.66) I Q 3b ,rms = 1 − 4ρ I LGp 6 (6.67) I G 3,rms = 2 ρ I LGp (6.68) It is worth noting that Equations (6.65) to (6.68) can be also used to estimate the individual effective currents when the charging or discharging intervals of Q3 and Q4 overlap as long as ρ is kept small. The total power loss in the resonant transition gate drive circuit is: Pdrive = PLG + PQ 34tb ,cond + PQ 34 + PQ 34tb , drive (6.69) Equations (6.61) to (6.69) confirm that the power loss in the gate drive circuit is very small if the parasitic component values are small. The MOSFET input capacitance includes gate-to-drain and gate-to-source capacitances. Due to the Miller Effect, the input capacitance is highly non-linear and the total gate charge QG is therefore a better parameter in determining the turn- 308 on and the turn-off characteristics of the MOSFET [182]. Consequently, the peak inductor current can be found more accurately as: I LGp = QG f boost ρ (6.70) In the selection of the transistors in the MOSFET gate drive circuit, special attention must be paid to their total gate charges, which must be at least an order of magnitude less than those of the power MOSFETs. Apart from being an additional loss term, a low gate charge of the transistor is a must in obtaining fast turn-on and turn-off transitions. A short turn-on transition after the power MOSFET input capacitance is charged to the supply voltage stops the peak inductor current from flowing through the reverse body diode of the transistors. Otherwise, higher conduction power loss could result due to the high forward voltage of the transistor reverse body diode. Moreover, if the dead time is very short, the turn-on and the turn-off transitions of the transistors must be kept minimal to ensure that the on times of the two transistors in the totem-pole do not overlap. In the practical operation of the resonant transition gate drive circuit, the MOSFET gate charging and discharging currents are not a constant as the inductor between two gates resonates with the MOSFET input capacitance when both control transistors in its drive circuit are turned off. Therefore, the actual charging and discharging currents iG3 and iG4 follow the sinusoidal waveform and their absolute values are higher than the absolute inductor current iLG at the end of its linear 309 charging or discharging interval. If the average of the absolute of iG3 or iG4 is IG and the absolute value of iLG at the end of its linear charging or discharging interval is ILG’, where I G > I LG ' , Equations (6.60) and (6.70) can be respectively rewritten to: LG = (1 − Dboost − ρ )VDD 2 I LG ' f boost IG = QG f boost ρ (6.71) (6.72) However, ILG’ in Equation (6.71) cannot be easily obtained and this makes the inductor design difficult. In order to simplify the design process of the inductance LG, ILG’ can be approximated by IG in Equation (6.72) as ρ is small. Equation (6.71) can be further rewritten to: LG = (1 − Dboost − ρ )VDD 2 I G f boost (6.73) As I G > I LG ' , the actual inductance value should be selected to be slightly larger than what is calculated from Equation (6.73). A simulation is performed with SIMULINK with the following parameters: • The gate drive circuit supply voltage VDD = 12 V , • The total gate charge of the MOSFET STB50NE10 QG = 123 nC , 310 • The switching frequency f boost = 500 kHz , the duty ratio Dboost = 0.6 and the dead time ratio ρ = 0.1 , and • The inductor in the gate drive circuit LG = 7.3 µH . The two power MOSFETs Q3 and Q4 are modelled by two capacitors and the capacitance values are derived from the total gate charge. The four control transistors Q3t, Q3b, Q4t and Q4b in the gate drive circuit are modelled by the ideal switches. The inductance in the resonant gate drive circuit is first calculated as LG = 5.85 µH from Equations (6.72) and (6.73) and then an adjustment is made to remove the over voltage on the input capacitance at the MOSFET turn-on and the under voltage on the input capacitance at the MOSFET turn-off. The simulation waveforms are shown in Figure 6.33. They respectively show the waveforms of the MOSFETs Q3 and Q4 gate voltages and the inductor LG voltage and current. The simulation waveforms agree well with the waveforms in Figure 6.32 except that the zero inductor voltage intervals do not exist in this particular case. 20 20 Inductor LG Voltage vLG (V) MOSFET Q3 Gate Voltage vQ3G (V) 311 15 10 5 0 -5 -10 0 1 2 3 15 10 5 0 -5 -10 -15 -20 0 4 1 2 3 4 3 4 t (µs) 20 1 0.8 Inductor LG Current iLG (A) MOSFET Q4 Gate Voltage vQ4G (V) t (µs) 15 10 5 0.6 0.4 0.2 0 -0.2 0 -0.4 -0.6 -5 -0.8 -10 0 1 2 3 4 -1 0 t (µs) 1 2 t (µs) Figure 6.33 Simulation Waveforms of the Resonant Transition Gate Drive Figure 6.34 shows the experimental waveforms. The main components used in the resonant transition gate drive circuit are: • High side transistors Q3t and Q4t – P channel MOSFET International Rectifier IRLML5103, VDS = −30 V , I D = −0.76 A , R DS ( on ) = 0.60 Ω , QG ,t = 3.4 nC . • Low side transistors Q3b and Q4b – N channel MOSFET International Rectifier IRLML2803, QG ,b = 3.3 nC . V DS = 30 V , I D = 1.2 A , R DS ( on ) = 0.25 Ω , 312 200 mA (a) (c) (b) (d) Figure 6.34 Experimental Waveforms of the Resonant Transition Gate Drive (a) MOSFETs Q3t, Q3b and Q3 Gate Voltages (b) MOSFETs Q4t, Q4b and Q4 Gate Voltages (c) Inductor LG Current (d) MOSFETs Q3 and Q4 Drain Source Voltages • Inductor LG – Core type Philips ETD44 with 1.6-mm air gap in the centre leg, ferrite grade Philips 3F3, Litz wire made up of 34 strands of 0.11-mm 313 (0.135-mm overall diameter) wire, inductor winding N LG = 7 turns and LG = 6.98 µH , series dc plus ac resistance R LG = 0.99 Ω at 500 kHz. • MOSFETs Q3 and Q4 – ST STB50NE10, VDS = 100 V , I D = 50 A , R DS ( on ) = 0.027 Ω , C oss = 0.675 nF , R g = 1.5 Ω . The experimental waveforms match well with the simulation waveforms shown in Figure 6.33. From top to bottom, Figure 6.34(a) shows the gate voltage waveforms of Q3t, Q3b and Q3 and Figure 6.34(b) shows those of Q4t, Q4b and Q4. After turn-on of the control transistors in the gate drive circuit, an over voltage or under voltage appears on the gate waveforms of Q3 and Q4. This is caused by the voltage drop across the embedded reverse body diodes of the transistors. Figure 6.34(c) shows the current waveform in the inductor between the gates. When one of the MOSFETs Q3 and Q4 is fully on and the other is fully off, the inductor current linearly increases or decreases as the voltage across the inductor is a constant. Figure 6.34(d) shows the drain source voltage waveforms of Q3 and Q4 from top to bottom. The waveforms confirm that the two power MOSFETs Q3 and Q4 turn on at zero voltage. Table 6.2 shows the comparisons of the power consumptions in the resonant transition and the conventional gate drive circuits. The conventional gate drive circuit employs the regulating pulse width modulator – Unitrode UC3526A and the MOSFET driver – MAXIM MAX4429. 314 Power Resonant Transition Gate Drive Circuit Conventional Gate Drive Circuit Control Signal Generation (W) 0.66 0.72 Control Transistors and Power MOSFETs Driving (W) 0.72 2.75 Total (W) 1.38 3.47 Table 6.2 Power Consumptions in Two Gate Drive Circuits An estimated power loss breakdown for the MOSFET driving power loss in the resonant transition gate drive circuit using Equations (6.61) to (6.64) is given in Table 6.3. Component Power Loss (W) Inductor 0.22 Control Transistors Conduction 0.16 Power MOSFETs Gate Resistance 0.23 Control Transistors Driving 0.08 Total 0.69 Table 6.3 Resonant Transition Gate Drive Power Loss Breakdown In the estimation of the CV 2 loss of the four control transistors, in order to use the total gate charges of the control transistors instead of the gate input capacitances, Equation (6.64) is rewritten to: PQ 34 tb ,drive = 2(QG ,t + QG ,b )V DD f boost (6.74) 315 where QG,t and QG,b are respectively the total gate charges of the top and the bottom transistors. The calculated total power loss is 0.69 W and agrees favourably with the MOSFET driving power loss in the experiment. The size of the inductor used in the drive circuit is relatively large compared with that of the control transistors. Therefore, Newport Component 2200 series miniature axial lead inductors with high quality factors are used in the converter. This type of inductor has a body length of 10 mm and diameter of 4 mm. A series connection of two 1-µH and one 4.7-µH axial inductors are finally used in the drive circuit for the soft-switched current fed two-inductor boost converter, where Dboost = 0.615 under the operating point selected in Section 6.3.1. A slightly higher drive power of 0.83 W is observed. The control signals in both of the drive circuits are generated by the analogue circuitry and the control signal generation consumes the same level of power as that in the conventional gate drive circuit. However, compared with the conventional gate drive circuit, the resonant gate drive circuit saves around 2 W in driving the four control transistors and the two power MOSFETs and this improves the overall efficiency of a 100-W converter by around 2%. 6.3.3 Experimental Results In the practical implementation of the soft-switched current fed two-inductor boost 316 converter with the power rating of 100 W, the switching frequency of the buck stage MOSFETs fbuck and that of the boost stage MOSFETs fboost are respectively selected to be f buck = 250 kHz and f boost = 500 kHz . The arrangement for the buck conversion stage is the same as that in the hardswitched current fed two-inductor boost converter except that the switching timing of the two-phase buck converter is synchronised with the signal from a frequency divider, whose input is the gate signal for the MOSFETs in the two-inductor boost cell. The components used in the buck stage, the rectification stage of the boost cell and the unfolding stage are the same as those in the hard-switched current fed twoinductor boost converter. Other main components used in the converter are listed below: • Inductors L1 and L2 – Core type Ferroxube ETD29 with a 0.5-mm air gap in each of the two outer legs, ferrite grade Ferroxube 3F3, two inductor windings respectively on two outer legs, inductor winding N L = 20 turns. • Transformer T2 – Core type Ferroxube ETD29, ferrite grade Ferroxube 3F3, primary and secondary wires: Litz wires respectively made up 36 and 10 strands of 0.11-mm (0.135-mm overall diameter) wire, primary winding N p 2 = 5 turns, secondary winding N s 2 = 20 turns, leakage inductance reflected to the transformer T2 primary Lle = 0.25 µH . 317 • Additional resonant inductor – Core type air core toroidal, inductor wire: Litz wire made up 50 strands of 0.11-mm (0.135 mm overall diameter) wire, quality factor Q = 96 , 1.25 µH measured inductance. • Additional resonant capacitors – Cornell Dubilier surface mount mica capacitor MC22FA202J, 2 nF, V dc = 100 V , DF = 1 6000 at 500 kHz, 15 nF capacitance used. Figure 6.35 shows the buck converter waveforms under static tests. From top to bottom, Figures 6.35(a) and (b) respectively shows the waveforms of v1, v2 and vH with the duty ratio lower and greater than 50%. The voltage after the IPT swings between zero and the half input voltage when Dbuck < 50% while it swings between the half and the full input voltages when Dbuck > 50% . In both cases, the frequency of the voltage vH after the IPT is twice that of the voltage v1 or v2. Figure 6.36 shows the two-inductor boost converter output voltage vC and the input voltage vH from top to bottom with the sinusoidal modulation. A three-level modulation can be obviously observed in the vH waveform although the waveform displayed by the oscilloscope is heavily aliased. The screen of the oscilloscope has a limited number of pixels therefore only the envelope of the PWM waveform is evident and asymmetry exists in the displayed vH waveform. Figure 6.37 shows the gate waveforms of the low frequency unfolder switches and the output voltage vO from top to bottom. In this case a resistive load is supplied 318 and this is adjusted to give the rated power, 100 W average, at 240 V ac, which is equivalent to the nominal mains voltage. From top to bottom, Figure 6.38 shows the gate and drain source voltage waveforms of the MOSFETs in the ZVS two-inductor boost cell when the output voltage is close to its peak. The MOSFET drain source voltage waveforms confirm that the MOSFETs turn on at zero voltage. Figure 6.39 shows the voltage across the diode in the voltage-doubler rectifier when the output voltage is close to its peak. The waveform is relatively clean. No reverse recovery can be seen in the SiC Schottky diodes although some lower frequency oscillations with an approximate 200-ns period can be seen. These are due to the resonance between the diode junction capacitance and the inductance in series with the transformer T2 secondary winding including the leakage inductance and the additional resonant inductance referred to the secondary. In the soft-switched current fed two-inductor boost converter, a conversion efficiency of 91% at the rated power rating of 100 W was obtained. Both the input and the output powers were measured with the same equipment as in the hardswitched current fed two-inductor boost converter. 319 (a) (b) Figure 6.35 Experimental Waveforms in the Two-Phase Buck Converter (a) Dbuck < 50% (b) Dbuck > 50% 320 100V Figure 6.36 Experimental Waveforms of the Sinusoidal Modulation 250V Figure 6.37 Experimental Waveforms in the Unfolder 321 Figure 6.38 Experimental Waveforms in the Two-Inductor Boost Cell 100V Figure 6.39 Experimental Waveform of the Diode Voltage 322 A photo of the prototype soft-switched current fed two-inductor boost converter is shown in Figure 6.40. Like the hard-switched current fed two-inductor boost converter, this converter had not been operated in a grid interactive mode at the time of writing and this is an area of future work. Figure 6.40 Photo of the Soft-Switched Current Fed Two-Inductor Boost Converter 6.4 Summary In this chapter, the MIC implementations employing the two-inductor boost topology with an unfolding stage are discussed. Both of the hard-switched and the soft-switched forms of the two-inductor boost converter are developed. In the hardswitched current fed two-inductor boost converter, non-dissipative snubbers are analysed in detail while in the soft-switched current fed two-inductor boost 323 converter, the resonant transition gate drive circuit is thoroughly investigated. The hard-switched and the soft-switched current fed two-inductor boost converters have respectively achieved 92% and 91% efficiency at the rated power rating of 100 W.