A High-Speed Gate Driver with PCB-Embedded Rogowski Switch-Current Sensor for a 10 kV, 240 A, SiC MOSFET Module Jun Wang, Slavko Mocevic, Yue Xu, Christina DiMarino, Rolando Burgos, Dushan Boroyevich Center for Power Electronics Systems Virginia Polytechnic Institute and State University Blacksburg, VA, USA [email protected] Abstract—High-voltage SiC MOSFET modules are revolutionizing modern high power electronics owing to their high blocking voltage, low conduction resistance, and fast switching frequency. A 10 kV, 240 A SiC MOSFET module has recently become a candidate to build medium-voltage converters. The MOSFET module comprises three independent submodules that can be conﬁgured as three phase-legs, or one half-bridge by paralleling. To maximize its performance, this paper presents a smart gate driver design for this particular semiconductor device. The design concentrates on a high-current booster stage and a high-bandwidth PCB-embedded Rogowski switch-current sensors for the paralleled submodules. The PCB layout has satisﬁed high-voltage clearance and creepage standards. Finally, the booster current sharing and RSCS performance have been experimentally validated. Index Terms—10 kV SiC MOSFET, smart gate driver, paralleled current boosters, Rogowski switch-current sensor I. I NTRODUCTION Owing to the booming technology of wide-bandgap (WBG) semiconductor devices and packaging, silicon-carbide (SiC) MOSFETs have demonstrated their superior performance to Si IGBTs in terms of higher breakdown voltage, faster switching speed, lower switching loss and higher operating temperature  . The high blocking voltage of SiC MOSFETs simpliﬁes converter power stage by using uncomplicated topologies, and meanwhile their high switching frequency preserves the overall harmonic performance despite of reduced number of voltage levels. Recently, Wolfspeed has developed a 10 kV, 240 A SiC MOSFET module XHV-6, which uses their 3rdgeneration 10 kV, 350 mΩ SiC MOSFETs  with an improved package layout . This device is suitable to construct converters such as a 6∼7 kV dc, 3.3 kV ac motor drive by using a simple three-phase two-level topology. In this research work, the device serves as a critical component in a power electronics building block rated at 6 kV dc bus voltage (PEBB6000) as shown in Fig. 1 . The power-stage topology is an H-bridge that consists of two XHV-6 modules. The three submodules of each module are paralleled by internal jumpers within the device package. This material is based upon research supported by the U.S. Ofﬁce of Naval Research under award number N00014-16-1-2939. 978-1-4799-7312-5/18/$31.00 ©2018 IEEE Fig. 1. PEBB6000 system architecture diagram. As seen in Fig. 1, four gate drivers are needed to drive the four SiC MOSFET switches in two XHV-6 modules. Gate driver is the critical interface between power semiconductor devices and control signals. It serves to provide galvanic isolation and to supply driving current while maintaining signal integrity under high-noise environment. For the XHV6 module, three submodules that contain 18 10 kV, 350 mΩ SiC MOSFET dies need to be driven simultaneously. The driving current magnitude, driving signal synchronization, driving loop parasitics, and common-mode noises become big challenges. On top of those basic tasks, a gate driver can also provide quick, reliable, and conﬁgurable protections, as well as advanced switch-current signal sensing, digital data processing, and active gate controllability, which deﬁne a “smart” gate driver. Taking those factors into consideration, Table. I summarizes the speciﬁcations and design objectives of the gate driver for the XHV-6 module. 5489 Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply. TABLE I S MART G ATE D RIVER S PECIFICATIONS Property Minimum Maximum Supply voltage Driving voltage dv/dt immunity Switching frequency Isolation voltage Driving current External gate resistors Driver IC over-temperature Under-voltage lockout Active Miller clamp Conﬁgurable short-circuit threshold Two-level turn-off 24 V −8 V 20 kV 0.53 Ω 150◦ C 11 V 5 A, VEE + 2 V 400 A 7 V, 0.5 μs 30 V +20 V 100 V/ns 100 kHz 90 A 200◦ C 14 V 15 A, 800 A 10 V, 1.5 μs Fig. 2. Smart gate driver power architecture for XHV-6 SiC MOSFET module. There have been a few research efforts published regarding gate drivers for SiC MOSFETs of no less than 10 kV. Wolfspeed has fabricated a gate driver evaluation board and corresponding gate driver power supply to demonstrate how the XHV-6 module can be driven . The gate driver board has two pairs of ﬁber-optic transceivers to realize signal isolation. It connects to XHV-6 module’s MCX gate connectors via coaxial cables. This design allows for ﬂexible connections even if the driver board is mounted in distance from the XHV6 module, nonetheless, the gate-loop inductance is still tens of nanohenry because of the long coaxial cables. The corresponding gate driver power supply is a voltage-transformer-based converter, and as such the distance between the transformer’s input and output interfaces has to meet clearance and creepage standards. That results in an a large size of the gate driving system. -  have presented similar designs with even lower driving current magnitude. Another type of gate driving system supplied by a current source has been demonstrated in  and , where a high-voltage current-source cable is leveraged to achieve high insulation and isolation strength. Wireless  and ﬁber-optic  power transfer techniques are also proposed to serve the same purposes, but the system density and power ratings are still limited. In the literature review, the HV gate driving system designs are typically partitioned into the HV gate driver design and HV power supply design. Both designs are pursuing greater performance and lower proﬁle. For the driving system, the gate driver board is grounded on the MOSFET source, and the HV isolation is realized by the power supply that feeds the gate drivers. This paper only concentrates on the gate driver design that includes its system architecture, noise-immunity design, current boosters, as well as the RSCS and the digital processor that bring the intelligence. II. G ATE D RIVER P OWER AND S IGNAL A RCHITECTURE A. Power architecture A well planned gate driver architecture design is able to bypass common-mode (CM) noise current away from sensitive components. This is even more critical for a smart gate driver ! " " Fig. 3. Gate driver signal architecture for XHV-6 SiC MOSFET module. as a large amount of analog and digital signals are processed on the board. Tens of millivolt noise voltage is high enough to cause inaccurate sensing. The design refers to the analysis and follows the solution that have been published in . As shown in Fig. 2, for each gate driver channel, two isolated ground planes have been designed. On the green plane, most of signal processing components and logic units with voltages at ±5 V, 3.3 V, and 1.2 V are located. On the red plane, the components designed for providing driving current and voltage at +20 V and −5 V are placed. The components on the red plane are much less sensitive than those on the green, so it is preferred that the CM noise current primarily ﬂows through red plane to the input power connector at the high side. The CM impedance of the red ground path is dominated by a few nanohenry trace inductance, whereas the CM impedance of the green ground path is determined by several picofarad inputoutput capacitance of isolated power supplies, the gate driver 5490 Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply. Fig. 6. Current sharing test of three current booster banks. Fig. 4. Paralleled current booster circuit diagram for three submodules. Fig. 5. PCB layout of the paralleled current boosters designed for minimized parasitics. IC, and digital isolators. The CM impedance of the green path is more than 10× higher than the red. Hence, the major part of CM noise current will ﬂow through the red plane instead of the green, so that the sensitive circuits will be subjected to greatly mitigated conductive noises. The Rogowski switchcurrent sensor (RSCS) for SiC MOSFET drain current sensing is also labeled in Fig. 2. The coupling capacitance between the primary-side copper bus-bar and the secondary-side coil is less than 2 pF, so the noise current introduced by the RSCS is negligible. B. Signal architecture A FPGA manages gate driver IC programming, RSCS reset, analog/digital conversion (ADC), and communication to other units. Detailed functionalities are shown in Fig. 3. The Rogowski coils are connected to the driver board via the three-pin header at the bottom-right. The coil output signals are processed by an operational ampliﬁer (OpAmp), and then given to functional blocks of over-current (OC) and shortcircuit (SC) with different RC ﬁltering. Three channels of the OC that correspond to three submodules are combined by an “OR” gate, and sent to the FPGA for post-fault reaction. SC signals are combined by a “OR” gate, and then fed to the gate driver IC (GDIC) via a digital isolator (D-Iso). The GDIC will activate short-circuit protection immediately. On the other hand, the SC signals of three channels notify the FPGA about the fault status, respectively. Since the RSCS serves as a current-based SC detector, the submodules where the SC fault occurs can be identiﬁed. Three current sensor outputs are fed to three ADC blocks via buffers. The ADC blocks sample three switch currents as commanded by the FPGA for control purposes. The sensors also receive signals. The FPGA must reset (RST) the sensor OpAmp every switching period to avoid dc drift. Manually calibrating the sensor’s steady-state dc offset value to zero is always a huge effort. Accordingly, an automatic start-up calibration is proposed on the gate driver. The FPGA senses the off-state current via the ADC, and adjust the resistance value of a digital potentiometer (DPM) until the value sensed by the ADC drops below a very low threshold. Besides the above-mentioned tasks, the FPGA also needs memory (MEM), external clock (CLK), and LED indicators. It initializes and conﬁgures the GDIC every time when the gate driver board is powered on. Overall, 35 out of 38 FPGA I/Os have been used. III. PARALLELED C URRENT B OOSTERS STMicro STGAP1AS is selected as the main gate driver IC based on a previous trade-off . This driver IC is not able to provide enough driving current for the three paralleled submodules. Therefore, external current boosters are designed to supply 90 A peak current to sustain the fastest switching transient. A current booster solution with nine paralleled bipolar junction transister (BJT) have been proposed and designed as shown in Fig. 4. The three driving channels are connected jointly at the common junction ”COM” to guarantee the three driving voltage is the same. Rg,com is used to balance the current sharing of the nine current booster channels, and to compensate the mismatched transconductance between the 5491 Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply. Fig. 7. Rogowski switch-current sensor (RSCS) fundamentals Fig. 8. Frequency-domain analysis of RSCS Fig. 9. Time-domain analysis of RSCS BJTs. Rg1,ext and Rg2,ext are split gate resistors to damp the resonance between the three paralleled gate loops. Rg1,ext determines the turn-on speed, while Rg1,ext and Rg2,ext jointly determine the turn-off speed. Fig. 5 shows the PCB layout of the current boosters. Three current-booster banks are placed in a wide area adjacent to a MCX gate/source connector. BJT ICs, decoupling capacitors, gate resistors, and internal power/ground planes are laminated at the same area to ensure extremely low turn-on and turn-off gate loop inductance. The current sharing test results of three current booster banks are shown in Fig. 6. The gate driving currents of submodule A, B and C have been obtained by measuring the across voltages of three gate resistors Rg,ext , using passive probes referred to the joint point “COM” as the ground. The three gate currents are almost overlapped with one another, presenting the total turn-on current peak of 36 A, and the total turn-off peak current of 48 A. IV. ROGOWSKI S WITCH -C URRENT S ENSOR A Rogowski switch-current sensor (RSCS) has been proposed to work effectively together with SiC MOSFET modules  . The high bandwidth, wide measurement range, good accuracy, and solid signal isolation make it an excellent shortcircuit current detector for SiC devices. As depicted in Fig. 7, a RSCS mainly comprises two parts. The ﬁrst part is a Rogowski coil that is a high-load-impedance current transform, and equivalently performs as an inductor with the value of mutual inductance. Fig. 13 shows that a one-turn conductor current that ﬂows out of the orange window as annotated by the red arrow generates a ﬂux, and the coil couples the ﬂux along with the orange trace. A did /dt voltage scaled by the mutual inductance M is induced at the terminal of the coil where id is the MOSFET drain current. For the HV design, the coils are embedded in the inner four layers of the PCB, constructed by buried traces and vias, and not exposed to the surface. This design eliminates creepage paths between the high-voltage primary-side conductor and the secondary-side coil, especially for the high-side switch current measurement. The second part of the RSCS is a group of signal processing circuits that include an active integrator circuit, a reset switch, and a proper signal ﬁlter, shown in Fig. 7. The active integrator converts the M did /dt value back to id . Fig.. 8 shows the frequency-domain characteristics of the RSCS. The Rogowski coil is fundamentally an inductor whose impedance increases with frequency at a +20 dB/dec slope, before reaching the double-pole caused by the leakage inductance and equivalent paralleled capacitance (EPC). The active integrator is basically a capacitor whose impedance droops at −20 dB/dec. The non-ideal characteristics of the OpAmp yield a limited dc gain. The overall RSCS transfer function vsen /id 5492 Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply. Fig. 10. Gate driver layout plan Fig. 12. Side-view of the gate driver prototype. Fig. 11. Assembled gate driver prototype including device module, two gate driver boards and one Rogowski coil board. V. G ATE D RIVING S YSTEM L AYOUT AND P ROTOTYPE is depicted by the green dashed line. It is a bandpass ﬁlter with high-frequency bandwidth brought by the parasitics, and the low-frequency bandwidth caused by the OpAmp. Accordingly, the time-domain study in Fig. 9 indicates that the green dashed waveform looses the correct dc offset value compared to the switch current id in red. To tackle the problem, a bi-directional analog switch labeled in orange is added to reset the integrator cycle-by-cycle when the SiC MOSFET is not conducting, ensuring that the initial value of the integration is zero at each cycle. By this means, the RSCS is able to measure the dc component of the switch current. The gate driver boards layout plan is shown in Fig. 10. The voltage input connector and power management unit are arranged to the left end. Three identical component banks are designed on the top of the XHV-6 submodules. Each submodule has its own current booster, analog and digital signal processing circuit. The ﬁber-optic transceivers, FPGA and the driver IC are assigned at the remaining spaces. The prototype of a phase-leg gate driving system is shown in Fig. 11, which consists of one 10 kV XHV-6 module, two gate driver boards, and one Rogowski coil board. Each gate driver board is plugged perpendicularly into the XHV-6 module via 5493 Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply. Fig. 14. Comparison between RSCS and commercial Rogowski probe on submodule A in double-pulse test: Rg,eqv = 1 Ω, Vdc = 6 kV, id of f,A = 40 A (120 A total), id on,A = 80 A (240 A total), turn-off dv/dt = 50 V/ns, turn-on di/dt = 2.4 A/ns. Fig. 13. Experiment setup for double-pulse test three MCX connectors, and plugged into the Rogowski coil board with three three-pin headers. The side-view in Fig. 12 shows that the drivers boards are physically paralleled to each other with a distance of about 20 mm, satisfying the clearance distance requirement in IEC 60664-1 (3.5 mm for 10 kV, 8 mm for 20 kV) . VI. E XPERIMENTAL VALIDATION Double-pulse test (DPT) has been conducted to validate the MOSFET switching behavior and the smart gate driver performance. The test diagram is shown in Fig. 14. A halfbridge circuit, a load inductor, and the driving system is connected. The RSCS output is connected to the non-inverting input pin of a high-speed comparator. The measured currents by the RSCS (in red) and by a commercial Rogowski probe (in red) indicate excellent agreements even at 6 kV, 40 A per submodule, and a maximum of 50 V/ns dv/dt rate. Other test conditions are listed in the ﬁgure caption. C ONCLUSIONS The paper has demonstrated the critical design considerations and solutions of the gate driver for a 10 kV, 240 A, SiC MOSFET module. The design results successfully validate the high-amplitude but balanced current boosters, as well as the high-bandwidth-and-accuracy Rogowski switchcurrent sensor. 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