A High-Speed Gate Driver with PCB-Embedded Rogowski Switch-Current Sensor for a 10 kV 240 A SiC MOSFET Module

A High-Speed Gate Driver with PCB-Embedded
Rogowski Switch-Current Sensor for a 10 kV, 240
A, SiC MOSFET Module
Jun Wang, Slavko Mocevic, Yue Xu, Christina DiMarino, Rolando Burgos, Dushan Boroyevich
Center for Power Electronics Systems
Virginia Polytechnic Institute and State University
Blacksburg, VA, USA
[email protected]
Abstract—High-voltage SiC MOSFET modules are revolu-
tionizing modern high power electronics owing to their high
blocking voltage, low conduction resistance, and fast switching
frequency. A 10 kV, 240 A SiC MOSFET module has recently
become a candidate to build medium-voltage converters. The
MOSFET module comprises three independent submodules that
can be configured as three phase-legs, or one half-bridge by
paralleling. To maximize its performance, this paper presents
a smart gate driver design for this particular semiconductor
device. The design concentrates on a high-current booster stage
and a high-bandwidth PCB-embedded Rogowski switch-current
sensors for the paralleled submodules. The PCB layout has
satisfied high-voltage clearance and creepage standards. Finally,
the booster current sharing and RSCS performance have been
experimentally validated.
Index Terms—10 kV SiC MOSFET, smart gate driver, paral-
leled current boosters, Rogowski switch-current sensor
I. INTRODUCTION
Owing to the booming technology of wide-bandgap (WBG)
semiconductor devices and packaging, silicon-carbide (SiC)
MOSFETs have demonstrated their superior performance to Si
IGBTs in terms of higher breakdown voltage, faster switching
speed, lower switching loss and higher operating temperature
[1] [2]. The high blocking voltage of SiC MOSFETs simplifies
converter power stage by using uncomplicated topologies,
and meanwhile their high switching frequency preserves the
overall harmonic performance despite of reduced number of
voltage levels. Recently, Wolfspeed has developed a 10 kV,
240 A SiC MOSFET module XHV-6, which uses their 3rd-
generation 10 kV, 350 mΩSiC MOSFETs [1] with an im-
proved package layout [3]. This device is suitable to construct
converters such as a 6∼7 kV dc, 3.3 kV ac motor drive
by using a simple three-phase two-level topology. In this
research work, the device serves as a critical component in a
power electronics building block rated at 6 kV dc bus voltage
(PEBB6000) as shown in Fig. 1 [4]. The power-stage topology
is an H-bridge that consists of two XHV-6 modules. The three
submodules of each module are paralleled by internal jumpers
within the device package.
This material is based upon research supported by the U.S. Office of Naval
Research under award number N00014-16-1-2939.
Fig. 1. PEBB6000 system architecture diagram.
As seen in Fig. 1, four gate drivers are needed to drive
the four SiC MOSFET switches in two XHV-6 modules. Gate
driver is the critical interface between power semiconductor
devices and control signals. It serves to provide galvanic
isolation and to supply driving current while maintaining
signal integrity under high-noise environment. For the XHV-
6 module, three submodules that contain 18 10 kV, 350
mΩSiC MOSFET dies need to be driven simultaneously.
The driving current magnitude, driving signal synchronization,
driving loop parasitics, and common-mode noises become big
challenges. On top of those basic tasks, a gate driver can
also provide quick, reliable, and configurable protections, as
well as advanced switch-current signal sensing, digital data
processing, and active gate controllability, which define a
“smart” gate driver. Taking those factors into consideration,
Table. I summarizes the specifications and design objectives
of the gate driver for the XHV-6 module.
978-1-4799-7312-5/18/$31.00 ©2018 IEEE 5489
Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply.

TABLE I
SMART GAT E DRIVER SPECIFICATIONS
Property Minimum Maximum
Supply voltage 24 V30 V
Driving voltage −8V+20 V
dv/dt immunity - 100 V/ns
Switching frequency - 100 kHz
Isolation voltage 20 kV -
Driving current - 90 A
External gate resistors 0.53 Ω -
Driver IC over-temperature 150◦C200◦C
Under-voltage lockout 11 V14 V
Active Miller clamp 5A, VEE +2 V15 A, -
Configurable short-circuit threshold 400 A800 A
Two-level turn-off 7V, 0.5μs10 V, 1.5μs
There have been a few research efforts published regarding
gate drivers for SiC MOSFETs of no less than 10 kV.
Wolfspeed has fabricated a gate driver evaluation board and
corresponding gate driver power supply to demonstrate how
the XHV-6 module can be driven [5]. The gate driver board has
two pairs of fiber-optic transceivers to realize signal isolation.
It connects to XHV-6 module’s MCX gate connectors via
coaxial cables. This design allows for flexible connections
even if the driver board is mounted in distance from the XHV-
6 module, nonetheless, the gate-loop inductance is still tens of
nanohenry because of the long coaxial cables. The correspond-
ing gate driver power supply is a voltage-transformer-based
converter, and as such the distance between the transformer’s
input and output interfaces has to meet clearance and creepage
standards. That results in an a large size of the gate driving
system. [6]- [8] have presented similar designs with even lower
driving current magnitude. Another type of gate driving system
supplied by a current source has been demonstrated in [9] and
[10], where a high-voltage current-source cable is leveraged
to achieve high insulation and isolation strength. Wireless
[11] and fiber-optic [12] power transfer techniques are also
proposed to serve the same purposes, but the system density
and power ratings are still limited.
In the literature review, the HV gate driving system designs
are typically partitioned into the HV gate driver design and
HV power supply design. Both designs are pursuing greater
performance and lower profile. For the driving system, the gate
driver board is grounded on the MOSFET source, and the HV
isolation is realized by the power supply that feeds the gate
drivers. This paper only concentrates on the gate driver design
that includes its system architecture, noise-immunity design,
current boosters, as well as the RSCS and the digital processor
that bring the intelligence.
II. GATE DRIVER POWER AND SIGNAL ARCHITECTURE
A. Power architecture
A well planned gate driver architecture design is able to
bypass common-mode (CM) noise current away from sensitive
components. This is even more critical for a smart gate driver
Fig. 2. Smart gate driver power architecture for XHV-6 SiC MOSFET module.
"
"
!
Fig. 3. Gate driver signal architecture for XHV-6 SiC MOSFET module.
as a large amount of analog and digital signals are processed
on the board. Tens of millivolt noise voltage is high enough
to cause inaccurate sensing. The design refers to the analysis
and follows the solution that have been published in [13]. As
shown in Fig. 2, for each gate driver channel, two isolated
ground planes have been designed. On the green plane, most
of signal processing components and logic units with voltages
at ±5 V, 3.3 V, and 1.2 V are located. On the red plane, the
components designed for providing driving current and voltage
at +20 V and −5 V are placed. The components on the red
plane are much less sensitive than those on the green, so it is
preferred that the CM noise current primarily flows through
red plane to the input power connector at the high side. The
CM impedance of the red ground path is dominated by a few
nanohenry trace inductance, whereas the CM impedance of the
green ground path is determined by several picofarad input-
output capacitance of isolated power supplies, the gate driver
5490
Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply.

Fig. 4. Paralleled current booster circuit diagram for three submodules.
Fig. 5. PCB layout of the paralleled current boosters designed for minimized
parasitics.
IC, and digital isolators. The CM impedance of the green path
is more than 10×higher than the red. Hence, the major part
of CM noise current will flow through the red plane instead
of the green, so that the sensitive circuits will be subjected
to greatly mitigated conductive noises. The Rogowski switch-
current sensor (RSCS) for SiC MOSFET drain current sensing
is also labeled in Fig. 2. The coupling capacitance between
the primary-side copper bus-bar and the secondary-side coil is
less than 2 pF, so the noise current introduced by the RSCS
is negligible.
B. Signal architecture
A FPGA manages gate driver IC programming, RSCS
reset, analog/digital conversion (ADC), and communication
to other units. Detailed functionalities are shown in Fig. 3.
The Rogowski coils are connected to the driver board via the
three-pin header at the bottom-right. The coil output signals
are processed by an operational amplifier (OpAmp), and then
given to functional blocks of over-current (OC) and short-
circuit (SC) with different RC filtering. Three channels of
Fig. 6. Current sharing test of three current booster banks.
the OC that correspond to three submodules are combined by
an “OR” gate, and sent to the FPGA for post-fault reaction.
SC signals are combined by a “OR” gate, and then fed to
the gate driver IC (GDIC) via a digital isolator (D-Iso). The
GDIC will activate short-circuit protection immediately. On
the other hand, the SC signals of three channels notify the
FPGA about the fault status, respectively. Since the RSCS
serves as a current-based SC detector, the submodules where
the SC fault occurs can be identified. Three current sensor
outputs are fed to three ADC blocks via buffers. The ADC
blocks sample three switch currents as commanded by the
FPGA for control purposes.
The sensors also receive signals. The FPGA must reset
(RST) the sensor OpAmp every switching period to avoid
dc drift. Manually calibrating the sensor’s steady-state dc
offset value to zero is always a huge effort. Accordingly, an
automatic start-up calibration is proposed on the gate driver.
The FPGA senses the off-state current via the ADC, and adjust
the resistance value of a digital potentiometer (DPM) until the
value sensed by the ADC drops below a very low threshold.
Besides the above-mentioned tasks, the FPGA also needs
memory (MEM), external clock (CLK), and LED indicators.
It initializes and configures the GDIC every time when the
gate driver board is powered on. Overall, 35 out of 38 FPGA
I/Os have been used.
III. PARALLELED CURRENT BOOSTERS
STMicro STGAP1AS is selected as the main gate driver
IC based on a previous trade-off [13]. This driver IC is
not able to provide enough driving current for the three
paralleled submodules. Therefore, external current boosters
are designed to supply 90 A peak current to sustain the
fastest switching transient. A current booster solution with nine
paralleled bipolar junction transister (BJT) have been proposed
and designed as shown in Fig. 4. The three driving channels are
connected jointly at the common junction ”COM” to guarantee
the three driving voltage is the same. Rg,com is used to balance
the current sharing of the nine current booster channels, and
to compensate the mismatched transconductance between the
5491
Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply.

Fig. 7. Rogowski switch-current sensor (RSCS) fundamentals
Fig. 8. Frequency-domain analysis of RSCS
BJTs. Rg1,ext and Rg2,ext are split gate resistors to damp
the resonance between the three paralleled gate loops. Rg1,ext
determines the turn-on speed, while Rg1,ext and Rg2,ext jointly
determine the turn-off speed. Fig. 5 shows the PCB layout of
the current boosters. Three current-booster banks are placed
in a wide area adjacent to a MCX gate/source connector.
BJT ICs, decoupling capacitors, gate resistors, and internal
power/ground planes are laminated at the same area to ensure
extremely low turn-on and turn-off gate loop inductance.
The current sharing test results of three current booster
banks are shown in Fig. 6. The gate driving currents of
submodule A, B and C have been obtained by measuring the
across voltages of three gate resistors Rg,ext, using passive
probes referred to the joint point “COM” as the ground. The
three gate currents are almost overlapped with one another,
presenting the total turn-on current peak of 36 A, and the
total turn-off peak current of 48 A.
IV. ROGOWSKI SWITCH-CURRENT SENSOR
A Rogowski switch-current sensor (RSCS) has been pro-
posed to work effectively together with SiC MOSFET modules
[14] [15]. The high bandwidth, wide measurement range, good
accuracy, and solid signal isolation make it an excellent short-
circuit current detector for SiC devices. As depicted in Fig. 7, a
RSCS mainly comprises two parts. The first part is a Rogowski
Fig. 9. Time-domain analysis of RSCS
coil that is a high-load-impedance current transform, and
equivalently performs as an inductor with the value of mutual
inductance. Fig. 13 shows that a one-turn conductor current
that flows out of the orange window as annotated by the red
arrow generates a flux, and the coil couples the flux along
with the orange trace. A did/dt voltage scaled by the mutual
inductance Mis induced at the terminal of the coil where id
is the MOSFET drain current. For the HV design, the coils
are embedded in the inner four layers of the PCB, constructed
by buried traces and vias, and not exposed to the surface. This
design eliminates creepage paths between the high-voltage
primary-side conductor and the secondary-side coil, especially
for the high-side switch current measurement. The second part
of the RSCS is a group of signal processing circuits that
include an active integrator circuit, a reset switch, and a proper
signal filter, shown in Fig. 7. The active integrator converts the
Mdid/dt value back to id.
Fig.. 8 shows the frequency-domain characteristics of the
RSCS. The Rogowski coil is fundamentally an inductor whose
impedance increases with frequency at a +20 dB/dec slope,
before reaching the double-pole caused by the leakage induc-
tance and equivalent paralleled capacitance (EPC). The active
integrator is basically a capacitor whose impedance droops at
−20 dB/dec. The non-ideal characteristics of the OpAmp yield
a limited dc gain. The overall RSCS transfer function vsen/id
5492
Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply.

Fig. 10. Gate driver layout plan
Fig. 11. Assembled gate driver prototype including device module, two gate
driver boards and one Rogowski coil board.
is depicted by the green dashed line. It is a bandpass filter with
high-frequency bandwidth brought by the parasitics, and the
low-frequency bandwidth caused by the OpAmp. Accordingly,
the time-domain study in Fig. 9 indicates that the green dashed
waveform looses the correct dc offset value compared to the
switch current idin red. To tackle the problem, a bi-directional
analog switch labeled in orange is added to reset the integrator
cycle-by-cycle when the SiC MOSFET is not conducting,
ensuring that the initial value of the integration is zero at each
cycle. By this means, the RSCS is able to measure the dc
component of the switch current.
Fig. 12. Side-view of the gate driver prototype.
V. G ATE DRIVING SYSTEM LAYOUT AND PROTOTYPE
The gate driver boards layout plan is shown in Fig. 10.
The voltage input connector and power management unit are
arranged to the left end. Three identical component banks
are designed on the top of the XHV-6 submodules. Each
submodule has its own current booster, analog and digital
signal processing circuit. The fiber-optic transceivers, FPGA
and the driver IC are assigned at the remaining spaces.
The prototype of a phase-leg gate driving system is shown in
Fig. 11, which consists of one 10 kV XHV-6 module, two gate
driver boards, and one Rogowski coil board. Each gate driver
board is plugged perpendicularly into the XHV-6 module via
5493
Authorized licensed use limited to: INP TOULOUSE. Downloaded on September 26,2021 at 21:20:31 UTC from IEEE Xplore. Restrictions apply.