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publicité
5
4
3
2
1
D
D
Berry DG15 Discrete/UMA Schematics Document
Arrandale
Intel PCH
C
C
2010-02-03
REV : A00
DY :None Installed
UMA:UMA platform installed
PARK:DIS PARK platform installed
M96:DIS M96 platform installed
VRAM_1G:VRAM 128M*16 installed
Colay :Manual modify BOM
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Cover Page
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
1
of
92
5
4
D
VRAM
1GB/512MB
DDR3
800MHz
Intel CPU
Arrandale
PCIe x 16
CPU DC/DC
DDRIII 800/1066 Channel B
(Discrete only)
OUTPUTS
+PWR_SRC
+VCC_CORE
DDRIII
800/1066
Slot 0
DDRIII
800/1066
Slot 1
18
OUTPUTS
+PWR_SRC
+1.05V_VTT
C
Discreet/UMA Co-lay
PCIE x 1
OUTPUTS
+5V_ALW2
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
+15V_ALW
SYSTEM DC/DC
19
57
54
RGB CRT
PCIE x 3
HM57
14 USB 2.0/1.1 ports
CRT
SATA x 1
ETHERNET (10/100/1000Mb)
77
Left Side:
USB x 2
10/100 NIC
RJ45
CONN
SATAx1 / USB2.0x1
PCIE x 1,USB x 1
ESATA/USB
Combo
+PWR_SRC
+CPU_GFX_CORE
VGA
89
76
OUTPUTS
+VGA_CORE
TI CHARGER
SIM
INPUTS
OUTPUTS
+DC_IN
+PBATT
+PWR_SRC
Right Side:
USB x 1
SYSTEM DC/DC
54
USB 2.0 x 1
OUTPUTS
+3.3V_ALW
+1.8V_RUN
+1.8V_RUN_VGA
Realtek
RTS5159
AZALIA
B
SYSTEM DC/DC
CardReader
20,21,22,23,24,25,26,27,28
51
APL5930
INPUTS
ACPI 1.1
PCI/PCI BRIDGE
45
BQ24745
Mini-Card
WWAN
USB 2.0 x 1
C
OUTPUTS
+PWR_SRC
LPC I/F
USB2.0 x 4
B
CAMERA
53
INPUTS
INPUTS
USB 2.0 x 4
SATA ports (6)
73
+1.5V_SUS
+0.75V_DDR_VTT
+V_DDR_REF
SYSTEM DC/DC
802.11a/b/g
26
PCIE ports (8)
Bluetooth
Mini-Card
High Definition Audio
CRT Board
OUTPUTS
RT8208B
Intel
PCH
LVDS(Dual Channel)
LCD
50
TPS51116
Realtek
RTL8103T-VB
Level 57
shifter
I/O Board
Connector
HDMI
HDMI
46
RT8205B
TPS51611
DMIx4
D
SYSTEM DC/DC
+PWR_SRC
PCIE x 1
USB x 1
49
TPS51218
INPUTS
+PWR_SRC
8,9,10,11,12,13,14
FDIx4x2
(UMA only)
39
SYSTEM DC/DC
INPUTS
80,81,82,83,84
47
ISL62883
INPUTS
INPUTS
DDRIII 800/1066 Channel A
Park-XT
(Discrete only)
7
1
Project code : 91.4HH01.001
PCB P/N
: 48.4HH01.0SA
Revision
: 09909-1
4
85,86,87,88
AMD Graphic
Clock Generator
SLG8SP585
2
Berry Block Diagram
(Discrete/UMA co-lay)
##OnMainBoard
1.Park-XT;512MB
(64Mx16b*4)
Dell P/N:9TGTN$AA HYNIX
Dell P/N:C995R$AA SAMSUNG
2.Park-XT;1GB (128Mx16b*4)
Dell P/N:PXFYJ$AA HYNIX
Dell P/N:C09DT$AA SAMSUNG
(1 and 2 co-lay)
3
SD/MMC+/MS/
MS Pro/xD
78
90
APL5930
INPUTS
26
OUTPUTS
+1.5V_SUS
+1.0V_RUN_VGA
Switches
HP1
MIC IN
Azalia
CODEC
Flash ROM
4MB 62
IDT
92HD79B1
SATA x 2
LPC Bus
Internal Analog MIC
SPI
INPUTS
+1.5V_SUS
+5V_ALW
+3.3V_ALW
HDD
59
LPC debug port
59
L1:Top
L2:VCC
L3:Signal
L4:Signal
L5:GND
L6:Bottom
30
KBC
SPI
SMBus
NUVOTON
A
NPCE781BA0DX
+1.5V_RUN
+5V_RUN
+3.3V_RUN
PCB LAYER
ODD
70
OUTPUTS
<Core Design>
A
37
Wistron Corporation
2CH SPEAKER
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Flash ROM
256kB 62
Touch
PAD
Main:G7922
Sec.EMC2102
Fan
58
http://laptop-motherboard-schematic.blogspot.com/
68
5
Title
Thermal
Int.
KB
4
68
Size
A3
2539
3
2
Date:
Block Diagram
Document Number
Rev
A00
Berry
W ednesday, February 10, 2010
Sheet
1
2
of
92
5
4
3
+VGA_CORE
RT8208B
2
1
+1.0V_RUN_VGA
For Discrete
APL5930KAI
D
D
+PWR_SRC
Adapter
TPS51116
ISL62883
TPS51218
TPS51611
+V_DDR_REF
AO4407A
+0.75V_DDR_VTT
+1.5V_SUS
Charger
+VCC_CORE
BQ24745
+CPU_GFX_CORE
+1.05V_VTT
AO4468
For UMA
+PBATT
Battery
+1.5V_RUN
RT8205B
For Discrete
C
+15V_ALW
+3.3V_RTC_LDO
SI2301CDS
+KBC_PWR
+5V_ALW2
+5V_ALW
UP7534BRA8
AO4468
UP7534BRA8
+5V_USB1
+5V_RUN
+5V_USB2
I/O Board USB Power
+1.5V_RUN_CPU
C
+3.3V_ALW
AO4468
+3.3V_RUN
PA102FMG
APL5930KAI
+3.3V_RUN_VGA
+3.3V_LAN
+1.8V_RUN
For Discrete
CRT Board USB Power
RT9198-33PBG
APL5930KAI
SI3456BD
RTS5159
RTL8103T-VB
B
B
+3.3V_CRT_LDO
+1.8V_RUN_VGA
+LCDVDD
+3.3V_RUN_CARD
+1.2V_LOM
For Discrete
Power Shape
Regulator
LDO
Switch
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Power Block Diagram
Document Number
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
3
of
92
A
B
C
PCH SMBus Block Diagram
+3.3V_ALW
Θ
+5V_RUN
Θ
+3.3V_RUN
Θ
SRN2K2J-1-GP
1
SMBCLK
PCH_SMB_CLK
SMBDATA
PCH_SMB_DATA
Θ
Θ
SRN2K2J-1-GP
DIMM 1
Θ
Θ
PCH_SMBCLK
SRN10KJ-5-GP
SDA
SMBus Address:A0
Θ
PSDAT1
TPDATA
PSCLK1
TPCLK
2N7002SPT
SML1CLK
KBC_SCL1
SML1DATA
KBC_SDA1
To KBC
SML0CLK
SML0_CLK
SML0DATA
SML0_DATA
PCH_SMBCLK
Θ
SCL
PCH_SMBDATA
SRN2K2J-1-GP
Θ
XDP
Battery Conn.
SRN100J-3-GP
SDA
Clock
Generator
SRN2K2J-1-GP
Θ
Θ
PCH_SMBCLK
PCH_SMBDATA
SCL1
BAT_SCL
PBAT_SMBCLK1
CLK_SMB
SDA1
BAT_SDA
PBAT_SMBDAT1
DAT_SMB
2
Level
Shift
PCH_HDMI_CLK
PCH_HDMI_DATA
SDATA
SCL
SDA
SMBus address:12
+3.3V_RUN
Θ
PCH_HDMI_CLK
PCH_HDMI_DATA
Θ
Θ
UMA
+3.3V_RUN
Θ
PCH_SMBCLK
PCH_SMBDATA
SRN2K2J-1-GP
UMA
SMBus address:16
BQ24745
KBC
NPCE781BA0DX
SCLK
SMBus address:D2
UMA
SRN0J-6-GP
PCH_SMBCLK
LDDC_CLK_PCH
PCH_SMBDATA
L_DDC_DATA
1
SMBus Address:A4
+3.3V_RUN
L_DDC_CLK
TPCLK
SRN4K7J-8-GP
DIMM 2
Θ
Θ
+3.3V_ALW
SDVO_CTRLCLK
TPDATA
TPCLK
Θ
2N7002DW-1-GP
SDVO_CTRLDATA
TPDATA
+KBC_PWR
SRN2K2J-8-GP
PCH
TouchPad Conn.
Θ
Θ
SCL
PCH_SMBDATA
+3.3V_ALW
E
KBC SMBus Block Diagram
+3.3V_RUN
Θ
D
LDDC_DATA_PCH
Minicard
WLAN
2
+3.3V_RUN
Θ
SMB_CLK
SMB_DATA
Minicard
W-WAN
GPIO73/SCL2
KBC_SCL1
GPIO74/SDA2
KBC_SDA1
SRN4K7J-8-GP
Θ
Θ
Thermal
THERM_SCL
SCL
THERM_SDA
SDA
SMBus address:7A
2N7002DW-1-GP
SMB_CLK
SMB_DATA
UMA
CRT_DDC_CLK
CRT_DDC_DATA
+3.3V_RUN_VGA
PCH_CRT_DDCCLK
Θ
PCH_CRT_DDCDATA
SRN2K2J-1-GP
DIS
3
DDC1CLK
3
LCD CONN
DDC1DATA
SRN0J-6-GP
DDC2CLK
DDC2DATA
VGA_CRT_DDCCLK
VGA_CRT_DDCDATA
+3.3V_RUN
+5V_RUN
DIS
Θ
VGA
Θ
+3.3V_RUN
UMA
SRN0J-6-GP
SRN2K2J-1-GP
UMA
Θ
SRN2K2J-1-GP
CRT_DDCCLK_CON
CRT_DDCDATA_CON
+5V_RUN
+3.3V_RUN_VGA
Θ
Θ
+5V_RUN
CRT CONN
UMA
2N7002DW-1-GP
SRN2K2J-1-GP
SRN2K2J-1-GP
4
4
DIS
IFPC_AUX_I2CW_SCL
GPU_HDMI_CLK
IFPC_AUX_I2C_SDA#
GPU_HDMI_DATA
TSCBTD3305CPWR
HDMI CONN
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
A
http://laptop-motherboard-schematic.blogspot.com/
B
C
D
Size
A2
Date:
SMBUS Block Diagram
Document Number
Rev
Berry
A00
Wednesday, February 10, 2010
E
Sheet
4
of
92
A
B
C
Thermal Block Diagram
D
E
Audio Block Diagram
1
1
SPKR_PORT_D_L-
SPEAKER
SPKR_PORT_D_R+
Codec
92HD79B1
DP1
EMC2102_DP1
MMBT3904-3-GP
HP
OUT
HP1_PORT_B_L
SC470P50V3JN-2GP
HP1_PORT_B_R
2
DN1
EMC2102_DN1
2
Place near CPU
PWM CORE
Thermal
G7922R61U
THRMDA
DP2
VGA_THERMDA
VGA
MIC
IN
HP0_PORT_A_L
HP0_PORT_A_R
THRMDC
DN2
VGA_THERMDC
VREFOUT_A_OR_F
Place near GPU(DISCRETE only).
MMBT3904-3-GP
3
3
DMIC_CLK/GPIO1
System Sensor(UMA only)
DP3
EMC2102_DP3
DN3
EMC2102_DN3
DMIC0/GPIO2
MMBT3904-3-GP
SC470P50V3JN-2GP
PORTC_L
Put under CPU(T8 HW shutdown)
Analog
MIC
PORTC_R
VREFOUT_C
4
4
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Thermal/Audio Block Diagram
A
http://laptop-motherboard-schematic.blogspot.com/
B
C
D
Size
Document Number
Custom
Rev
A00
Berry
Date:
Wednesday, February 10, 2010
Sheet
E
5
of
92
A
B
C
PCH Strapping
SPKR
INIT3_3V#
Weak internal pull-down. Do not pull high.
GNT3#/
GPIO55
Default Mode: Internal pull-up.
Low (0) = Top Block Swap Mode (Connect to ground with 4.7-kȍ weak
pull-down resistor).
INTVRMEN
High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Default (SPI): Left both GNT0# and GNT1# floating. No pull up
required.
Boot from PCI: Connect GNT1# to ground with 1-kȍ pull-down
resistor. Leave GNT0# Floating.
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kȍ
pull-down resistor.
Default - Internal pull-up.
Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops).
GNT0#,
GNT1#/GPIO51
GNT2#/
GPIO53
GPIO33
Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-kȍ
pull-down resistor.
SPI_MOSI
NV_ALE
Enable iTPM: Connect to Vcc3_3 with 8.2-kȍ weak pull-up resistor.
Disable iTPM: Left floating, no pull-down required.
Enable Danbury: Connect to Vcc3_3 with 8.2-kȍ weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-kȍ weak pull-down
resistor.
NC_CLE
Weak internal pull-up. Do not pull low.
HAD_DOCK_EN#
/GPIO[33]
HDA_SDO
Low (0): Flash Descriptor Security will be overridden.
High (1) : Flash Descriptor Security will be in effect.
Weak internal pull-down. Do not pull high.
3
HDA_SYNC
Weak internal pull-down. Do not pull high.
GPIO15
Weak internal pull-down. Do not pull high.
GPIO8
Weak internal pull-up. Do not pull low.
GPIO27
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2
Calpella Schematic Checklist Rev.0_7
Reboot option at power-up
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kȍ
- 10-kȍ weak pull-up resistor.
4
PCIE Routing
LANE2
LANE3
RESERVED
MiniCard WLAN
0
USB3 (CRT Board)
2
WLAN (I/O Board)
LAN
3
RESERVED
LANE4
W-WAN
4
CARD READER
LANE5
RESERVED
6
LANE6
RESERVED
7
HM55 no support
8
USB1 (I/O Board)
9
USB0 (I/O Board ESATA)
10
RESERVED
11
W-WAN (I/O Board)
12
RESERVED
13
CAMERA
LANE7
H55/HM55 no support
LANE8
H55/HM55 no support
Configuration (Default value for each bit is
1 unless specified otherwise)
Default
Value
CFG[4]
Embedded
DisplayPort
Presence
1: Disabled - No Physical Display Port attached to
Embedded DisplayPort.
0: Enabled - An external Display Port device is
connected to the Embedded Display Port.
1: Normal Operation.
0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
1
4
CFG[3]
PCI-Express Static
Lane Reversal
CFG[0]
PCI-Express
Configuration
Select
1: Single PCI-Express Graphics
0: Bifurcation enabled
1
CFG[7]
Reserved Temporarily used
for early
Clarksfield
samples.
Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor
Note: Only temporary for early CFD samples
(rPGA/BGA) [For details please refer to the WW33
MoW and sighting report].
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
impact AUB functionality.
0
1
SATA Table
SATA
Pair
Device
USB2 (CRT Board)
1
5
1
Device
Strap Description
2
USB Table
Pair
Pin Name
3
USB
LANE1
E
Processor Strapping
Calpella Schematic Checklist Rev.0_7
Schematics Notes
Name
D
BLUETOOTH
HM55 no support
0
HDD
1
ODD
2
HM55 no support
3
HM55 no support
4
ESATA
5
RESERVED
http://laptop-motherboard-schematic.blogspot.com/
1
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
Document Number
Table of Content
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
6
of
92
5
4
3
2
1
SSID = CLOCK
X02-20091222
+3.3V_RUN_SL585
+1.05V_VTT
X02-20091222
D
2
1
1
C711
SCD1U16V2ZY-2GP
2
1
1
C710
x01 change tolerant 20091117
+3.3V_RUN_SL585
+3.3V_RUN
C709
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
x01 change tolerant 20091117
DY
2
1
C708
C707
2
1
C706
SCD1U16V2ZY-2GP
2
1
C705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
1
C704
2
C703
2
1
C701
2
0R0603-PAD
SC10U10V5ZY-1GP
DY
SC1U6D3V2KX-GP
1
1
SC10U10V5ZY-1GP
+1.05V_RUN_SL585_IO
R703
23 CLKIN_DMI#
23 CLKIN_DMI
RN
23 CLK_PCIE_SATA#
23 CLK_PCIE_SATA
14
13
SRC_2#
SRC_2
6
7
CLK_VGA_27M_NSS_R
CLK_VGA_27M_SS_R
CPU_STOP#
CKPWRGD/PD#
REF_0/CPU_SEL
16
25
30
CPU_STOP#
CK_PW RGD
FSC
CPU_0#
CPU_0
XTAL_IN
XTAL_OUT
28
27
CLK_XTAL_IN
CLK_XTAL_OUT
CPU_1#
CPU_1
SDA
SCL
31
32
11
10
SRC_1/SATA#
SRC_1/SATA
22
23
19
20
1
R708 1
R709
DIS
2
2 33R2J-2-GP
33R2J-2-GP
DY
CLK_VGA_27M_NSS 82
CLK_VGA_27M_SS 82
DY
R704
2
1
33R2J-2-GP
1
27MHZ
27MHZ_SS
1
DOT_96#
DOT_96
EC701
SC4D7P50V2CN-1GP
DY
EC702
SC4D7P50V2CN-1GP
CLK_PCH_14M 23
DY
EC703
SC4D7P50V2CN-1GP
VSS_SATA
PCH_SMBDATA 18,19,23,76
PCH_SMBCLK 18,19,23,76
+3.3V_RUN_SL585
B
9
8
2
2
VSS_27
VSS_DOT
VSS_SRC
VSS_CPU
12
26
33
SLG8SP585VTR-GP
21
B
VSS_REF
GND
2
RN
23 CLK_CPU_BCLK#
23 CLK_CPU_BCLK
2 RN703 3 CLK_PCIE_SATA#_C
1
4 CLK_PCIE_SATA_C
0R4P2R-PAD
4
3
2
2
3
1
4
0R4P2R-PAD
23 CLK_DREF#
23 CLK_DREF
CLKIN_DMI#_C
CLKIN_DMI_C
X01-20091116
2
RN702
18
VDD_SRC_IO
X02-20091222
C
VDD_CPU_IO
15
1
17
5
VDD_27
VDD_DOT
VDD_REF
24
VDD_CPU
U701
29
CPU_STOP#
2
2K2R2J-2-GP
C
VDD_SRC
1
1
2
C702
SC1U6D3V2KX-GP
DY
R702
2
0R0603-PAD
2
1
1
D
+1.05V_RUN_SL585_IO
R701
2
+3.3V_RUN
CK_PW RGD
+1.05V_VTT
D
1
133MHz
Q701
2N7002E-1-GP
.
.
. .
DY 4K7R2J-2-GP
1
G
X-14D31818M-37GP
82.30005.901
2
C712
SC12P50V2JN-3GP
CLK_XTAL_OUT
2
1
1
(Default)
1
.
R706
X701
CLK_XTAL_IN
100MHz
2
SPEED
C713
SC12P50V2JN-3GP
S
0
2
FSC
1
R705
10KR2J-3-GP
FSC
2
47 VR_CLKEN#
1
R707
10KR2J-3-GP
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Clock Generator SLG8SP585
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
7
of
92
5
4
SSID = CPU
3
2
1
D
D
1 OF 9
CPU1A
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
22
22
22
22
DMI_PTX_CRXP0
DMI_PTX_CRXP1
DMI_PTX_CRXP2
DMI_PTX_CRXP3
B24
D23
B23
A22
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
22
22
22
22
DMI_CTX_PRXN0
DMI_CTX_PRXN1
DMI_CTX_PRXN2
DMI_CTX_PRXN3
D24
G24
F23
H23
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
22
22
22
22
DMI_CTX_PRXP0
DMI_CTX_PRXP1
DMI_CTX_PRXP2
DMI_CTX_PRXP3
D25
F24
E23
G23
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
E22
D21
D19
D18
G21
E19
F21
G18
FDI_TX#0
FDI_TX#1
FDI_TX#2
FDI_TX#3
FDI_TX#4
FDI_TX#5
FDI_TX#6
FDI_TX#7
22
22
22
22
22
22
22
22
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
D22
C21
D20
C18
G22
E20
F20
G19
FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7
22 FDI_FSYNC0
22 FDI_FSYNC1
F17
E17
FDI_FSYNC0
FDI_FSYNC1
22 FDI_INT
C17
FDI_INT
22 FDI_LSYNC0
22 FDI_LSYNC1
F18
D17
FDI_LSYNC0
FDI_LSYNC1
1
B
R804
1KR2J-1-GP
DIS
RN801
SRN1KJ-4-GP
1
2
3
4
2
DIS
8
7
6
5
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
Intel(R) FDI
22
22
22
22
22
22
22
22
PCI EXPRESS -- GRAPHICS
A24
C23
B22
A21
CLARKSFIELD
DMI_PTX_CRXN0
DMI_PTX_CRXN1
DMI_PTX_CRXN2
DMI_PTX_CRXN3
DMI
C
22
22
22
22
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
B26 PEG_IRCOMP_R
A26
B27
EXP_RBIAS
A25
R801 1
R802 1
2 49D9R2F-GP
2 750R2F-GP
PEG_RXN[0..15]
PEG_RXN[0..15]
80
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0
C816
C815
C814
C813
C812
C811
C810
C809
C808
C807
C806
C805
C804
C803
C802
C801
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0
C832
C831
C830
C829
C828
C827
C826
C825
C824
C823
C822
C821
C820
C819
C818
C817
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_RXP[0..15]
PEG_RXP[0..15] 80
C
PEG_TXN[0..15]
PEG_TXN[0..15] 80
B
PEG_TXP[0..15]
PEG_TXP[0..15] 80
x01 change tolerant 20091117
CLARKUNF
62.10055.341
SEC. 62.10053.561
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
http://laptop-motherboard-schematic.blogspot.com/
Size
CPU (PCIE/DMI/FDI)
Document Number
Rev
Berry
Date:
Monday, March 29, 2010
A00
Sheet
8
of
92
4
SSID
= CPU
1
AN26
H_CPURST#
AL15
22 H_PM_SYNC
X02-20091222
AN14
VCCPWRGOOD
1 R910
2
0R0402-PAD
1 R912
2
0R0402-PAD
VDDPWRGOOD_R
H_PWRGD_XDP
1
AM26
2
R917
1K54R2F-GP
R918
750R2F-GP
RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
TCK
TMS
TRST#
TDI
TDO
TDI_M
TDO_M
DBR#
DY
DY
DY
23 SML0_DATA
23 SML0_CLK
2
DY
XDP_TCLK
x01 change tolerant 20091117
XDP_PRDY#
XDP_PREQ#
AN28
AP28
AT27
XDP_TCLK
XDP_TMS
XDP_TRST#
AT29
AR27
AR29
AP29
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
AN25
H_DBR#_R
1
2
4
3
RN904
0R4P2R-PAD
1
PM_EXTTS#0 18
PM_EXTTS#1 19
X03-20100118
DDR3 Compensation Signals
SM_RCOMP_0
R913 1
2 100R2F-L1-GP-U
SM_RCOMP_1
R914 1
2 24D9R2F-L-GP
SM_RCOMP_2
R916 1
2 130R2F-1-GP
X02-20091222
+1.05V_VTT
1 R911
2
0R0402-PAD
XDP_DBRESET#
XDP_TMS
1
R919
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
XDP_TDI_R
+1.5V_RUN_CPU
1
R920
XDP_PREQ#
DY
1
R922
XDP_TCLK
R915
1KR2J-1-GP
SM_DRAMRST#
1
R923
DY 2
DY 2
DY 2
DY
51R2J-2-GP
51R2J-2-GP
51R2J-2-GP
2
51R2J-2-GP
X01 20091111
C
R921
100KR2J-1-GP
2
1
2
3
A
B
GND
VCC
Y
5
4
VTT_PWRGD_C
1
H_CPUPWRGD_XDP
2
2 1KR2J-1-GP PM_PWRBTN#_XDP
0R2J-2-GP
PCIE_CLK_XDP_P
2
0R2J-2-GP
1
22 PM_PWRBTN#_R
H_PWRGD_XDP
1
R935 1
R937
1
R938
AT28
AP27
DY
DY 2
0R2J-2-GP
1
R929
DY
0R2J-2-GP
1
2
DY
1
R928
XDP_TDO_M
VDDPWRGOOD_KBC
37
XDP_TDI_M
XDP_TDO_R
+1.05V_VTT
Scan Chain
(Default)
CPU Only
x01 change tolerant 20091117
C901
SCD1U10V2KX-5GP
XDP_RST#_R
1
R939
DY
GMCH Only
R936
51R2J-2-GP
DY
2H_CPURST#
1KR2J-1-GP
XDP_TDO
2
R931
0R0402-PAD
X02-20091224
R930
750R2F-GP
BCLK_ITP_P
BCLK_ITP_N
XDP_TDI
XDP_TRST#
R941
1
2
1K54R2F-GP
1
VDDPWRGOOD_R
XDP_TDI_R
2
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
R927
1K54R2F-GP
NL17SZ08DFT2G-GP
NP1
61
2
62
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
64
NP2
1
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
H_PWRGD
D
C903
SCD1U10V2KX-5GP
2
0R2J-2-GP
1
R933
DY 2
R932
1 R934
2
0R0402-PAD
0R2J-2-GP
X02-20091222
Stuff --> R928, R931, R934
No Stuff --> R929, R933
Stuff --> R928, R929
No Stuff --> R931, R934, R933
Stuff --> R933, R934
No Stuff --> R928, R929, R931
JTAG MAPPING
2
+1.05V_VTT
DY
x01 change tolerant 20091117
1
1
2
DY
PRDY#
PREQ#
2
XDP_OBS2
XDP_OBS3
X01 20091112
1
R909
SRN10KJ-5-GP
2E
XDP_OBS0
XDP_OBS1
VDDPWRGOOD_R
R926
3KR2F-GP
4
3
RSTIN#
XDP1
XDP_PREQ#
XDP_PRDY#
R925
1K1R2F-GP
2
DY
PM_EXTTS#0_C
PM_EXTTS#1_C
+1.05V_VTT
1
2
18,19
U901
1
1
1
R924
1K1R2F-GP
RN903
AN15
AP15
DDR3_DRAMRST#
2N7002E-1-GP
PM_EXTTS#0_C 53
CLARKUNF
50 0D75V_EN
+1.5V_RUN_CPU
2
DY
1
DY
x01 change tolerant 20091117
+1.5V_SUS
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
AL1
AM1
AN1
R908
1KR2J-1-GP
D
S
+3.3V_RUN
SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
DY
SM_DRAMRST#
F6
A00-20100226
EC901
C901
2E
EC902
C902
2E
DY
SCD1U10V2KX-5GP
2E
EC903
C903
1
1
SCD1U10V2KX-5GP
1
DY
SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
DY
EC904
C904
2E
EC905
C905
2E
EC906
C906
C902
SCD1U10V2KX-5GP
AL14
PM_EXT_TS#0
PM_EXT_TS#1
2
XDP_RST#_R
VCCPWRGOOD
VDDPWRGOOD_R
H_VTTPWRGD
PLT_RST#_R
XDP_DBRESET#
PLT_RST#_R
THERMTRIP#
G
1
49 H_VTTPWRGD
X01 20091121
VTTPWRGOOD signal must be clean
and close to CPU
21,37,70,76,78,80 PLT_RST#
For EMI
B
AK13
AM15
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
Q901
A18
A17
51R2J-2-GP
2
22 PM_DRAM_PWRGD
AN27
SM_DRAMRST#
+1.5V_SUS
CLK_EXP_P 23
CLK_EXP_N 23
1
25,42 H_PWRGD
PROCHOT#
PWR MANAGEMENT
AP26
PECI
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
S3_RST_GATE# 25
X01 20091117
1 RN902 4
2
3
0R4P2R-PAD
RN
AK15
H_THERMTRIP#
CATERR#
CLK_EXP_C_P
CLK_EXP_C_N
25
25
.
AT15
25 H_PECI
SKTOCC#
E16
D16
BCLK_CPU_P
BCLK_CPU_N
.
.
. .
AK14
THERMAL
AH24
H_CATERR#
PEG_CLK
PEG_CLK#
1 RN901 4
2
3
0R4P2R-PAD
BCLK_ITP_P
BCLK_ITP_N
AR30
AT30
1
TP901
SKTOCC#_R
47 H_PROCHOT#
C
COMP0
BCLK_ITP
BCLK_ITP#
A16 BCLK_CPU_C_P
B16 BCLK_CPU_C_N
2
TPAD14-GP
25,37,42,82
COMP1
BCLK
BCLK#
2
AT26
49D9R2F-GP
COMP2
1
2
COMP3
H_CPURST#
2 68R2-GP
D
H_COMP0
49D9R2F-GP
1
DY
G16
1
2
R904
R905
R906 1
AT24
H_COMP1
CLOCKS
H_PROCHOT#
2 68R2-GP
AT23
H_COMP2
20R2F-GP
DDR3
MISC
R907 1
H_COMP3
20R2F-GP
JTAG & BPM
2
CLARKSFIELD
2
1
RN
2
1
R903
2
RN
H_CATERR#
2 49D9R2F-GP
MISC
1
R902
R901 1
3
X02-20091222
2 OF 9
CPU1B
2
Processor Compensation Signals
Processor Pullups
1
5
+1.05V_VTT
XDP_DBRESET# 22,23
B
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_RST#_R
1
R940
2
DY0R2J-2-GP
PLT_RST# 21,37,70,76,78,80
PAD-60P-GP
A00-20100208
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
CPU (THERMAL/CLOCK/PM )
Size
Document Number
Date:
Monday, March 29, 2010
Rev
A00
Berry
Sheet
1
9
of
92
5
4
3
2
SSID = CPU
C
B
18 M_A_BS0
18 M_A_BS1
18 M_A_BS2
AC3
AB2
U7
18 M_A_CAS#
18 M_A_RAS#
18 M_A_W E#
AE1
AB3
AE9
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_CK1
SA_CK#1
SA_CKE1
Y6
Y5
P6
M_CLK_DDR1 18
M_CLK_DDR#1 18
M_CKE1 18
SA_CS#0
SA_CS#1
AE2
AE8
M_CS#0 18
M_CS#1 18
SA_ODT0
SA_ODT1
AD8
AF9
M_ODT0 18
M_ODT1 18
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
B9
D7
H7
M7
AG6
AM7
AN10
AN13
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_CLK_DDR0 18
M_CLK_DDR#0 18
M_CKE0 18
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DM[7..0] 18
M_A_DQS#[7..0] 18
M_A_DQS[7..0] 18
SA_BS0
SA_BS1
SA_BS2
SA_CAS#
SA_RAS#
SA_WE#
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
C9
F8
J9
N9
AH7
AK9
AP11
AT13
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
C8
F9
H9
M9
AH8
AK10
AN11
AR13
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A[15..0] 18
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
CLARKSFIELD
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
19 M_B_DQ[63..0]
AA6
AA7
P7
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
19 M_B_BS0
19 M_B_BS1
19 M_B_BS2
AB1
W5
R7
SB_BS0
SB_BS1
SB_BS2
19 M_B_CAS#
19 M_B_RAS#
19 M_B_W E#
AC5
Y7
AC6
SB_CAS#
SB_RAS#
SB_WE#
SB_CK0
SB_CK#0
SB_CKE0
W8
W9
M3
M_CLK_DDR2 19
M_CLK_DDR#2 19
M_CKE2 19
SB_CK1
SB_CK#1
SB_CKE1
V7
V6
M2
M_CLK_DDR3 19
M_CLK_DDR#3 19
M_CKE3 19
SB_CS#0
SB_CS#1
AB8
AD6
M_CS#2 19
M_CS#3 19
SB_ODT0
SB_ODT1
AC7
AD1
M_ODT2 19
M_ODT3 19
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
D4
E1
H3
K1
AH1
AL2
AR4
AT8
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
D5
F4
J4
L4
AH2
AL4
AR5
AR8
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
C5
E3
H4
M5
AG2
AL5
AP5
AR7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
D
M_B_DM[7..0] 19
M_B_DQS#[7..0] 19
M_B_DQS[7..0] 19
DDR SYSTEM MEMORY - B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CLARKSFIELD
M_A_DQ[63..0]
SA_CK0
SA_CK#0
SA_CKE0
DDR SYSTEM MEMORY A
18 M_A_DQ[63..0]
4 OF 9
CPU1D
3 OF 9
CPU1C
D
1
C
M_B_A[15..0] 19
B
CLARKUNF
CLARKUNF
A
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
CPU (DDR)
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
10
of
92
5
4
3
2
1
SSID = CPU
CPU1E
5 OF 9
RSVD#AJ13
RSVD#AJ12
CFG0
1
PCI-Express Configuration Select
CFG0
1:Single PEG
0:Bifurcation enabled
2
DY
R1101
3KR2F-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TP1101
TP1102
TP1103
1
1
1
TPAD14-GP
TPAD14-GP
TP1104
TP1105
1
1
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TP1106
TP1107
TP1108
TP1109
TP1110
TP1111
TP1112
TP1113
TP1114
TP1115
1
1
1
1
1
1
1
1
1
1
CFG3
CFG3 - PCI-Express Static Lane Reversal
1
DIS
R1104
3KR2J-2-GP
CFG3
2
C
1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
RSVD#AP25
RSVD#AL25
RSVD#AL24
RSVD#AL22
RSVD#AJ33
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF
SB_DIMM_VREF
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP_86
CFG4
1
CFG4 - Display Port Presence
CFG4
2
DY
R1105
3KR2F-GP
B19
A19
1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
A20
B20
U9
T9
AC9
AB9
RSVD#AH25
RSVD#AK26
RSVD#AL26
RSVD_NCTF_37
RSVD#AJ26
RSVD#AJ27
RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33
RESERVED
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
CLARKSFIELD
D
1
B
2
DY
R1106
3KR2F-GP
CFG7
J29
J28
Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor.
D
AH25
AK26
AL26
AR2
AJ26
AJ27
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
C
RSVD#AR32
RSVD_TP#E15
RSVD_TP#F15
KEY
RSVD#D15
RSVD#C15
RSVD#AJ15
RSVD#AH15
AR32
E15
F15
A2
D15
C15
AJ15
AH15
RSVD#B19
RSVD#A19
RSVD#A20
RSVD#B20
SA_CK2
SA_CK#2
SA_CKE2
SA_CS#2
SA_ODT2
SA_CK3
SA_CK#3
SA_CKE3
SA_CS#3
SA_ODT3
RSVD#U9
RSVD#T9
RSVD#AC9
RSVD#AB9
CFG7
CFG7(Reserved) - Temporarily used for early
Clarksfield samples.
AJ13
AJ12
SB_CK2
SB_CK#2
SB_CKE2
SB_CS#2
SB_ODT2
SB_CK3
SB_CK#3
SB_CKE3
SB_CS#3
SB_ODT3
RSVD#J29
RSVD#J28
Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
VSS (AP34) can be left NC is
CRB implementation; EDS/DG
recommendation to GND.
B
R1107
VSS
AP34
RSVD_VSS
1
2
0R0402-PAD
X02-20091224
CLARKUNF
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
CPU (RESERVED)
Document Number
Rev
Berry
Date:
A00
Wednesday, February 10, 2010
Sheet
1
11
of
92
5
4
3
SSID = CPU
CPU1F
2
1
6 OF 9
2
1
2
1
1
1
1
2
DY
2
1
1
2
2
2
2
2
2
1
1
1
1
1
2
1
2
1
2
2
1.1V RAIL POWER
PSI#
CPU VIDS
C
VID
VID
VID
VID
VID
VID
VID
PROC_DPRSLPVR
VTT_SELECT
AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
PSI# 47
H_VID[6..0]
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
47
PM_DPRSLPVR
47
B
G15
H_VTTVID1
1
TP1201
TPAD14-GP
H_VTTVID1 = Low, 1.1V
H_VTTVID1 = High, 1.05V
1
+VCC_CORE
AN35
R1201
100R2F-L1-GP-U
IMVP_IMON 47
2
ISENSE
AJ34
AJ35
VCC_SENSE 47
VSS_SENSE 47
1
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
B15
A15
TP_VSS_SENSE_VTT 1
R1202
100R2F-L1-GP-U
VTT_SENSE 49
TP1202
TPAD14-GP
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
C1234
Please note that the VTT Rail
Values are Auburndale
VTT=1.05V; Clarksfield
VTT=1.1V
POWER
1
2
1
1
1
2
2
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
B
C1233
SC10U6D3V5MX-3GP
C1242
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
SC10U6D3V5KX-1GP
C1241
+1.05V_VTT
x01 change tolerant 20091117
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
CPU CORE SUPPLY
C1240
C1232
DY
SC10U6D3V5MX-3GP
C1239
DY
C1231
DY
SC10U6D3V5KX-1GP
C1238
SC10U6D3V5MX-3GP
DY
SC10U6D3V5KX-1GP
2
C1230
DY
SC10U6D3V5KX-1GP
C1237
SC10U6D3V5KX-1GP
1
C1229
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
SC22U6D3V5MX-2GP
2
C1228
x01 change tolerant 20091117
C1236
SC10U6D3V5KX-1GP
C1243
DY
SC10U6D3V5KX-1GP
DY
C1227
SC10U6D3V5KX-1GP
C1235
DY
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
C
C1226
D
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.
C1218
DY
DY
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
x01 change tolerant 20091117
C1225
SC10U10V5ZY-1GP
C1224
DY
C1217
C1214
DY
+1.05V_VTT
x01 change tolerant 20091117
C1216
C1213
DY
SC10U6D3V5MX-3GP
C1223
C1204
SC10U10V5ZY-1GP
C1222
C1203
SC10U6D3V5KX-1GP
C1221
DY
C1212
SC10U6D3V5KX-1GP
C1220
DY
C1211
DY
SC10U6D3V5KX-1GP
C1219
DY
C1208
SC10U6D3V5KX-1GP
x01 change tolerant 20091117
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
C1215
C1210
SC10U6D3V5KX-1GP
C1207
C1202
DY
SC10U6D3V5KX-1GP
C1206
C1209
SC10U10V5ZY-1GP
C1205
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
SC10U6D3V5KX-1GP
C1201
+1.05V_VTT
x01 change tolerant 20091117
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
SC10U10V5ZY-1GP
48A
x01 change tolerant 20091117
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SENSE LINES
+VCC_CORE
D
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
CLARKSFIELD
+VCC_CORE
PROCESSOR CORE POWER
A
A
<Core Design>
CLARKUNF
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
http://laptop-motherboard-schematic.blogspot.com/
Date:
5
CPU (VCC_CORE)
Document Number
4
3
2
Rev
Berry
Monday, March 29, 2010
A00
Sheet
1
12
of
92
5
4
3
2
1
SSID = CPU
+CPU_GFX_CORE
DDR3
C1315
TC1301
C1333
DY
+1.5V_SUS
C
1
1
C1332
C1334
DY
2
2
DY
1
C1331
2
1
2
2
2
DY SE330U2D5VDM-2GP
x01 change tolerant 20091117
S3 Reduction
DY
2
1
C1314
1
1
1
2
2
2
1
1
1
C1313
+1.05V_VTT
1
1
2
x01 change tolerant 20091117
1
B
C1325
SC4D7U6D3V3KX-GP
DY
L26
L27
M26
1
1
2
2
SC2D2U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
C1329
2
1
C1328
C1327
SC1U6D3V2KX-GP
C1326
SC1U6D3V2KX-GP
2
1.35A
1
SENSE
LINES
2
VCCPLL
VCCPLL
VCCPLL
C1319
SC10U6D3V5KX-1GP
2
J22
J20
J18
H21
H20
H19
1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
2
2.6A
C1324
SC10U6D3V5KX-1GP
CLARKUNF
C1312
x01 change tolerant 20091117
2
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
1.1V
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
C1311
3A
+1.05V_VTT
1.8V
1
2
1
2
1
1
2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
2
C1323
C1310
2
P10
N10
L10
K10
1
VTT0
VTT0
VTT0
VTT0
C1309
+1.5V_RUN_CPU
2
DIS 1KR2J-1-GP
SCD1U10V2KX-5GP
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
GFX_VR_EN 53
GFX_DPRSLPVR 53
GFX_IMON 53
2
0R2J-2-GP
SCD1U10V2KX-5GP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DY
SCD1U10V2KX-5GP
- 1.5V RAILS
1
R1303
1
R1304
SCD1U10V2KX-5GP
C1322
GFX_IMON_C
1 4K7R2J-2-GP
UMA
C1318
SC10U6D3V5KX-1GP
PEG & DMI
C1321
DY
2
SC22U6D3V5MX-2GP
1
R1305
53
53
53
53
53
53
53
SC22U6D3V5MX-2GP
2
AR25
AT25
AM24
SC1U6D3V2KX-GP
1
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6
SC1U6D3V2KX-GP
2
AM22
AP22
AN22
AP23
AM23
AP24
AN24
x01 change tolerant 20091117
18A
C1320
SC10U6D3V5KX-1GP
B
VTT1
VTT1
VTT1
FDI
+1.05V_VTT
J24
J23
H25
SC10U6D3V5KX-1GP
C1316
SC10U6D3V5KX-1GP
C1317
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
D
VCC_AXG_SENSE 53
VSS_AXG_SENSE 53
SC1U6D3V2KX-GP
+1.05V_VTT
AR22
AT22
SC1U6D3V2KX-GP
C
VAXG_SENSE
VSSAXG_SENSE
SC1U6D3V2KX-GP
Please note that the VTT Rail
Values are: Auburndale VTT=1.05V
Clarksfield VTT=1.1V
GRAPHICS VIDs
0R3J-0-U-GP
GRAPHICS
SC10U6D3V5MX-3GP
2
2
DIS
CLARKSFIELD
UMA
R1302
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
POWER
1
C1308
1
2
1
UMA
2
UMA
2
1
1
2
1
1
1
C1307
SC10U6D3V5MX-3GP
2
DY UMA
C1306
SC10U6D3V5MX-3GP
2
DY
C1305
SC10U6D3V5MX-3GP
2
C1304
SC10U6D3V5MX-3GP
DY
C1303
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
C1302
1
D
C1301
7 OF 9
CPU1G
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
2
22A
+1.8V_RUN
C1330
SC10U6D3V5MX-3GP
x01 change tolerant 20091117
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
CPU (VCC_GFXCORE)
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
13
of
92
5
4
3
2
1
SSID = CPU
8 OF 9
B
VSS
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
CLARKUNF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLARKSFIELD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
C
VSS
NCTF
C
CLARKSFIELD
D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 9
CPU1I
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
NCYF TEST PIN:
A35,AT1,AT35,B1,A3,A33,A34,
AP1,AP35,AR1,AR35,AT2,AT3,
AT33,AT34,C1,C35,B35
CPU1H
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
VSS_NCTF
VSS_NCTF
VSS_NCTF
AR34
B34
B2
VSS_NCTF#A35
VSS_NCTF#AT1
VSS_NCTF#AT35
VSS_NCTF#B1
RSVD_NCTF#A3
RSVD_NCTF#A33
RSVD_NCTF#A34
RSVD_NCTF#AP1
RSVD_NCTF#AP35
RSVD_NCTF#AR1
RSVD_NCTF#AR35
RSVD_NCTF#AT2
RSVD_NCTF#AT3
RSVD_NCTF#AT33
RSVD_NCTF#AT34
RSVD_NCTF#C1
RSVD_NCTF#C35
RSVD_NCTF#B35
A35
AT1
AT35
B1
A3
A33
A34
AP1
AP35
AR1
AR35
AT2
AT3
AT33
AT34
C1
C35
B35
TP_MCP_VSS_NCTF1
TP_MCP_VSS_NCTF2
TP_MCP_VSS_NCTF3
TP_MCP_VSS_NCTF4
1
1
1
1
TP1401
TP1402
TP1403
TP1404
B
CLARKUNF
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (VSS)
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Document Number
Rev
Berry
Date:
W ednesday, February 10, 2010
A00
Sheet
1
14
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
15
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
16
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
17
of
92
5
4
3
2
1
SSID = MEMORY
10
M_A_DQS#[7..0]
1
2
C1822
SC1U6D3V2KX-GP
DY
x01 change tolerant 20091117
30
9,19 DDR3_DRAMRST#
203
204
+0.75V_DDR_VTT
H =4mm
1
2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
SA0_DIM0
SA1_DIM0
C1801
SCD1U10V2KX-5GP
DY
C1802
x01 change tolerant 20091117
SC2D2U6D3V3KX-GP
+1.5V_SUS
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
SODIMM A DECOUPLING
+1.5V_SUS
2
C1817
C1810
DY
1
C
DY
2
1
1
C1809
DY
2
C1808
2
1
1
C1807
2
2
1
2
2
1
C1816
C1806
DY
1
1
C1805
2
C1815
2
2
2
1
C1814
Layout Note:
Place these Caps near
SO-DIMMA.
C1804
1
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
1
C1803
DY
2
TC1801
1
x01 change tolerant 20091117
2
197
201
77
122
125
x01 change tolerant 20091117
S3 Power Reduction
1
+0.75V_DDR_VTT
2
R1806
22R2J-2-GP
B
Q1801
D
2
1
C1821
SC1U6D3V2KX-GP
2
1
2
DY
C1820
SC1U6D3V2KX-GP
1
2
C1819
SC1U6D3V2KX-GP
+V_DDR_REF
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+3.3V_RUN
PM_EXTTS#0 9
199
.
.
.
. .
2N7002E-1-GP
42,50 PS_S3CNTRL
S
126
1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
PCH_SMBDATA 7,19,23,76
PCH_SMBCLK 7,19,23,76
198
G
1
1
2
1
2
2
1
116
120
10 M_ODT0
10 M_ODT1
SA0
SA1
NC#1
NC#2
NC#/TEST
200
202
SC10U6D3V5KX-1GP
12
29
47
64
137
154
171
188
VDDSPD
M_CLK_DDR1 10
M_CLK_DDR#1 10
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SC10U6D3V5KX-1GP
Place these caps
close to VTT1 and
VTT2.
+0.75V_DDR_VTT
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SDA
SCL
EVENT#
11
28
46
63
136
153
170
187
SCD1U10V2KX-5GP
C1818
SC10U6D3V5KX-1GP
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
D
DISCHARGE_0D75V
DY
10
27
45
62
135
152
169
186
M_CLK_DDR0 10
M_CLK_DDR#0 10
102
104
SCD1U10V2KX-5GP
B
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
CK1
CK1#
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
R1804
10KR2J-3-GP
SCD1U10V2KX-5GP
+0.75V_DDR_VTT
101
103
R1803
10KR2J-3-GP
SCD1U10V2KX-5GP
C1813
SCD1U10V2KX-5GP
M_CKE0 10
M_CKE1 10
SC10U10V5ZY-1GP
SC2D2U6D3V3KX-GP
73
74
SA1_DIM0
SC10U6D3V5KX-1GP
C1812
M_CS#0 10
M_CS#1 10
SC10U6D3V5KX-1GP
DY
114
121
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
SA0_DIM0
SC10U10V5ZY-1GP
C1811
SCD1U10V2KX-5GP
CK0
CK0#
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_RAS# 10
M_A_WE# 10
M_A_CAS# 10
SC10U6D3V5KX-1GP
x01 change tolerant 20091118
CKE0
CKE1
110
113
115
SC10U6D3V5KX-1GP
+V_DDR_REF
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
CS0#
CS1#
10
SE330U2D5VDM-2GP
C
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
RAS#
WE#
CAS#
M_A_A[15..0]
NP1
NP2
1
109
108
10 M_A_BS0
10 M_A_BS1
10 M_A_DQ[63..0]
NP1
NP2
1
10 M_A_BS2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
2
D
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
10
10
2
M_A_DQS[7..0]
DM1
1
M_A_DM[7..0]
84.2N702.D31
DDR3-204P-47-GP
62.10017.P31
SEC. 62.10017.P11
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR3-SODIMM1
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
A00
Berry
Sheet
1
18
of
92
5
4
3
SSID = MEMORY
1
2
1
2
1
2
1
2
C1921
SC1U6D3V2KX-GP
1
C1920
SC1U6D3V2KX-GP
2
1
2
C1919
SC1U6D3V2KX-GP
C1918
SC1U6D3V2KX-GP
1
2
DY
VTT1
VTT2
H = 8mm
1
2
RESET#
1
2
PCH_SMBDATA 7,18,23,76
PCH_SMBCLK 7,18,23,76
198
+3.3V_RUN
PM_EXTTS#1 9
199
197
201
SA0_DIM1
SA1_DIM1
77
122
125
C1901
SCD1U10V2KX-5GP
DY
C1902
SC2D2U6D3V3KX-GP
+1.5V_SUS
x01 change tolerant 20091118
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
C
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
SODIMM B DECOUPLING
+1.5V_SUS
x01 change tolerant 20091117
x01 change tolerant 20091117
C1913
1
C1910
DY
2
2
2
2
DY
1
C1909
1
1
C1908
C1914
1
C1912
C1907
SCD1U10V2KX-5GP
2
C1911
Layout Note:
Place these Caps near
SO-DIMMB.
1
1
C1906
2
C1905
DY
2
2
DY
1
1
C1904
2
C1903
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
200
202
1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
D
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
R1903
10KR2J-3-GP
SCD1U10V2KX-5GP
2
SA0
SA1
NC#1
NC#2
NC#/TEST
M_CLK_DDR3 10
M_CLK_DDR#3 10
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
1
VDDSPD
11
28
46
63
136
153
170
187
SA0_DIM1
2
EVENT#
102
104
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
SA1_DIM1
SC10U6D3V5KX-1GP
DY
SDA
SCL
VREF_CA
VREF_DQ
203
204
Place these caps
close to VTT1 and
VTT2.
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
ODT0
ODT1
30
9,18 DDR3_DRAMRST#
R1902
10KR2J-3-GP
SC10U10V5ZY-1GP
+0.75V_DDR_VTT
CK1
CK1#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
126
1
+V_DDR_REF
CK0
CK0#
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
116
120
10 M_ODT2
10 M_ODT3
M_CLK_DDR2 10
M_CLK_DDR#2 10
10
10
SC10U6D3V5KX-1GP
C1917
SCD1U10V2KX-5GP
M_CKE2 10
M_CKE3 10
101
103
M_B_A[15..0]
SC10U6D3V5KX-1GP
SC2D2U6D3V3KX-GP
12
29
47
64
137
154
171
188
73
74
M_B_DQS[7..0]
SC10U6D3V5KX-1GP
C1916
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_CS#2 10
M_CS#3 10
SC10U6D3V5KX-1GP
DY
10
27
45
62
135
152
169
186
114
121
+3.3V_RUN
SC10U10V5ZY-1GP
x01 change tolerant 20091118
C1915
SCD1U10V2KX-5GP
1
10
SCD1U10V2KX-5GP
B
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
10
M_B_DQS#[7..0]
SCD1U10V2KX-5GP
2
C
CKE0
CKE1
BA0
BA1
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_B_DM[7..0]
M_B_RAS# 10
M_B_WE# 10
M_B_CAS# 10
SC10U10V5ZY-1GP
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
CS0#
CS1#
NP1
NP2
110
113
115
1
109
108
10 M_B_BS0
10 M_B_BS1
10 M_B_DQ[63..0]
NP1
NP2
RAS#
WE#
CAS#
2
10 M_B_BS2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
1
D
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
+V_DDR_REF
2
DM2
B
DDR3-204P-55-GP
62.10017.Q31
SEC. 62.10017.N71
x01 change tolerant 20091117
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR3-SODIMM2
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
A00
Berry
Sheet
1
19
of
92
5
4
3
2
1
+3.3V_RUN
UMA
L_BKLTCTL
LDDC_CLK_PCH
LDDC_DATA_PCH
4
3
SRN0J-6-GP
LCTRL_CLK
LCTRL_DATA
1
LIBG
R2002
DY
1 PCH_LCDVDD_EN
L_DDC_CLK
L_DDC_DATA
AB46
V48
L_CTRL_CLK
L_CTRL_DATA
AP39
AP41
LVD_IBG
LVD_VBG
1LVDS_VBG
RN2004
1
4 LVD_VREFH AT43
2
3 LVD_VREFL AT42
R2001
2K37R2F-GP
Place near PCH
UMA
TP2001
UMA
LVD_VREFH
LVD_VREFL
55 PCH_LVDSA_TXC#
55 PCH_LVDSA_TXC
AV53
AV51
LVDSA_CLK#
LVDSA_CLK
55 PCH_LVDSA_TX0#
55 PCH_LVDSA_TX1#
55 PCH_LVDSA_TX2#
BB47
BA52
AY48
AV47
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
55 PCH_LVDSA_TX0
55 PCH_LVDSA_TX1
55 PCH_LVDSA_TX2
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
55 PCH_LVDSB_TXC#
55 PCH_LVDSB_TXC
AP48
AP47
LVDSB_CLK#
LVDSB_CLK
55 PCH_LVDSB_TX0#
55 PCH_LVDSB_TX1#
55 PCH_LVDSB_TX2#
AY53
AT49
AU52
AT53
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
55 PCH_LVDSB_TX0
55 PCH_LVDSB_TX1
55 PCH_LVDSB_TX2
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
AA52
AB53
AD53
CRT_BLUE
CRT_GREEN
CRT_RED
+3.3V_RUN
4
3
2
1
Impedance:85 ohm
UMA
5
6
7
8
C
RN2002
SRN2K2J-4-GP
LCTRL_DATA
LCTRL_CLK
LDDC_CLK_PCH
LDDC_DATA_PCH
Close to ball <600mil
5
6
7
8
Need Level Shift
UMA
77 PCH_CRT_DDCCLK
77 PCH_CRT_DDCDATA
77 PCH_CRT_HSYNC
77 PCH_CRT_VSYNC
V51
V53
CRT_DDC_CLK
CRT_DDC_DATA
Y53
Y51
CRT_HSYNC
CRT_VSYNC
4
3
2
1
RN2005
SRN150F-1-GP
1
2.5V Tolerance
B
CRT_IREF AD48
AB51
DAC_IREF
CRT_IRTN
SDVO_STALLN
SDVO_STALLP
BJ48
BG48
SDVO_INTN
SDVO_INTP
BF45
BH45
RN2006
UMASRN2K2J-1-GP
D
R2007
T51
T53
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
BG44
BJ44
AU38
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
DDPC_CTRLCLK
DDPC_CTRLDATA
Y49
AB49
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
BE44
BD44
AV40
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
77 PCH_CRT_BLUE
77 PCH_CRT_GREEN
77 PCH_CRT_RED
BJ46
BG46
SDVO_CTRLCLK
SDVO_CTRLDATA
SRN0J-6-GP
2
2
100KR2J-1-GP
TPAD14-GP
AB48
Y45
SDVO_TVCLKINN
SDVO_TVCLKINP
1
2
1
2
54,82 GPU_LVDS_CLK
54,82 GPU_LVDS_DATA
55 PCH_LBKLT_CTL
Y48
Digital Display Interface
D
L_BKLTEN
L_VDD_EN
LVDS
RN2001
T48
T47
4
3
4 OF 10
U2001D
55 PCH_VGA_BLEN
55 PCH_LCDVDD_EN
PCH_HDMI_CLK 57
PCH_HDMI_DATA 57
HDMI_PCH_DET
HDMI_DATA2#_C
HDMI_DATA2_C
HDMI_DATA1#_C
HDMI_DATA1_C
HDMI_DATA0#_C
HDMI_DATA0_C
HDMI_CLK#_C
HDMI_CLK_C
UMA1
UMA1
UMA1
UMA1
UMA1
UMA1
UMA1
UMA1
2
2
2
2
2
2
2
2
C2001
C2002
C2003
C2004
C2005
C2006
C2007
C2008
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
57
HDMI_PCH_DATA2# 57,82
HDMI_PCH_DATA2 57,82
HDMI_PCH_DATA1# 57,82
HDMI_PCH_DATA1 57,82
HDMI_PCH_DATA0# 57,82
HDMI_PCH_DATA0 57,82
HDMI_PCH_CLK# 57,82
HDMI_PCH_CLK 57,82
Close to VGA
C
Impedance:85 ohm
Impedance:100 ohm
U50
U52
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
BC46
BD46
AT38
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
B
IBEXPEAK-M-GP-NF
2
1KR2J-1-GP
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (LVDS/CRT/DDI)
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Document Number
Rev
Berry
Date:
Monday, March 29, 2010
A00
Sheet
1
20
of
92
SSID = PCH
+3.3V_RUN
SRN8K2J-2-GP-U
RN2103
INT_PIRQH#
INT_PIRQB#
INT_PIRQF#
PCI_REQ3#
D
1
2
3
4
5
+3.3V_RUN
10
9
8
7
6
PCI_REQ1#
PCI_PLOCK#
PCI_PERR#
PCI_REQ0#
+3.3V_RUN
SRN8K2J-2-GP-U
+3.3V_RUN
+3.3V_RUN
RN2102
1
2
3
4
PCI_STOP#
INT_PIRQE#
INT_PIRQC#
INT_PIRQG#
8
7
6
5
U2101
SRN8K2J-4-GP
9,37,70,76,78,80
PLT_RST#
5
VCC
4
Y
A
B
GND
DY
1
2
3
PCI_PLTRST#
1
NL17SZ08DFT2G-GP
BOOT BIOS Strap
PCI_GNT#1 PCI_GNT#0
C
2
DY
BOOT BIOS Location
1
R2101
2
0R0402-PAD
C2101
SC220P50V2KX-3GP
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
0
0
LPC
0
1
Reserved
1
0
PCI
1
1
SPI(Default)
TPAD14-GP
TPAD14-GP
TPAD14-GP
RN2104
USB_OC#2_3
SMC_W AKE_SCI#_R
USB_OC#6_7
USB_OC#0_1
+3.3V_ALW
1
2
3
4
5
10
9
8
7
6
USB_OC#12_13
USB_OC#8_9
USB_OC#10_11
USB_OC#4_5
TP2102
TP2103
TP2104
1
1
1
+3.3V_ALW
U2001E
5 OF 10
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
AY9
BD1
AP15
BD8
NV_DQS0
NV_DQS1
AV9
BG8
NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
NV_ALE
NV_CLE
BD3
AY6
NV_RCOMP
AU2
NV_RB#
AV7
J50
G42
H47
G34
C/BE0#
C/BE1#
C/BE2#
C/BE3#
NV_WR#0_RE#
NV_WR#1_RE#
AY8
AY5
G38
H51
B37
A44
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
F51
A46
B45
M53
REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
F48
K45
F36
H53
GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
B41
K53
A36
A48
SRN8K2J-2-GP-U
TPAD14-GP
TP2110
1
R2105
PCI_GNT3#
1
DY
PCIRST#
PCI_SERR#
PCI_PERR#
2
K6
E44
E50
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCIRST#
SERR#
PERR#
4K7R2J-2-GP
PCI_IRDY#
B
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default
TPAD14-GP
70 PCLK_FW H
23 CLK_PCI_FB
37 PCLK_KBC
2
2 22R2J-2-GP
2 22R2J-2-GP
22R2J-2-GP
1
PCI_DEVSEL#
PCI_FRAME#
A42
H44
F46
C46
IRDY#
PAR
DEVSEL#
FRAME#
PCI_PLOCK#
D49
PLOCK#
PCI_STOP#
PCI_TRDY#
D41
C48
STOP#
TRDY#
PCH_PME#
M7
PME#
PCI_PLTRST#
D5
PLTRST#
PCLK_FW H_R
CLK_PCI_FB_R
PCLK_KBC_R
2
R2107
R2108
R2109
1
1
1
TP2115
N52
P53
P46
P51
P48
NV_WE#_CK0
NV_WE#_CK1
+V_NVRAM_VCCQ
DMI Termination Voltage
NV_CLE
1
PCI_FRAME#
PCI_REQ2#
INT_PIRQD#
PCI_SERR#
Set to Vss when low.
Set to Vcc when high.
R2102
DY1KR2J-1-GP
2
+3.3V_RUN
10
9
8
7
6
1
NV_CLE
D
+V_NVRAM_VCCQ
1
1
2
3
4
5
NVRAM
PCI_TRDY#
PCI_DEVSEL#
INT_PIRQA#
PCI_IRDY#
2
Danbury Technology:
Disabled when Low.
Enable when High.
NV_ALE
NV_CLE
NV_RCOMP 1
R2103
DY1KR2J-1-GP
2
3
USB
4
PCI
5
RN2101
NV_ALE
TP2105
TPAD14-GP
USB
AV11
BF5
Device
Pair
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
USBRBIAS#
B25
USBRBIAS
D25
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
N16
J16
F16
L16
E14
G16
F12
T15
USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
77
77
77
77
76
76
0
USB2 (CRT Board)
1
USB3 (CRT Board)
2
WLAN (I/O Board)
3
X
USB_PN4
USB_PP4
USB_PN5
USB_PP5
78
78
73
73
4
CARD READER
5
BLUETOOTH
6
X
C
7
X
8
USB1 (I/O Board)
9
ESATA (I/O Board COMBO)
10
X
USB_PN11 76
USB_PP11 76
11
W-WAN (I/O Board)
USB_PN13 54
USB_PP13 54
13
USB_PN8
USB_PP8
USB_PN9
USB_PP9
76
76
76
76
12
X
CAMERA
B
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
USB_RBIAS_PN
1
2
R2106
22D6R2F-L1-GP
USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
SMC_W AKE_SCI#_R
USB_OC#0_1 63
USB_OC#8_9 63
EC2101
IBEXPEAK-M-GP-NF
1
DY SC4D7P50V2CN-1GP
KBC CLK EMI
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (PCI/USB/NVRAM)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
21
of
92
5
4
3
2
1
SSID = PCH
RN2201
3 OF 10
U2001C
8
8
8
8
DMI_CTX_PRXN0
DMI_CTX_PRXN1
DMI_CTX_PRXN2
DMI_CTX_PRXN3
BC24
BJ22
AW20
BJ20
8
8
8
8
DMI_CTX_PRXP0
DMI_CTX_PRXP1
DMI_CTX_PRXP2
DMI_CTX_PRXP3
BD24
BG22
BA20
BG20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_PTX_CRXN0
DMI_PTX_CRXN1
DMI_PTX_CRXN2
DMI_PTX_CRXN3
8
8
8
8
DMI_PTX_CRXP0
DMI_PTX_CRXP1
DMI_PTX_CRXP2
DMI_PTX_CRXP3
BD22
BH21
BC20
BD18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BH25
DMI_ZCOMP
+1.05V_VTT
R2202
1
DMI_IRCOMP_R
2
BF25
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
FDI_PCH_TXN0
FDI_PCH_TXN1
FDI_PCH_TXN2
FDI_PCH_TXN3
FDI_PCH_TXN4
FDI_PCH_TXN5
FDI_PCH_TXN6
FDI_PCH_TXN7
FDI_PCH_TXP0
FDI_PCH_TXP1
FDI_PCH_TXP2
FDI_PCH_TXP3
FDI_PCH_TXP4
FDI_PCH_TXP5
FDI_PCH_TXP6
FDI_PCH_TXP7
FDI_FSYNC0
BF13
FDI_FSYNC0_C
FDI_FSYNC1
BH13
FDI_FSYNC1_C
FDI_LSYNC0
BJ12
FDI_LSYNC0_C
FDI_LSYNC1
BG14
FDI_LSYNC1_C
1
FDI_PCH_TXN4
FDI_PCH_TXP4
FDI_PCH_TXP0
FDI_PCH_TXN0
1
2
3
4
FDI_PCH_TXP6
FDI_PCH_TXN6
FDI_PCH_TXN2
FDI_PCH_TXP2
SRN0J-7-GP
RN2203
1
2
3
4
FDI_PCH_TXN7
FDI_PCH_TXP7
FDI_PCH_TXP5
FDI_PCH_TXN5
1
2
3
4
UMA
8
7
6
5
FDI_TXP3
FDI_TXN3
FDI_TXN1
FDI_TXP1
8
8
8
8
UMA
8
7
6
5
FDI_TXN4
FDI_TXP4
FDI_TXP0
FDI_TXN0
8
8
8
8
UMA
8
7
6
5
FDI_TXP6
FDI_TXN6
FDI_TXN2
FDI_TXP2
8
8
8
8
8
7
6
5
FDI_TXN7
FDI_TXP7
FDI_TXP5
FDI_TXN5
8
8
8
8
8
7
6
5
FDI_LSYNC1
FDI_FSYNC1
FDI_LSYNC0
FDI_FSYNC0
D
SRN0J-7-GP
RN2204
2
UMA 0R2J-2-GP
BJ14
DMI_IRCOMP
49D9R2F-GP
FDI_INT_C
FDI_INT
1
2
3
4
SRN0J-7-GP
RN2202
R2201
FDI
8
8
8
8
BE22
BF21
BD20
BE18
DMI
D
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_PCH_TXP3
FDI_PCH_TXN3
FDI_PCH_TXN1
FDI_PCH_TXP1
FDI_INT
8
UMA
SRN0J-7-GP
RN2205
FDI_LSYNC1_C
FDI_FSYNC1_C
FDI_LSYNC0_C
FDI_FSYNC0_C
1
2
3
4
UMA
8
8
8
8
SRN0J-7-GP
C
C
9,23 XDP_DBRESET#
T6
SYS_RESET#
WAKE#
M6
SYS_PWROK
CLKRUN#/GPIO32
J12
PCIE_W AKE# 76
X02-20091222
Y1
+3.3V_ALW
PM_CLKRUN# 37
PM_PW RGD
1
2
0R0402-PAD
37 PM_PW ROK
1 R2206 2
0R0402-PAD
RN2207
3
4
2
1
X02-20091224
SRN10KJ-5-GP
TPAD14-GP
X02-20091222
9 PM_DRAM_PW RGD
37 SUS_PW R_DN_ACK
9 PM_PW RBTN#_R
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
1
D9
PM_RSMRST#_R
C16
SUS_PW R_ACK
M1
DRAMPWROK
RSMRST#
SUS_PWR_DN_ACK/GPIO30
R2218
1
2
0R0402-PAD
37 PM_PW RBTN#
B
MEPW ROK
LAN_RST#1
TP2206
R2213
1
2
0R0402-PAD
R2215
1
2
0R0402-PAD
37 PCH_RSMRST#
X02-20091222
R2219
1
2
0R0402-PAD
37 AC_PRESENT_EC
PM_BATLOW #_R
PM_RI#
PM_PW RBTN#_R
P5
AC_PRESENT
P7
A6
F14
System Power Management
R2204
PWRBTN#
ACPRESENT/GPIO31
BATLOW#/GPIO72
RI#
RN2206
SUS_STAT#/GPIO61
P8
PM_SUS_STAT# 1
SUSCLK/GPIO62
F3
PCH_SUSCLK
SLP_S5#/GPIO63
E4
SLP_S4#
H7
PM_SLP_S4#_R
SLP_S3#
P12
PM_SLP_S3#_R
SLP_M#
K8
SIO_SLP_M#_R
1
TP23
N2
PM_SLP_DSW #
1
BJ10
H_PM_SYNC
F6
PM_SLP_LAN#
PM_BATLOW #_R
PM_RI#
AC_PRESENT_EC
SUS_PW R_ACK
TP2201
TPAD14-GP
1
2
3
4
A00-20100204
PCH_SLP_S5#
1
R2209
1
R2211
1
8
7
6
5
SRN10KJ-6-GP
2
0R0402-PAD
2
10R2J-2-GP
PCH_SUSCLK_2102 39
PCH_SUSCLK_KBC
PCIE_W AKE#
2
0R0402-PAD
PM_SLP_S4# 37,50
1
R2216
2
0R0402-PAD
PM_SLP_S3# 37,42,47,50,51,89
1
2
R2210
37
TP2202
TPAD14-GP
1
R2214
1KR2J-1-GP
R2217
PCH_RSMRST#
1
2
10KR2J-3-GP
PMSYNCH
SLP_LAN#/GPIO29
TP2203TPAD14-GP
X02-20091222
B
TP2204TPAD14-GP
H_PM_SYNC
9
1
+3.3V_RUN
TP2205TPAD14-GP
IBEXPEAK-M-GP-NF
PM_CLKRUN# 1
1
2
R2221
10KR2J-3-GP
R2220
10KR2J-3-GP
DY
2
Option to " Disable " clkrun.
Pulling it down will keep the clks running.
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (DM I/FDI/PM)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
22
of
92
5
4
3
2
1
SSID = PCH
+3.3V_ALW
AT34
AU34
AU36
AV36
PERN7
PERP7
PETN7
PETP7
PCIECLKRQ0#/GPIO73
AH42
AH41
R2304
1
PCIE_CLK_RQ3#
10KR2J-3-GP
CLKOUT_PCIE2N
CLKOUT_PCIE2P
A8
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE5N
CLKOUT_PCIE5P
H6
PCIECLKRQ5#/GPIO44
PEG_B_CLKRQ#
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ#/GPIO56
RN2307
1
2
3
4
8
7
6
5
T11
CL_DATA 1
CL_RST1#
T9
CL_RST# 1
W W AN_CLKREQ#
PCIE_CLK_RQ0#
PEG_B_CLKRQ#
PCIE_CLK_RQ5#
4
3
UMA
1
TP2302 TPAD14-GP
PEG_CLKREQ#_C
H1
PEG_CLKREQ#_C
TP2303 TPAD14-GP
SML0_DATA
KBC_SCL1
TP2304 TPAD14-GP
SML0_CLK
KBC_SDA1
1
R2310
DY
DIS
2
0R2J-2-GP
PEG_CLKREQ# 82
AD43
AD45
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA# 80
CLK_PCIE_VGA 80
CLKOUT_DMI_N
CLKOUT_DMI_P
AN4
AN2
CLK_EXP_N
CLK_EXP_P
CLK_EXP_N 9
CLK_EXP_P 9
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
AT1
AT3
R2308
10KR2J-3-GP
R2309
10KR2J-3-GP
C
+3.3V_RUN
RN2303
2
1
3
4
SRN2K2J-1-GP
AW24
BA24
CLKIN_DMI#
CLKIN_DMI
CLKIN_DMI# 7
CLKIN_DMI 7
CLKIN_BCLK_N
CLKIN_BCLK_P
AP3
AP1
CLK_CPU_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK# 7
CLK_CPU_BCLK 7
CLKIN_DOT_96N
CLKIN_DOT_96P
F18
E18
CLKIN_DMI_N
CLKIN_DMI_P
Q2301
AH13
AH12
CLK_PCH_14M
CLK_PCH_14M 7
CLKIN_PCILOOPBACK
J42
CLK_PCI_FB
CLK_PCI_FB
XTAL25_IN
XTAL25_OUT
AH51
AH53
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
AF38
XCLK_RCOMP
T45
CLKOUTFLEX1/GPIO65
P43
CLKOUTFLEX2/GPIO66
T42
CLK_PCH_GPIO64
6
1
5
2
4
3
84.27002.F3F
21
B
DIS uses 0ohm 63.R0034.1DL
UMA uses 12pF 78.12034.1FL
R2306 1
1
2 90D9R2F-1-GP
+1.05V_VTT
C2308
XTAL25_IN
TP2301 TPAD14-GP
2
UMA
CLK48_GPIO
N50
PCH_SMBCLK 7,18,19,76
PCH_SMB_CLK
X01 20091118
CLKOUTFLEX3/GPIO67
PCH_SMBDATA 7,18,19,76
2N7002EDW -GP
CLK_PCIE_SATA# 7
CLK_PCIE_SATA 7
P41
CLKOUTFLEX0/GPIO64
PCH_SMB_DATA
CLK_DREF# 7
CLK_DREF 7
REFCLK14IN
PCIECLKRQ4#/GPIO26
AK53
AK51
+3.3V_ALW
CL_DATA1
CLKOUT_PCIE4N
CLKOUT_PCIE4P
AJ50
AJ52
PCIE_CLK_RQ5#
CL_CLK
CLKOUT_PCIE3N
CLKOUT_PCIE3P
M9
76 W W AN_CLKREQ#
T13
CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P
PCIECLKRQ2#/GPIO20
AM51
AM53
76 CLK_PCIE_W W AN#
76 CLK_PCIE_W W AN
CL_CLK1
KBC_SDA1 37
RN2301
SRN2K2J-1-GP
R2303
1M1R2J-GP
UMA
1
B
PCIECLKRQ1#/GPIO18
AM47
AM48
76 CLK_PCIE_LAN#
76 CLK_PCIE_LAN
2
CLKOUT_PCIE1N
CLKOUT_PCIE1P
U4
N4
KBC_SDA1
+3.3V_ALW
RN2309
SRN2K2J-1-GP
2
P9
76 W LAN_CLKREQ#
G12
KBC_SCL1 37
2
CLKOUT_PCIE0N
CLKOUT_PCIE0P
AM43
AM45
76 CLK_PCIE_W LAN#
76 CLK_PCIE_W LAN
SML1DATA/GPIO75
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PERN8
PERP8
PETN8
PETP8
AK48
AK47
PCIE_CLK_RQ1#
KBC_SCL1
SML0_DATA 9
1
XTAL25_OUT
X01 2009/11/06
1
COLAY
SC12P50V2JN-3GP
X2301
XTAL-25MHZ-96GP
C2307
1
BG34
BJ34
BG36
BJ36
PCIE_CLK_RQ0#
E10
PEG_A_CLKRQ#/GPIO47
C
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW.
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN
SML1CLK/GPIO58
4
3
PERN6
PERP6
PETN6
PETP6
LPD_SPI_INTR#
+3.3V_ALW
1
BA34
AW34
BC34
BD34
x01 change tolerant 20091117
SML1ALERT#/GPIO74
M14
PCH_SMB_DATA
SML0_CLK 9
2
PERN5
PERP5
PETN5
PETP5
SML0DATA
SML0_DATA
D
PCH_SMB_CLK
1
BF33
BH33
BG32
BJ32
SML0_CLK
1
10KR2J-3-GP
2
W-WAN
C6
G8
LPD_SPI_INTR#
2
R2311
RN2302
SRN2K2J-1-GP
4
3
PERN4
PERP4
PETN4
PETP4
SML0CLK
1
10KR2J-3-GP
1
2
BA32
BB32
BD32
BE32
PCIE_C_TXN4
PCIE_C_TXP4
TPM_ID1
SML0ALERT#/GPIO60
2
R2305
1
2
2
2
LAN
J14
WLAN
SMBus
C2304 SCD1U10V2KX-5GP 1
C2305 SCD1U10V2KX-5GP 1
PCIE_C_TXN3
PCIE_C_TXP3
PERN3
PERP3
PETN3
PETP3
PCH_SMB_DATA
Link
76 PCIE_RXN4
76 PCIE_RXP4
76 PCIE_TXN4
76 PCIE_TXP4
2
2
AU30
AT30
AU32
AV32
C8
SMBDATA
Controller
C2303 SCD1U10V2KX-5GP 1
C2306 SCD1U10V2KX-5GP 1
PCIE_C_TXN2
PCIE_C_TXP2
PERN2
PERP2
PETN2
PETP2
TPM_ID1
PCH_GPIO11 25
PCH_SMB_CLK
PEG
76 PCIE_RXN3
76 PCIE_RXP3
76 PCIE_TXN3
76 PCIE_TXP3
2
2
AW30
BA30
BC30
BD30
B9
H14
SMBCLK
PCI-E*
C2301 SCD1U10V2KX-5GP 1
C2302 SCD1U10V2KX-5GP 1
SMBALERT#/GPIO11
From CLK BUFFER
76 PCIE_RXN2
76 PCIE_RXP2
76 PCIE_TXN2
76 PCIE_TXP2
PERN1
PERP1
PETN1
PETP1
Clock Flex
D
U2001B
BG30
BJ30
BF29
BH29
1
2
+3.3V_ALW
2 OF 10
2
1
UMA
SC12P50V2JN-3GP
TP2307 TPAD14-GP
X01 2009/11/05
IBEXPEAK-M-GP-NF
SRN10KJ-6-GP
A
+3.3V_RUN
<Core Design>
RN2308
4
3
2
1
5
6
7
8
XDP_DBRESET#
W LAN_CLKREQ#
INT_SERIRQ
PCIE_CLK_RQ1#
A
XDP_DBRESET# 9,22
Wistron Corporation
INT_SERIRQ
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
24,37
Title
SRN10KJ-6-GP
PCH (PCI-E/SMBUS/CLOCK/CL)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
23
of
92
5
4
R2402
1
2
2
3
2
4
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable internal VRs
C2402
SC1U6D3V2KX-GP
1
C2403
SC15P50V2JN-2-GP
2
1
+RTC_CELL
PCH_RTCX1
PCH_RTCX2
B13
D13
RTCX1
RTCX2
PCH_RTCRST#
C14
RTCRST#
SRTCRST#
D17
SRTCRST#
X-32D768KHZ-65-GP
1
+RTC_CELL
1
SM_INTRUDER#
A16
INTRUDER#
2
PCH_INTVRMEN
330KR2F-L-GP
A14
INTVRMEN
ACZ_BIT_CLK
A30
HDA_BCLK
ACZ_SYNC_R
D29
X01 20091118 layout swap
30 PCH_AZ_CODEC_SYNC
30 PCH_SDOUT_CODEC
1
2
4
3
ACZ_SYNC_R
ACZ_SDATAOUT_R
ACZ_RST#_R
SRN33J-5-GP-U
C
30 PCH_AZ_CODEC_RST#
30 PCH_AZ_CODEC_BITCLK
P1
30 ACZ_SPKR
RN2403
RN2402
SRN33J-5-GP-U
1
4
2
3
30 PCH_SDIN_CODEC
ACZ_RST#_R
ACZ_BIT_CLK
ACZ_SDATAOUT_R
37 ME_UNLOCK#
HDA_SYNC
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN#/GPIO33
J30
HDA_DOCK_RST#/GPIO13
NO REBOOT STRAP
No Reboot Strap R23
1
R2410
DY
2 ACZ_SPKR
1KR2J-1-GP
Low = Default
HDA_SPKR High = No Reboot
TPAD14-GP
TP2404
1
PCH_JTAG_TCK
M3
JTAG_TCK
TPAD14-GP
TP2405
1
PCH_JTAG_TMS
K3
JTAG_TMS
TPAD14-GP
TP2406
1
PCH_JTAG_TDI
K1
JTAG_TDI
TPAD14-GP
TP2407
1
PCH_JTAG_TDO
J2
JTAG_TDO
TPAD14-GP
TP2408
1
PCH_JTAG_RST#
J4
FWH4/LFRAME#
C34
LDRQ0#
LDRQ1#/GPIO23
A34
F34
SERIRQ
AB9
LPC_LAD[0..3]
D
37,70
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME# 37,70
INT_SERIRQ
23,37
x01 Change tolerant 20091117
TRST#
JTAG
+3.3V_RUN
LPC
2
1M1R2J-GP
1
R2404
SATA
R2407
RTC
2
1
G2401
GAP-OPEN
IHDA
X01
2
X01
2
20KR2J-L2-GP
C2404
SC1U6D3V2KX-GP
D33
B33
C32
A32
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
R2403
1
82.30001.A41
LPC_LAD[0..3]
1 OF 10
U2001A
C2401
SC15P50V2JN-2-GP
2
D
SSID = PCH
20KR2J-L2-GP
X2401
1
1
R2401
1
PCH_RTCX2
2
10MR2J-L-GP
2
+RTC_CELL
PCH_RTCX1
1
3
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AK7
AK6
AK11
AK9
SATA_TXN0_C C2409 1
SATA_TXP0_C C2410 1
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
SATA_RXN0_C 59
SATA_RXP0_C 59
SATA_TXN0 59
SATA_TXP0 59
HDD
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AH6
AH5
AH9
AH8
SATA_TXN1_C C2405 1
SATA_TXP1_C C2406 1
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
SATA_RXN1_C 59
SATA_RXP1_C 59
SATA_TXN1 59
SATA_TXP1 59
ODD
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF11
AF9
AF7
AF6
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AH3
AH1
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD9
AD8
AD6
AD5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AD3
AD1
AB3
AB1
C
SATA_TXN4_C C2407 1
SATA_TXP4_C C2408 1
SATA_RXN4_C 76
SATA_RXP4_C 76
SATA_TXN4 76
SATA_TXP4 76
ESATA
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
+1.05V_VTT
SATAICOMPO
AF16
SATAICOMPI
AF15
R2412
SATAICOMP 1
2
+3.3V_RUN
37D4R2F-GP
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_RST#
PCH_SPI_CLK
R2413
1
2 15R2J-GP
SPI_CLK_R
BA2
SPI_CLK
62 PCH_SPI_CS0#
PCH_SPI_CS0#
R2414
1
2 15R2J-GP
SPI_CS#0_R
AV3
SPI_CS0#
1
2
0R2J-2-GP
SPI_CS1#
AY3
SPI_CS1#
SATALED#
T3
SPI_MOSI_R
AY1
SPI_MOSI
SATA0GP/GPIO21
Y9
SATA_DET#0_R
AV1
SPI_MISO
SATA1GP/GPIO19
V1
SATA_DET#1_R
2
DY
1
DY
1
EC2402
SCD1U10V2KX-5GP
2
R2415
EC2401
SC22P50V2JN-4GP
62 PCH_SPI_DO
PCH_SPI_DO
62 PCH_SPI_DI
PCH_SPI_DI
R2416
1
DY
2 15R2J-GP
4
3
62 PCH_SPI_CLK
RN2401
SRN10KJ-5-GP
SPI
B
B
SATA_LED# 66
1
2
For EMI
IBEXPEAK-M-GP-NF
x01 Change tolerant 20091117
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
24
of
92
5
4
3
2
1
SSID = PCH
6 OF 10
U2001F
37 SIO_EXT_SCI#
Y3
C38
TACH1/GPIO1
PCH_GPIO6
D37
TACH2/GPIO6
SIO_EXT_W AKE#
J32
TACH3/GPIO7
SIO_EXT_SMI#
F10
GPIO8
D
37 SIO_EXT_W AKE#
PCH_GPIO12
K9
LAN_PHY_PWR_CTRL/GPIO12
HOST_ALTERT#1
T7
GPIO15
10
PCH_GPIO38
9
DGPU_HOLD_RST#
8
S_GPIO
7
6 PCH_TEMP_ALERT#_C
BCLK_CPU_N 9
AM1
BCLK_CPU_P 9
PCH_GPIO24
H10
GPIO24
PCH_GPIO27
AB12
GPIO27
PCH_GPIO28
V13
GPIO28
STP_PCI#
M11
STP_PCI#/GPIO34
1
9 S3_RST_GATE#
1
C2503
+3.3V_RUN
2
SCD047U16V2KX-1-GP
1 R2510 2
0R0402-PAD
37 PCH_TEMP_ALERT#
TPAD14-GP
TP2503
1
2
3
4
DY
AW22
PCH_GPIO38
V3
SLOAD/GPIO38
TP3
BB22
PCH_GPIO39
P3
SDATAOUT0/GPIO39
TP4
AY45
PCH_GPIO45
H3
PCIECLKRQ6#/GPIO45
TP5
AY46
F1
PCIECLKRQ7#/GPIO46
TP6
AV43
SDATAOUT1/GPIO48
TP7
AV45
PCH_TEMP_ALERT#_C
AA4
SATA5GP/GPIO49
TP8
AF13
GPIO57
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
TP13
AK42
TP14
M32
TP15
N32
TP16
M30
TP17
N30
TP18
H12
PCH_NCTF_1
1
100KR2J-1-GP
RN2501
PCH_GPIO12
SIO_EXT_SMI#
PCH_GPIO28
HOST_ALTERT#1
1
2
3
4
5
10
9 S3_RST_GATE#
PCH_GPIO45
8
7
PCH_GPIO57
6
TPAD14-GP
TP2504
1
PCH_NCTF_2
TPAD14-GP
TP2505
1
PCH_NCTF_3
PCH_GPIO11 23
SRN10KJ-L3-GP
+3.3V_ALW
TPAD14-GP
TP2507
GPIO
BA22
TP2
AB6
1
1
PCH_NCTF_4
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
R2504
56R2J-4-GP
37
H_PW RGD 9,42
PCH_THERMTRIP_R
1
R2506
2
54D9R2F-L1-GP
H_THERMTRIP# 9,37,42,82
PCH
SATACLKREQ#/GPIO35
TP1
F8
H_PECI 9
SIO_RCIN#
Placed Within 2" from
SATA3GP/GPIO37
+3.3V_ALW
2
R2515
BD10
SATA2GP/GPIO36
SRN10KJ-6-GP
PCH_GPIO24
BE10
THRMTRIP#
AB7
8
7
6
5
B
PROCPWRGD
AB13
RN2504
PCH_GPIO17
PCH_GPIO6
SIO_EXT_SCI#
SIO_EXT_W AKE#
BG10
T1
PCH_GPIO37
X02-20091222
1
2
PECI
RCIN#
PCH_GPIO36
PCH_GPIO57
4
3
V6
SCLOCK/GPIO22
PCH_GPIO48
RN2503
PCH_GPIO39
STP_PCI#
SRN100KJ-6-GP
+1.05V_VTT
2
AM3
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
1
1
2
+3.3V_RUN
SIO_A20GATE 37
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CPU
TP2502
R2508
10KR2J-3-GP
C
U2
TACH0/GPIO17
CLK_SATA_OE#
SRN10KJ-L3-GP
A20GATE
D
SATA4GP/GPIO16
RN2502
1
2
3
4
5
AF48
AF47
F38
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
NCTF
TPAD14-GP
+3.3V_RUN
PCH_GPIO22
PCH_GPIO37
PCH_GPIO36
PCH_GPIO48
CLKOUT_PCIE7N
CLKOUT_PCIE7P
AA2
Y7
1
2
DY
AH45
AH46
PCH_GPIO17
PCH_GPIO22
C2502
SC47P50V2JN-3GP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
DGPU_HOLD_RST#
RSVD
1
37 SIO_EXT_SMI#
DY
2
C2501
SC47P50V2JN-3GP
BMBUSY#/GPIO0
SIO_EXT_SCI#
MISC
S_GPIO
TP19
AA23
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
NC_5
T39
INIT3_3V#
TP24
P6
C
B
INIT3_3V#
1
TP2506TPAD14-GP
C10
IBEXPEAK-M-GP-NF
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (GPIO/CPU)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
25
of
92
5
4
3
2
1
SSID = PCH
+3.3V_RUN
DIS
1
R2601
1
+3VS_VCCA_LVD
VSSA_LVDS
AH39
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
AP43
AP45
AT46
AT45
DIS
1
C2606
1
2
0R2J-2-GP
R2604
1
L2602
+1.8V_RUN
VCC3_3
AT22
TP2601
VCCFDIPLL
1
TPAD14-GP
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
1
1
2
2
1
2
2
1
0R2J-2-GP
C2609
X01 Change
SC10U6D3V5MX-3GP
location-20091116
3.3V CRT LDO
UMA
+5V_RUN
+3.3V_CRT_LDO
U2601
+3.3V_RUN
3
2
1
357mA
C2611
SCD1U10V2KX-5GP
VIN
GND
EN
VOUT
4
NC#5
5
DY
C2612
SC1U10V2KX-1GP
DY
RT9198-33PBG-GP
2
DY
C2613
SC1U6D3V2KX-GP
C
VCCIO
2
C2619
61mA
2
+1.8V_RUN
0R0402-PAD
A00-20100204
SC1U6D3V2KX-GP
R2607
0R0402-PAD
+V_NVRAM_VCCQ
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
1
156mA
+3.3V_RUN
1
1
DY R2608
0R2J-2-GP
C2620
SCD1U10V2KX-5GP
2
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
+1.05V_VTT
R2606
+1.05VS_VCC_DMI
2
VCCDMI
AU16
1
AT16
x01 change tolerant 20091117
X02-20091222
2
VCCDMI
35mA
1
VCCVRM
AT24
+3.3V_RUN
X02-20091222
1
B
VCCME3_3
VCCME3_3
VCCME3_3
VCCME3_3
R2609
0R0402-PAD
85mA
AM8
AM9
AP11
AP9
PCH_VCCME3_3
C2623
SCD1U10V2KX-5GP
2
IBEXPEAK-M-GP-NF
2
+1.05V_VTT
AD35
59mA
0R5J-5-GP
+1.8V_RUN
NAND / SPI
VCCAFDI_VRM
VCC3_3
UMA2
1
AN35
AB35
DY
1
R2611
Second 74.09091.H3F
FDI
357mA
B
VCC3_3
1
VCCIO
VCCIO
VCC3_3
UMA
C2608
D
0R2J-2-GP
300mA
0R3J-0-U-GP
2
AN30
AN31
HVCMOS
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
AB34
1
1
1
+3.3V_RUN
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
2
C2621
SCD1U10V2KX-5GP
2
1
x01 change tolerant 20091117
C2618
SC1U6D3V2KX-GP
2
1
C2617
UMA
SC1U6D3V2KX-GP
2
1
C2616
SC1U6D3V2KX-GP
2
C2615
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
UMA
2
C2614
1
x01 change tolerant 20091117
3.208A
VCCAPLLEXP
DMI
+1.05V_VTT
C
LVDS
BJ24
PCI E*
VCCAPLLEXP
C2607
SCD01U16V2KX-3GP
1 TPAD14-GP
R2605
DIS
1
R2602
UMA1
2
DY
+1.8VS_VCCTX_LVDS
SCD01U16V2KX-3GP
TP2602
VCCIO
UMA2
2
HCB1608KF-181-GP
+3.3V_RUN
2
R2603
SCD1U10V2KX-5GP
AK24
UMA
1
VCCALVDS
AH38
+3.3V_CRT_LDO
C2605
UMA
2
VSSA_DAC
AF51
C2604
2
AF53
UMA
1
VSSA_DAC
+VCCA_DAC_1_2
C2603
1
VCCADAC
AE52
2
CRT
2
+1.05V_VTT
VCC CORE
1
1
2
x01 change tolerant 20091117
AE50
2
0R2J-2-GP
69mA
7 OF 10
VCCADAC
SC10U6D3V5MX-3GP
C2601
SC1U6D3V2KX-GP
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
SCD1U10V2KX-5GP
DY
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
SCD01U16V2KX-3GP
C2602
SC10U6D3V5KX-1GP
D
POWER
U2001G
1.524A
2
+1.05V_VTT
X02-20091222
+1.8V_RUN
R2610
VCCAFDI_VRM
1
2
0R0402-PAD
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (POWER1)
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Document Number
Rev
Berry
Date:
W ednesday, February 10, 2010
A00
Sheet
1
26
of
92
3
VCCACLK
VCCIO
VCCIO
VCCIO
VCCIO
V24
V26
Y24
Y26
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
DY
C2705
SC1U6D3V2KX-GP
VCCME
AF43
VCCME
AF41
VCCME
AF42
VCCME
V39
VCCME
V41
VCCME
V42
VCCME
Y39
VCCME
Y41
VCCME
Y42
VCCME
+1.8V_RUN
2
AU24
VCCVRM
C2717
SC1U6D3V2KX-GP
72mA +1.05VS_VCCA_A_DPL
73mA +1.05VS_VCCA_B_DPL
+1.05V_VTT
VCCADPLLA
VCCADPLLA
BD51
BD53
VCCADPLLB
VCCADPLLB
AH23
AJ35
AH35
VCCIO
VCCIO
VCCIO
AF34
VCCIO
V5REF
K49
VCC3_3
J38
VCC3_3
L38
VCC3_3
M36
VCC3_3
N36
VCC3_3
P36
VCC3_3
U35
VCC3_3
AD13
+3.3V_RUN
D2701
CH751H-40PT-GP
+1.05V_VTT
+5V_ALW
+5VALW _PCH_VCC5REFSUS
1
+5VS_PCH_VCC5REF
2
AH34
VCCIO
AF32
VCCIO
R2702
V12
DCPSST
+5V_RUN
1
Y22
DCPSUS
1
1
VCCSATAPLL
VCCSATAPLL
+3.3V_RUN
C2715
SC1U10V2KX-1GP
C2718
SCD1U10V2KX-5GP
+3.3V_RUN
x01 change tolerant 20091117
AK3
AK1
VCCSATAPLL
1
TPAD14-GP
TP2702
C2719
SCD1U10V2KX-5GP
x01 change tolerant 20091117
C2726
SCD1U10V2KX-5GP
VCCIO
AH22
VCCVRM
AT20
VCCIO
AH19
VCCIO
AD20
VCCIO
AF22
VCCIO
VCCIO
VCCIO
VCCIO
AD19
AF20
AF19
AH20
VCCIO
VCCIO
VCCIO
VCCIO
AB19
AB20
AB22
AD22
VCCME
VCCME
VCCME
VCCME
AA34
Y34
Y35
AA35
+1.8V_RUN
P18
VCCSUS3_3
U19
VCCSUS3_3
U20
VCCSUS3_3
B
+1.05V_VTT
C2727
SC1U6D3V2KX-GP
U22
+3.3V_RUN
2
C2729
SCD1U10V2KX-5GP
VCC3_3
V16
VCC3_3
Y16
VCC3_3
IBEXPEAK-M-GP-NF
VCCSUSHDA
L30
+1.05V_VTT
X02-20091222
+VCCSUSHDA
1
VCCRTC
HDA
A12
RTC
2
V_CPU_IO
CPU
1
V_CPU_IO
C2732
AU18
1 R2703 2
0R0402-PAD
6mA
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
C2733
SC1U6D3V2KX-GP
Title
Size
3
2
Document Number
PCH (POWER2)
Rev
Berry
x01 change tolerant 20091117
http://laptop-motherboard-schematic.blogspot.com/
4
A
+3.3V_ALW
C2735
2
1
1
2
C2734
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2mA
AT18
2
+RTC_CELL
1
1
2
A
C2731
SCD1U10V2KX-5GP
C2730
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
1mA
5
V15
x01 change tolerant 20091117
2
+1.05V_VTT
VCCSUS3_3
1
C2728
SCD1U10V2KX-5GP
2
1
163mA
SATA
+3.3V_ALW
PCI/GPIO/LPC
2
2
2
C2725
SCD1U10V2KX-5GP
2
10R2J-2-GP
R2701
1
+1.05VALW _INT_VCCSUS
x01 change tolerant 20091117
C
C2713
SC1U10V2KX-1GP
+VCCSST
B
D2702
CH751H-40PT-GP
2
10R2J-2-GP
1
1
C2722
SC1U6D3V2KX-GP
2
C2721
SC1U6D3V2KX-GP
2
C2720
SC1U6D3V2KX-GP
1
x01 change tolerant 20091117
BB51
BB53
V5REF_SUS
F24
C2709
SCD1U10V2KX-5GP
1
2
2
DY
V23
+3.3V_ALW
x01 change tolerant 20091117
2
1
C2716
SC10U6D3V5MX-3GP
DCPRTC
1
+1.05VS_VCCA_B_DPL
V9
U23
VCCIO
+3.3V_ALW
1
x01 change tolerant
+VCCRTCEXT
20091118
C2714
SCD1U10V2KX-5GP
L2703
1
2
IND-10UH-218-GP
1
2
C2712
SC1U6D3V2KX-GP
VCCSUS3_3
PCI/GPIO/LPC
2
DY
1
C2711
SC10U6D3V5MX-3GP
2
1
C
DY
1
+1.05VS_VCCA_A_DPL
1
2
IND-10UH-218-GP
2
2
SC10U6D3V5MX-3GP
2
C2710
SC1U6D3V2KX-GP
L2702
C2708
1
1
C2704
DY
X01 20091121
+1.05V_VTT
SC1U6D3V2KX-GP
C2707
SC10U6D3V5KX-1GP
1
1.998A
1
VCCME
AD41
Clock and Miscellaneous
+1.05V_VTT
2
VCCME
AD39
USB
x01 change tolerant 20091117
1
AD38
2
C2703
SCD1U10V2KX-5GP
D
C2706
SCD1U10V2KX-5GP
2
DCPSUSBYP
x01 change tolerant 20091117
1
Y20
1
DCPSUSBYP
+3.3V_ALW
2
VCCLAN
D
1
VCCLAN
AF24
2
AF23
2
VCCACLK
AP53
1
AP51
2
1 VCCACLK
TPAD14-GP
SSID = PCH
+1.05V_VTT
10 OF 10
2
TP2701
POWER
1
2
U2001J
2
1
4
1
5
Date:
W ednesday, February 10, 2010
A00
Sheet
1
27
of
92
5
4
3
SSID = PCH
D
8 OF 10
U2001H
C
B
AB16
VSS
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
IBEXPEAK-M-GP-NF
A
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
1
9 OF 10
U2001I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
D
C
B
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
IBEXPEAK-M-GP-NF
PCH (VSS)
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Document Number
Rev
Berry
Date:
W ednesday, February 10, 2010
A00
Sheet
1
28
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
29
of
92
5
4
3
2
1
SSID = AUDIO
+AVDD
+3.3V_RUN
1
2
0R0603-PAD
2 33R2J-2-GP
24 PCH_AZ_CODEC_RST#
TP3001
TP3002
1
1
10
PCH_AZ_CODEC_RST#
11
AUD_DMIC_CLK
AUD_DMIC_IN0
2
4
HDA_BITCLK
HDA_SDI
HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F
HDA_SDO
HDA_SYNC
HP1_PORT_B_L
HP1_PORT_B_R
HDA_RST#
PORT_C_L
PORT_C_R
VREFOUT_C
DMIC_CLK/GPIO1
DMIC0/GPIO2
SPKR_PORT_D_L+
SPKR_PORT_D_L-
DMIC1/GPIO0/SPDIF_OUT_1
2
46
SENSE_A
SENSE_B
48
AMP_MUTE#
37 AMP_MUTE#
47
EAPD
PORT_E_L
PORT_E_R
PUMP_CAPN
1
13
14
AUD_SENSE_A
AUD_SENSE_B
28
29
23
AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B
PORT_F_L
PORT_F_R
CAP-
1
2
1
2
C3009
SC1U10V2KX-1GP
2
1
SCD1U10V2KX-5GP
39
45
R3004
1
2
0R0603-PAD
AUD_AGND
X01 Change 0603 part-20091116
C3021
C3022
1 SC1U10V3KX-3GP
1 SC1U10V3KX-3GP
2
2
AUD_HP1_JACK_L
AUD_HP1_JACK_R
31
32
R3005 1
R3006 1
AUD_SPK_RAUD_SPK_R+
43
44
AUD_HP1_JACK_L2
AUD_HP1_JACK_R2
close to audio jack
1
2
C3011
SC1U10V3KX-3GP
AUD_VREFOUT_C
1
2
R3007
2K2R2J-2-GP
AUD_SPK_L+
AUD_SPK_L+ 60
AUD_SPK_LAUD_SPK_L- 60
40
41
60
2 60D4R2F-GP
2 60D4R2F-GP
AUD_INT_MIC_R_L
19
20
24
MIC_IN_L 60
MIC_IN_R 60
AUD_VREFOUT_B
AUD_SPK_RAUD_SPK_R+
INT_MIC_L_R
60
x01 change tolerant 20091117
C3012
2
1 SCD1U10V2KX-5GP
SB_SPKR_R
R3009
120KR2J-L-GP
1
2
From SB
ACZ_SPKR 24
C
60
60
1 SCD1U10V2KX-5GP
2
15
16
KBC_BEEP_R 1
R3010
2
470KR2J-2-GP
C3013
G3001
DUMMY-C2
17
18
60
60
Check
KBC_BEEP 37
From EC
AUD_PC_BEEP
PC_BEEP
CAP+
MONO_OUT
AUD_V_B
VREG
37
AUD_VREG
PVSS
49
GND
92HD79B1A5NLGXTAX-GP
AUD_AGND
X01 will change to 92HD79B1
P/N:71.92H79.003
C3017
AUD_AGND
$]DOLD,)(0,
AUD_AGND
AUD_AGND
C3016
SC1U6D3V2KX-GP
34
42
1
AUD_VREFFLT
V-
CAP2
2
AUD_CAP2
VREFFILT
SC4D7U6D3V3KX-GP
22
21
AVSS
AVSS
AVSS
1
DVSS
2
7
33
30
26
25
C3015
SC10U6D3V5MX-3GP
X01 20091117
AUD_PC_BEEP
Trace width>15 mils
12
C3018
SC10U6D3V5MX-3GP
36
PUMP_CAPP
1
C3023
SC1U10V2KX-1GP
2
2
1
C3014
SC2D2U10V3KX-1GP
1
2
35
1
AUD_VREFOUT_B
SPDIF_OUT_0
C3008
AUD_AGND
2
AMP_MUTE#
SPKR_PORT_D_RSPKR_PORT_D_R+
2
2
5
PCH_AZ_CODEC_SYNC
PVDD
PVDD
DVDD_IO
SC1U10V2KX-1GP
1
1
TPAD14-GP
TPAD14-GP
R3008
10KR2J-3-GP
8
PCH_SDOUT_CODEC
24 PCH_SDOUT_CODEC
24 PCH_AZ_CODEC_SYNC
+3.3V_RUN
PCH_SDIN_CODEC_C0
DVDD
27
38
2
24 PCH_SDIN_CODEC
R3001 1
6
AVDD
AVDD
R3003
1
2
0R0603-PAD
C3006
C3010
SC10U6D3V5MX-3GP
1
2
24 PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_BITCLK
DVDD_CORE
+5V_RUN
+PVDD
x01 change tolerant 20091117
1
1
9
3
C3007
SC4D7P50V2CN-1GP
SCD1U10V2KX-5GP
U3001
1
x01 change tolerant 20091117
DY
X02-20091222
C3005
C3001
SC10U6D3V5MX-3GP
2
2
1
AUD_DVDDCORE
C3004
SCD1U10V2KX-5GP
1
2
C3003
SC1U6D3V2KX-GP
1
2
C3002
SCD1U10V2KX-5GP
PCH_AZ_CODEC_BITCLK
D
R3002
Close to codec
Close to codec
C
+5V_RUN
X02-20091222
+3.3V_RUN
D
AUD_AGND
Close to codec
B
B
1
PCH_SDOUT_CODEC
X02-20091222
+AVDD
R3016
20KR2F-L-GP
1
2
1
PCH_AZ_CODEC_SDOUT1
AUD_HP1_JD#
60
2 R3014
2
C3020
SCD1U10V2KX-5GP
R3022
39K2R2F-L-GP
1
2
2 R3017
0R0603-PAD
1
R3021
20KR2F-L-GP
2 R3020
1
2
C3019
SC1000P50V3JN-GP-U
1
0R0603-PAD
1
AUD_SENSE_B
2
1
AUD_SENSE_A
R3019
2K49R2F-GP
2
R3018
2K49R2F-GP
1
2
DY
+AVDD
1
R3015
47R2J-2-GP
2
DY
EXT_MIC_JD# 60
0R0603-PAD
AUD_AGND
AUD_AGND
Close to Pin13
AUD_AGND
Close to Pin14
x01 change tolerant 20091117
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Audio Codec 92HD81B1
Document Number
Size
Custom
Date:
5
4
3
2
http://laptop-motherboard-schematic.blogspot.com/
Rev
A00
Berry
Sheet
Monday, March 29, 2010
1
30
of
92
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
31
of
92
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Custom
Rev
A00
Berry
Date:
Wednesday, February 10, 2010
Sheet
1
32
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
33
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
34
of
92
A
B
C
D
E
4
4
3
3
(Blanking)
2
2
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
A
http://laptop-motherboard-schematic.blogspot.com/
B
C
D
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
E
35
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
36
of
92
5
4
R3701
1
0R2J-2-GP
1
0R0603-PAD
PCB_VER0
KBC_BIOS_ID
1
DIS
90 1.0V_RUN_VGA_EN
2K2R2J-2-GP
PCB_VER1
66 PWRLED#
66 PWR_BTN_LED#
66 WHITE_LED#_KBC
68 KB_LED_BL_DET
22 PCH_RSMRST#
22,50 PM_SLP_S4#
A00-20100203
80 PLTRST_DELAY#
46 3V_5V_POK
22 PM_PWROK
62 EC_SPI_WP#_R
EC_ENABLE#
54 BLON_OUT
47 IMVP_VR_ON
76 PSID_DISABLE#
89 GFX_CORE_EN
24 ME_UNLOCK#
63 USB_PWR_EN#
GPIO01/TB2
GPIO03
GPIO06
GPIO07
GPIO23
GPIO24
GPIO30
GPIO31
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47
GPIO50/TDO
GPIO51
GPIO52/RDY#
GPIO53
GPIO70
GPIO71
GPIO72
GPO82/TRIS#
GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1
SMB
GPIO66/G_PWM
PANEL_BLEN
ECSWI#_KBC
1
UMA
68
67
69
70
9,25,42,82
2
GPIO
GPIO77
GPIO76/SHBM
GPIO75
GPIO81
SPI
GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
SER/IR
GPIO16
GPIO34
GPIO36
1.05VTT_PWRGD_KBC
1
R3723
S5_ENABLE 42
ECSCI#_KBC
2
0R0402-PAD
1.05VTT_PWRGD
X02-20091222
D3705
+3.3V_RUN
ECSMI#_KBC
S
4
3
2
1
DY
SRN4K7J-10-GP
1
R3711
DY
KB_DET#
LCD_CBL_DET#
2
10KR2J-3-GP
4
3
1
2
KCOL[0..16]
77
R3737 1
+KBC_PWR
30
DY
AMP_MUTE#
2TOURBO_BOOST 79
10KR2J-3-GP
30
63
117
31
32
118
62
47 IMVP_PWRGD
22 PM_PWRBTN#
54 LCD_TST_EN
30 KBC_BEEP
66 AMBER_LED#_KBC
82 THERMTRIP_VGA_GATE
68 KB_DET#
54 LCD_CBL_DET#
2
1
R3746
0R0402-PAD
62 EC_SPI_DI
62 EC_SPI_DO
62 EC_SPI_CS#
62 EC_SPI_CLK
1
R3745
R3734 1
13
12
THERMTRIP_VGA_GATE_C 11
10
54 LCD_TST
71
68 TPDATA
72
68 TPCLK
2
EC_SPI_DO_C
33R2J-2-GP
2 33R2J-2-GP
EC_SPI_CLK_C
86
87
90
92
32KX1/32KCLKIN
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
32KX2
GPIO55/CLKOUT
GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
F_SDI
F_SDO
F_CS0#
F_SCK
KBC
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
54
55
56
57
58
59
60
61
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
FIU
85
ECRST#
68
X01 change location
BLUETOOTH_EN R3712 1
S5_ENABLE
R3713 1
IMVP_VR_ON
R3717 1
2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP
GFX_CORE_EN
2 10KR2J-3-GP
R3719 1
X01
20091116
+KBC_PWR
R3722
10KR2J-3-GP
1
TP3708
TPAD14-GP
KROW[0..7]
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
PS/2
VCC_POR#
PCLK_KBC
x01 Change tolerant 20091117
SRN100KJ-6-GP
1
1 100KR2J-1-GP
100KR2J-1-GP
2 OF 2
U3701B
EC3701
SCD1U10V2KX-5GP
RN3703
E51_RxD
BAS16PT-GP
KBC_THERMTRIP#
2
AC_IN#_KBC
R3709 2
R3718
For EMI
D
2
5
6
7
8
2
22 PCH_SUSCLK_KBC
PM_PWROK
THERMTRIP_VGA#
BAT_SCL
BAT_SDA
ECRST#
A00-20100301
1
C3712
SC1U6D3V2KX-GP
9(5
C
+KBC_PWR
RN3701
DISCRETE_ID
49,50
2
AGND
DY
R3705
2K2R2J-2-GP
2
BAS16PT-GP
Vendor recomment FW can do it
*3,2
2
1
25 SIO_EXT_SCI#
68 KB_BL_CTRL
80$
0DGLVDQ
3DUN
0
+KBC_PWR
D3704
76
3
A00-20100203
9*$675$3
RSWLRQ *3,2
ECSWI#_KBC
SSID = KBC
KBC_VCORF
A00-20100125
B
KBC_ON#
D
S
2N7002E-1-GP
3
E51_TxD 76
E51_RxD 76
AC_PRESENT_EC 22
PM_LAN_ENABLE 76
1
2
2
EC_ENABLE#
D3701
103
GND
GND
GND
GND
GND
GND
1
1
1
2
DY
DY
$
;
;
$
10KR2J-3-GP
R3733
10KR2J-3-GP
R3732
R3731
10KR2J-3-GP
0%9(56,21
,' 9(5 9(5
116
89
78
45
18
5
1
2
1
2
2
10KR2J-3-GP
R3729
10KR2J-3-GP
R3728
1
NPCE781BA0DX-GP
+KBC_PWR
BAS16PT-GP
111
113
112
44
45
1
90
BLUETOOTH_EN 73
WIFI_RF_EN 76
WWAN_RADIO_DIS#
114
14
15
AC_IN#
SI2301CDS-T1-GE3-GP
84.2N702.D31
3
+3.3V_RUN
PCB_VER0
PCB_VER1
PCB_VER2
3 KBC_THERMTRIP#
Q3705
PMBS3904-1-GP
ECSMI#_KBC
84
83
82
91
Q3703
Q3704
G
SCD1U10V2KX-5GP
X02-20100104
25 SIO_EXT_SMI#
DY
1
2
H_THERMTRIP#
10KR2F-2-GP
1.8V_VGA_RUN_EN
C3711
H_THERMTRIP_R# 2
DY1
DY
55
KBC_SDA1 23
KBC_SCL1 23
BAT_SDA 44,45
BAT_SCL 44,45
81
3
D
G
C3713
D3703
BAT54C-U-GP
R3710
2K2R2J-2-GP
DY
INT_SERIRQ 23,24
PM_CLKRUN# 22
SIO_RCIN# 25
SIO_A20GATE 25
ECSCI#_KBC
+KBC_PWR
2
VCORF
R3727
10KR2J-3-GP
2
1
24,70
25 SIO_EXT_WAKE#
SP
AC_IN#_KBC
24,70
LPC_LAD[0..3]
1KBC_ON#_GATE
10KR2J-3-GP
1
R3715
64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110
+1.05V_VTT
PCLK_KBC 21
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
R3707
KBC_ON# 2
R3708
1 DY
2
0R2J-2-GP
PCH_TEMP_ALERT# 25
PLT_RST1#_1
2
KBC_PWRBTN_EC#
AC_IN#_KBC
THERM_SCL 39
1
124
7
2
3
126
127
128
1
125
8
122
121
29
9
123
20091111
2
PM_SLP_S3#
69 LID_CLOSE#
1
X01
1
22,42,47,50,51,89
+3.3V_RTC_LDO
R3706
10KR2J-3-GP
2
4
80
GPIO41
VDD
AVCC
D/A
+3.3V_RTC_LDO
KBC_PWRBTN#
3
D3702
BAT54C-U-GP
66 KBC_PWRBTN#
2N7002EDW-GP
R3714
A00-20100301
6
1
100KR2J-1-GP
KBC_SDA1
1
PH for Discrete
Internal PL for UMA
GPI94
GPI95
GPI96
GPI97
2
.
PCB_VER2
101
105
106
107
LPC
3
5
84.27002.F3F
GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#
A/D
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05
GPIO04
KBC_SCL1
BAT_IN# 44
4
.
.
. .
22 SUS_PWR_DN_ACK
90 3.3V_RUN_VGA_EN
97
98
99
100
108
96
VREF
1
Q2302
1 OF 2
2
2
X01 change location
X01 20091111
C
SC2D2U6D3V3KX-GP
2
DISCRETE_ID
KBC_THERMTRIP#
104
2 KBC_PWRBTN_EC#
DY 0R2J-2-GP
1
R3703
1
DY
9 VDDPWRGOOD_KBC
+KBC_PWR
R3704
C3703
SCD1U10V2KX-5GP
C3715
TP3704
102
115
88
76
46
19
VCC
VCC
VCC
VCC
VCC
U3701A
2
SCD1U10V2KX-5GP
KBC_GPIO91
1
82 THERMTRIP_VGA#
76 PSID_EC
DY
39 THERM_SDA
A00-20100202
1
1
C3710
SCD1U10V2KX-5GP
2
1
1
2
C3709
SC2D2U6D3V3KX-GP
C3708
SCD1U10V2KX-5GP
2
1
45 AD_IA
x01 change tolerant 20091118
1
C3702
SCD1U10V2KX-5GP
x01 change tolerant 20091117
2
10mW circuit
+3.3V_RUN
x01 change tolerant 20091118
1
VBAT
C3707
SCD1U10V2KX-5GP
2
1
C3706
SCD1U10V2KX-5GP
2
1
C3705
SCD1U10V2KX-5GP
2
1
C3704
SCD1U10V2KX-5GP
2
1
1
2
C3701
SC2D2U6D3V3KX-GP
DY
1
+3.3V_RTC_LDO
X02-20091222
+KBC_PWR
2
+3.3V_RUN
CAP close to VCC-GND pin pair
DY
2
R3702
2
2
D
3
20091111
2
X01
+KBC_PWR
PURE_HW_SHUTDOWN#
68
B
+3.3V_RUN
RN3702
SIO_A20GATE
SIO_RCIN#
2
1
3
4
SRN10KJ-5-GP
NPCE781BA0DX-GP
2
1
2
1
Vendor recomment can remove
DY
EC3702
SC470P50V2JN-GP
A00-20100204
EC3703
SC18P50V2JN-1-GP
X02-20091222
R3716
X02-20100105
9,21,70,76,78,80
PLT_RST#
2
PLT_RST1#_1
1
0R0402-PAD
1
ECRST#
2
1
2
DY
C3714
SC470P50V2JN-GP
2
1
Q3701
PMBS3906-GP
C3716
SC1U6D3V2KX-GP
3
39,42 PURE_HW_SHUTDOWN#
DY
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
KBC Nuvoton NPCE781BA0DX Rev
Size
A2
Document Number
Date:
Monday, March 29, 2010
A00
Berry
Sheet
1
37
of
92
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
Reserved
Date: Wednesday, February 10, 2010
5
4
3
2
Rev
Berry
A00
Sheet
38
of
1
92
A
5
4
3
+5V_RUN
SSID = Thermal
2
1
+3.3V_RUN
1
R3901
10KR2J-3-GP
C3901
SCD1U10V2KX-5GP
2
2
C3902
SC10U6D3V5MX-3GP
2
1
1
x01 change tolerant 20091117
+3.3V_RUN
1. Place near CPU PWM CORE and PCH.
1
58
+3.3V_RUN
THERM_SCL 37
THERM_SDA 37
RN3901
THERM_SCL
THERM_SDA
23
22
SMCLK
2
1
SRN4K7J-8-GP
SRN10KJ-5-GP
SMDATA
24
26
25
FANb
FANa
28
27
3
4
THERM_POWER_OK#
THERMTRIP#
3
4
2
1
RN3902
UMA
1
Layout notice :
UMA
Both DN2 and DP2 routing 10 mil
trace width and 10 mil spacing.
1
DIS
VDD_3V
2
DN1
EMC2102_DP1
3
DP1
EMC2102_DN2
4
DN2
DP2
2
0R2J-2-GP
C3907
SC470P50V2JN-GP
ALERT#
19
CLK_IN
18
CLK_SEL
17
EMC2102_CLK_SEL
EM2102_RESET# 1
6
DN3
RESET#
16
7
DP3
NC#15
15
THERMTRIP#
13
SYS_SHDN#
12
FAN_MODE
TRIP_SET
11
10
NC#8
SHDN_SEL
9
8
GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled
X02-20091222
+3.3V_RUN
CLK_32K
R3905
5
DIS
Layout notice :
Both VGA_THERMDA and VGA_THERMDC routing
10 mil trace width and 10 mil spacing.
20
EMC2102_DN3
EMC2102_DP3
3.VGA Sensor(DISCRETE Only)
21
GND
EMC2102_DP2
1
2
R3907 0R2J-2-GP
82 VGA_THERMDA
NC#21
EMC2102
2
R3906
1
Reserved DISCRETE
82 VGA_THERMDC
1
EMC2102_DN1
C
1
2
0R0402-PAD
GND = Internal Oscillator Selected
+3.3V = External 32.768kHz Clock Selected
TP3901
POWER_OK#
2
R3904
R3903
14
2. System Sensor(UMA Only)
1
2
0R2J-2-GP
EMC2102_DP2_UMA
0R2J-2-GP
3
2
DY
VDD_5Vb
1
TACH
1
2
UMA
C3906
SC470P50V2JN-GP
VDD_5Va
29
GND
U3901
C
EMC2102_FAN_DRIVE
C3903
SCD1U10V2KX-5GP
EMC2102_DN2_UMA
Q3902
PMBS3904-1-GP
58
3
2
DY
C3905
SC470P50V2JN-GP
2
1
2
1
C3904
SC470P50V2JN-GP
EMC2102_FAN_TACH
D
EMC2102_FAN_DRIVE
1
near EMC2102
C3905 must be near Q3901
Q3901
PMBS3904-1-GP
EMC2102_FAN_TACH
R3902
49D9R2F-GP
2
1 EMC2102_VDD_3D3
Layout notice :
Both DN1 and DP1 routing 10 mil
trace width and 10 mil spacing.
2
D
Main G7922R61U for GMT P/N:74.07922.0B3
SEC. EMC2102 for SMSC P/N:74.02102.A73
EMC2102-DZK-GP
R3908
2
DY 1
EMC2102_SHDN
THERM_POWER_OK#
THERMTRIP#
10KR2J-3-GP
C3907 must be near Q3902
3
C63 must be
near EMC2102
A00-20100204
R3911
1
2
0R0402-PAD
4.HW T8 sensor
Q3904
G
GND = Fan is OFF
OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale
B
.
Layout notice :
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.
+3.3V_RUN
+3.3V_RUN
1
EMC2102_FAN_mode
D
PURE_HW_SHUTDOWN#
37,42
S
C3910
SCD1U10V2KX-5GP
R3913
10KR2F-2-GP
2
1
10KR2J-3-GP
1
2
DY
2
1
R3909
2
.
.
. .
B
DY
THERM_SYS_SHDN#
1
Q3903
PMBS3904-1-GP
C3909
SC470P50V2JN-GP
2
1
2
+3.3V_RUN
C3908
SC470P50V2JN-GP
2N7002E-1-GP
TRIP_SET Pin Voltage
V_DEGREE=(((Degree-75)/21)
V_DEGREE
22 PCH_SUSCLK_2102
C3911
SCD1U10V2KX-5GP
R3914
2K37R2F-GP
2
D
2
32K suspend clock output
1
1
84.2N702.D31
84.2N702.D31
S
G
.
.
. .
T8 shutdown is set 88 deg-C.
x01 change tolerant 20091117
Q3905
2N7002E-1-GP
.
R3915
CLK_32K_R
1
A
CLK_32K
2
10R2J-2-GP
1
42 RUN_ENABLE
2
DY
C3913
SC4D7P50V2CN-1GP
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Thermal/Fan Controllor EMC2102
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Custom
Rev
A00
Berry
Date:
Tuesday, April 06, 2010
Sheet
1
39
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
40
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
41
of
92
5
4
3
SSID = Reset.Suspend
2
1
E
H_THERMTRIP# 9,25,37,82
R4201
1
B
DY
C4202
DY
Q4201
CHT2222APT-GP
x01 change to 10V tolerant 20091117
2
D
C
H_PW RGD_R
2
DY
1KR2J-1-GP
SCD1U10V2KX-5GP
BAS16PT-GP
2
1
9,25 H_PW RGD
3
PURE_HW _SHUTDOW N#
D
37,39
1
46 3V_5V_EN
1
D4201
R4202
200KR2J-L1-GP
1
R4203
2
1KR2J-1-GP
S5_ENABLE 37
2
DY
Run Power
+15V_ALW
2
+5V_RUN
5
6
7
8
R4204
100KR2J-1-GP
R4205
4
3
2
1
+5V_RUN Comsumption
Peak current 7.73A
5V_RUN_ENABLE
C
C4203
SC10U10V5KX-2GP
SI4800BDY-T1-GP
2
2
10KR2J-3-GP
100KR2J-1-GP
R4207
1
2 PS_S3CNTRL
G
S
S
S
1
1
+3.3V_RTC_LDO
U4201
D
D
D
D
1
1
C
+5V_RUN
AO4468 MAX 9A
Rds(on) = 18.5mOhm
+5V_ALW
84.04800.D37
C4201
SC6800P25V2KX-1GP
2
PS_S3CNTRL 18,50
x01 change to 10V tolerant 20091117
+3.3V_RUN
4
3
2
1
Q4202
2N7002EDW -GP
AO4468 MAX 11.6A
Rds(on) = 18.5mOhm
84.27002.F3F
+3.3V_ALW
+3.3V_RUN
S G D
PM_SLP_S3#
R4211
1
2
10KR2J-3-GP
+3.3V_RUN Comsumption
Peak current 8.14A
4
3
2
1
SI4800BDY-T1-GP
3.3V_RUN_ENABLE
84.04800.D37
+1.5V_RUN_CPU
1
S3 Power Reduction X01 20091111
DISCHARGE_1D5V_CPU_C
R4214 1
0R5J-5-GP
R4219 1
0R5J-5-GP
2
1
R4215
1
R4220
2
2
0R0805-PAD
2
0R0805-PAD
+1.5V_RUN for Mini-Card Comsumption
Peak current 1A
Total= 11.39A
TPCA8039-H-GP
10KR2J-3-GP
C4210
SCD01U50V2KX-1GP
<Core Design>
C4208
SC10U6D3V5KX-1GP
A
COLAY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
21.5V_RUN_ENABLE
1
1
2
3
4
Title
2
84.2N702.D31
R4227
U4203
S
S
S
G
2
Q4206
2N7002E-1-GP
D
D
D
D
1
D
8
7
6
5
S
G
DY
DY
TPCA8039-H MAX 34A
Rds(on) = 3.8m OHM
DIS uses 84.08039.037 TPCA8039-H Peak current=34A
UMA uses 84.07686.037 SI7686DP Peak current=35A
PS_S3CNTRL
5
+1.5V_RUN
X02-20091222
.
.
. .
DY
+1.5V_RUN_CPU Comsumption
Peak current 3A
+1.5V_SUS
+1.5V_RUN_CPU
.
A
1.5V_RUN for VGA Comsumption
Peak current 7.39A
MAX Current 3000 mA
Design Current 2100 mA
2
DY
2
B
+1.5V_RUN
1
S3 Power Reduction
R4213
220R2J-L2-GP
C4205
SC10U6D3V5KX-1GP
C4207
SCD01U50V2KX-1GP
2
B
G
S
S
S
2
RUN_ENABLE
39 RUN_ENABLE
U4202
D
D
D
D
1
22,37,47,50,51,89
5
6
7
8
1
5
6
D G S
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Power Plane Enable
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
42
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
43
of
92
5
4
3
2
1
Batt Connecter
PC4402
SCD1U50V3KX-GP
GAP-CLOSE-PWR-3-GP
2
+KBC_PWR
1
BATT1
D
10
1
R4401
R4402
R4403
37,45 BAT_SCL
37,45 BAT_SDA
37 BAT_IN#
PC4401
SC2200P50V2KX-2GP
2
PG4401
1
2
D
2
45 BATT_SENSE
1
+VCHGR
1
1
1
2 100R2J-2-GP
2 100R2J-2-GP
2 100R2J-2-GP
2
3
4
5
6
7
8
9
11
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
PR4401
1
1BAT_ALERT
AFTP4401
470KR2J-2-GP
ALP-CON9-2-GP-U
20.81316.009
C
C
For actual location, need to be swap all pin
Close to Batt Connector
3
PD4402
3
3
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
+VCHGR
BAT_SCL
B
1
1
1
1
BAT_SDA
BAT_IN#
AFTP4402
AFTP4403
AFTP4404
AFTP4405
PD4403
1
1
2
1
PD4401
2
B
2
BAV99-8-GP
BAV99-8-GP
BAV99-8-GP
+KBC_PWR
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Rev
Berry
Date: Monday, March 29, 2010
5
BATT CONN
A00
Sheet
44
of
1
92
A
5
4
3
2
1
SSID = Charger
modify +VCHGR
1
16
PC4523
1
2
NC#16
2 PR4528 1
2 PR4529 1
0R0402-PAD
DY
CHG_AGND
CHG_AGND
DY
GAP-CLOSE-PWR-3-GP
2
1
1
EC4501
SC2200P50V2KX-2GP
PC4509
SCD1U50V3KX-GP
2
2
PC4508
SC10U25V6KX-1GP
2
1
2
PC4507
SC10U25V6KX-1GP
2
1
EC4502
SCD1U25V2ZY-1GP
PD4502
1SMA18AT3G-GP
PC4519
SCD1U50V3KX-GP
A
K
DY
PR4524
0R0402-PAD
BQ24745_CSOP
0R0402-PAD
X02-20091223
X02-20091223
BQ24745_CSON
BATT_SENSE 44
0R0402-PAD
X02-20091223
1 PR4523 2
DY
PR4530
1K8R6J-GP
BAT_SENSE
1
PU4501
BQ24745RHDR-GP
15
DY
BQ24745_PR4505
1
GND
X02-20091223
VFB
29
1
2
CHG_AGND
FBO
EAI
EAO
VREF
CE
GND
PC4518
SC10U25V6KX-1GP
2
1
17
VICM
2
2
CSON
BQ24745_CSOP_1
G
S
S
S
18
4
3
2
1
19
CSOP
1
L-5D6UH-GP-U
SCD1U50V3KX-GP
PGND
PC4520
SCD1U50V3KX-GP
1
2
NC#14
2
SCD01U50V2KX-1GP
1
DY
PC4517
SC10U25V6KX-1GP
2
1
1
2
PC4514
SC220P50V2JN-3GP
+VCHGR
PR4519
1
2
D01R2512F-4-GP
PC4516
SC10U25V6KX-1GP
2
1
BQ24745_PHASE_GND
BQ24745_LGATE_1
2009/11/24
+VCHGR1
PL4501
2
1
PC4515
SC10U25V6KX-1GP
2
1
20
X02-20100116
PC4513
SC3300P50V3KX-1GP
BQ24745_LX1
C
modify +VCHGR
1
LGATE
SDA
DY
Charger Current=1.4~3.6A
2
PHASE
23
1
2
PC4512
SCD1U50V3KX-GP
1 PR4518 2
0R0603-PAD
2
PC4528
PC4530
SCD1U10V2KX-5GP
1
2
1
DY
DY
2
PR4521
1
4K7R2J-2-GP
SCD01U50V2KX-1GP
2
1
DY
GAP-CLOSE-PWR-3-GP
PG4505
1
2
X02-20091223
PR4522
200KR2F-L-GP
1
2
6
BQ24745_EAI
5
BQ24745_EAO
PC4522
4
PR4526
BQ24745_REF
3
1
2SC2200P50V2KX-2GP
BQ24745_CE 7
2
1PR4526_01
2 7K5R2F-1-GP
1
1 PR4527 2
PC4521
12
0R0402-PAD
PC4525
SC150P50V2JN-3GP
1
2
X02-20091223
PC4527 SC56P50V2JN-2GP
PC4529
DY
SCD1U50V3KX-GP
2
PC4526
8
BQ24745_FBO
PU4504
SI4800BDY-T1-GP
5
6
7
8
1
2
D
D
D
D
G
S
S
S
BQ24745_CHARGER_UGATE
D
D
D
D
9
GAP-CLOSE-PWR-3-GP
PG4504
1
2
PG4501
1
2
24
DY
1
BAT_SDA_1
1
GAP-CLOSE-PWR-3-GP
2
PG4508
37,44 BAT_SDA
PC4506
SC1U6D3V2KX-GP
UGATE
PR4513
33R3J-2-GP
2
1
PD4501
CHG_AGND
1 PR4517 2BQ24745_BST1
BQ24745_BOOT_1
K
A
1
2
0R0603-PAD
BQ24745_LDO
PC4511
SD103AWS-1-GP SCD1U50V3KX-GP
DY
PC4531
SCD1U50V3KX-GP
SCL
1
2
PC4504
SCD1U50V3KX-GP
25
21
DY
PG4509
GAP-CLOSE-PWR-3-GP
1
2
10
GAP-CLOSE-PWR-3-GP
PG4506
1
2
2
1
BOOT
VDDP
DY
CHG_AGND
PG4510
GAP-CLOSE-PWR-3-GP
1
2
BAT_SCL_1
1
GAP-CLOSE-PWR-3-GP
2
PG4507
SC1U6D3V2KX-GP
2
27
26
CHG_AGND
BQ24745_VICM
1BQ24745_FBO1
2
8K45R2F-2-GP
ACOK
CHG_AGND
1 PC4524
SC220P50V2JN-3GP
PR4525
1
13
PR4506
470KR2J-2-GP
PU4505
SI4800BDY-T1-GP
BQ24745_ACOK
X03-20100119
2
VDDSMB
D
Id=-12A
Qg=-25nC
Rdson=10~38mohm
CHAGER_SRC
4
3
2
1
PC4501
SCD1U10V2KX-5GP PR4512
2
1
0R0402-PAD
14
B
CSSN
ICOUT
SCD1U50V3KX-GP
BQ24745_CSSN
BQ24745_ICOUT
X02-20091223
1
0R2J-2-GP
DY
11
28
CSSP
PC4532
SCD1U25V2ZY-1GP
PR4501
ACIN
DY
5
6
7
8
DY
CHG_AGND
DCIN
2
x01 change tolerant 20091117
37,44 BAT_SCL
2009/08/04
22
BQ24745_ACIN
PC4505
BQ24745_CSSP1
2
1
2
1
+KBC_PWR
BQ24745_DCIN
8
7
6
5
CHAGER_SRC
2
ACAV_IN
PR4516
2 10KR2F-2-GP
1
PR4515
10KR2F-2-GP
2
1
DY
PR4520
15K8R3F-GP
2
1
PC4510
SCD01U50V2KX-1GP
1
BQ24745_LDO
2
PR4514 48K7R3F-1-GP
2
1
BQ24745_REF
1
CHG_AGND
ICREF
1
0R0402-PAD
2
1
PC4503
SCD1U50V3KX-GP
2
PR4510
0R0402-PAD
1
2
PC4502
SCD1U50V3KX-GP
84.27002.F3F
2
PR4511
37 AD_IA
1
1
PR4508
0R0402-PAD
2N7002EDW-GP
X02-20091223
C
1
PR4507
0R2J-2-GP
D
D
D
D
2
6
X02-20091223
DY
2
1
GAP-CLOSE-PWR-3-GP
2
+VCHGR
PU4503
S
S
S
G
AO4407A-GP
PG4503
GAP-CLOSE-PWR-3-GP
PR4533_02 2
2
5
PR4505
10KR2F-2-GP
1
4
2
1
2
3
4
+DC_IN_SS
PG4502
1
316KR3F-2-GP
BQ24745_ACOK
2
PR4509
PQ4502_05
PQ4501
3
1
2
D01R2512F-4-GP
PR4524_03
PQ4502_03
1
+DC_IN_SS
Id=-12A
PR4513_03
Qg=-25nC
Rdson=10~38mohm
2
PR4504
1
2
10KR2J-3-GP
AO4407A-GP
D
+PWR_SRC
PR4502
1
2
3
4
1
PU4502
S
S
S
G
D
D
D
D
PR4503
100KR2J-1-GP
8
7
6
5
+DC_IN_SS
+SDC_IN
B
CHG_AGND
CHG_AGND
This Resistor
must be 1%
tolerance.
PC4533
SCD1U10V2KX-5GP
Q4502
2N7002E-1-GP
.
2
DY
D
1
37 AC_IN#
A
x01 change tolerant 20091117
G
S
.
. .
.
ACAV_IN
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Custom
CHARGER BQ24745
Rev
Berry
Date:
Monday, March 29, 2010
A00
Sheet
1
45
of
92
A
B
C
D
E
+3.3V_ALW_2
51125_LL1
19
51125_DRVL1
24
51125_VO1
51125_VBST1_1
1
2
1
1
2
2
S
4
3
2
1
G
1
5
6
7
8
2
2
1
1
2
Design Current = 8.48A
13.32A<OCP< 15.75A
1
2
ENTRIP1
SKIPSEL
G
S
DY
PC4622
SC560P50V-GP
25
51125_VCLK
18
LG1_CP
PR4611
0R2J-2-GP
1
2
1
DY
PTC4604
2
DY
1
1
GAP-CLOSE-PWR
PG4618
2
1
GAP-CLOSE-PWR
PG4619
2
1
GAP-CLOSE-PWR
PG4620
2
1
GND
PTC4603
PC4620
2
1
2
51125_ENTIP1
1
GAP-CLOSE-PWR
PG4617
x01 change tolerant 20091117
PG4626
1
GAP-CLOSE-PWR
PG4621
1
TONSEL
1
15
PGND
2
REF
3V_5V_POK
151125_LL1_R
2
PGOOD
ENTRIP2
51125_FB1
23
1 2
1
2
14
51125_SKIPSEL
EN
2
2D2R5F-2-GP
1
PR4612
33KR2F-GP
2
51125_FB1_R
1
GAP-CLOSE-PWR
2
51125_FB2_R
4
FB1
VREG3
PR4610
0R2J-2-GP
DY
51125_TONSEL
FB2
DYPR4607
1
1
IND-2D2UH-46-GP-U
5
6
7
8
D
4
3
2
1
2
2
GAP-CLOSE-PWR
PG4616
2
PU4605
FDS6676AS-GP
1
GAP-CLOSE-PWR
PG4615
2
+5V_PWR
X02-20100116
PL4602
2
1
2
16
VIN
VOUT1
20
1
VREG5
D 8
D 7
D 6
D 5
1 S
2 S
3 S
4 G
LGATE1
VOUT2
1
DY PR4618
0R2J-2-GP
PR4619
+3.3V_ALW_2
2
1
0R2J-2-GP
PR4620
X02-20091228
2
1
DY0R2J-2-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 10.8mohm/11.8mohm Isat =16Arms 68.3R310.20C
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: FDS8880 9.6mohm/[email protected]/ 84.08880.037
L/S: FDS6676AS 5.9mOhm/[email protected]/ 84.06676.A37
PR4614
PR4617
TPS51125
DY
ASM
DY
+3.3V_ALW_2
3
1
1
PC4627
SC10U10V5KX-2GP
Close to VFB Pin (pin5)
PC4626
SC4D7U6D3V3KX-GP
2
PR4616
21K5R2F-GP
2
Change to RT8205B
74.08205.B73
1
51125_VREF
GAP-CLOSE-PWR-3-GP
1
0R2J-2-GP
PR4617
1
DY0R2J-2-GP
2
2
2
2
1
2
2
51125_VREF
+3.3V_ALW_2
DY
PR4615
100KR2J-1-GP
3V_5V_POK
SC22U6D3V5MX-2GP
PC4628
PR4613
10KR2F-2-GP
2
1
2
17
8
PG4635
1
3D3V_AUX_S5_5_51125
2
+3.3V_ALW_2
PR4614
+3.3V_ALW
+5V_ALW2
2
PC4624
SC18P50V2JN-1-GP
RT8205BGQW-GP
DY PC4625
SC18P50V2JN-1-GP
1
3
2
1
D 8
D 7
D 6
D 5
1 S
2 S
3 S
4 G
1
1
2
2
2
1
51125_VREF
5
51125_EN 13
820KR2F-GP
51125_ENTIP2 6
DY
PR4608
G
2
1
2
7
51125_FB2
1
X02-20100201
1
LGATE2
51125_DRVH1
ST100U6D3VBM-5GP
1
51125_VO2
PC4623
2
PU4604
3
1 2
PHASE1
51125_VBST1
21
ST220U6D3VDM-15GP
DY
S
PHASE2
22
+5V_ALW
PG4613
2
GAP-CLOSE-PWR
PG4614
SCD1U10V2KX-5GP
151125_LL2_R
2
1
2
1
12
UGATE1
+5V_PWR
PC4617
GAP-CLOSE-PWR-3-GP
PC4621
SC330P50V2KX-3GP
D
DY
SCD22U10V2KX-1GP
PR4609
6K65R2F-GP
11
BOOT1
UGATE2
S
S
S
G
x01 change tolerant 20091117
51125_LL2
BOOT2
D
D
D
D
PR4606
2D2R5F-2-GP
PG4624
9
10
51125_DRVL2
2
IND-3D3UH-115-GP
GAP-CLOSE-PWR-3-GP
ST100U6D3VBM-5GP
51125_DRVH2
FDS6676AS-GP
ST220U6D3VDM-15GP
SCD1U10V2KX-5GP
2
1
1
SCD1U25V3KX-GP
PC4618
PR4605
4D7R3J-L1-GP
251125_VBST2
1
PC4616
SCD1U25V2KX-GP
PR4604
4D7R3J-L1-GP
51125_VBST2_1
1
PC4614
SC10U25V6KX-1GP
2
X01 EMI stuff 20091118
D
PU4603
FDS8880-NL-GP
S
S
S
G
PC4615
SCD1U25V3KX-GP
G
PL4601
PR4605
RT8205B
4R7
SC10U25V6KX-1GP
PU4601
S
2
RT8205B
4R7
TPS51125
0R3J
D
D
D
D
TPS51125
0R3J
PR4604
PU4602
FDS8880-NL-GP
PC4613
SCD01U50V2KX-1GP
SC10U25V6KX-1GP
DY
D
SC10U25V6KX-1GP
PC4611
SC10U25V6KX-1GP
SCD1U25V2KX-GP
PC4610
X02-20100116
+3.3V_ALW
DY
1
PC4612
PC4609
PTC4602
PD3904_1
2
2
820KR3J-GP
PTC4601
2
2
2
X01 20091124
+PWR_SRC
51125_EN 1
X01 EMI stuff 20091118
PC4619
4
PC4606
SCD1U10V2KX-5GP
PC4608
SCD1U25V3KX-GP
+PWR_SRC
PR4622
Design Current =9.07A
14.25A<OCP<16.84A
PC4605
SC1U25V3KX-1-GP
1
1
1
RT8205B
ASM
+5V_PWR
x01 change tolerant 20091117
1
GAP-CLOSE-PWR-3-GP
PR4603
82KR2F-1-GP
2
PC4607
SC18P50V2JN-1-GP
TPS51125
DY
3
1
PD3903_2
2
2
51125_ENTIP2
PR4622
2
PG4605
1
DY
PD3903_04
84.27002.F3F
A00-20100224
1
3
2
1
+15V_ALW
4
+PWR_SRC
PD4602
BAT54S-5-GP
2
PQ4602
2N7002EDW-GP
1
PD4601
BAT54S-5-GP
4
6
5
1
2
76K8R2F-GP
2
S
G
42 3V_5V_EN
PC4604
SCD1U25V3KX-GP
PR4601
DY
SC18P50V2JN-1-GP
84.2N702.D31
1
51125_ENTIP1
PC4601
.
.
. .
PC4603
SCD1U25V3KX-GP
PD3903_1
2
2
D
51125_ENTRIP
.
Q4601
2N7002E-1-GP
PC4602
SC1KP50V2KX-1GP
PR4602
100KR2J-1-GP
3
1
1
51125_VCLK
X02-20091223
+3.3V_RTC_LDO
Close to VFB Pin (pin2)
37
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: FDS8880 9.6mohm/[email protected]/ 84.08880.037
L/S: FDS6676AS 5.9mOhm/[email protected]/ 84.06676.A37
PR4621
RT8205B
ASM
DY
1
2
0R0402-PAD
TPS51125:
CH1
CH2
GND
200kHz
265kHz
VREF
TONSEL
245kHz
305kHz
VREG3
300kHz
375kHz
VREG5
365kHz
460kHz
SKIPSEL
VREG3 or VREG5
VREF(2V)
Operating
Mode
OOA Auto Skip
Auto Skip
EN0
Operating
Mode
GND
PWM only
Open
enable both
LDOs, VCLK on
and ready to
turn on
switcher
channels
820kȍ to GND
enable both LDOs,
VCLK off and
ready to turn on
switcher channels
GND
disable all
circuit
RT8205B:
TONSEL
2
CH1
CH2
GND
200kHz
250kHz
VREF
300kHz
375kHz
VREG3
365kHz
460kHz
VREG5
365kHz
460kHz
2
1
1
Bom
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
http://laptop-motherboard-schematic.blogspot.com/
B
C
D
Title
RT8205B_5V/3D3V
Size
A1
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
E
A00
Sheet
46
of
92
4
3
1
ISEN3
1
PR4780
1
PR4739
1
PR4708
1
PR4760
1
PR4707
2
1
2
715R2F-GP
VSUMISEN1
ISEN2
2
1
1
2
1
2
SE220U2VDM-12GP
1
2
ST330U2VDM-4-GP
1
2
+VCC_CORE_PHASE1
PHASE1_R
10KR2F-2-GP
2
3K65R2F-1-GP
2
1
1
2
SE220U2VDM-12GP
1
2
ST330U2VDM-4-GP
1
2
1
1
2
2
1
2
2
PTC4707
ST330U2VDM-4-GP
1
PTC4706
ST330U2VDM-4-GP
1
2
1
2
PHASE3_R
PR4740
2D2R5J-1-GP
1SNUBBER_3
2
2
1
PR4763
1
PR4764
1
PR4747
1
PR4719
1
PR4765
+VCC_CORE_PHASE3
VSUM+
PC4739
SC330P50V2KX-3GP
1
5
6
7
8
4
3
2
1
1
1
2
2
1
2
1
1
2
2
1
1
2
2
1
1
2
2
ISEN3
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.36UH PCMC104T-R36MN1R05J Cyntec 1.05mohm/ 68.R3610.20C
O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L
O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L
H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
PG4714
DY
LGATE3
GAP-CLOSE-PWR-3-GP
PR4777
1KR2J-1-GP
DY
2
IND-D36UH-9-GP
PG4701
PR4706 PR4703
1KR2J-1-GP
DY
1KR2J-1-GP
1KR2J-1-GP
A
PR4710
DY
GAP-CLOSE-PWR-3-GP
SIR460DP-T1-GE3-GP
D
S
D
S
D
S
D
G
PR4743 PR4727
1KR2J-1-GP
DY
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
DY
+VCC_CORE
PL4703
1
PU4708
PR4702 PR4768
2
2
1
1
2
5
6
7
8
4
3
2
1
1
1
2
2
1
2
1
1
2
2
1
1
2
2
X02-20100116
UGATE3
PHASE3
DY
PC4726
DY
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR
PSI#
PR4715
PC4728
DY
SCD1U50V3KX-GP
PU4707
2
GAP-CLOSE-PWR-3-GP
PC4725
SC10U25V6KX-1GP
2
PC4727
SC10U25V6KX-1GP
PC4731
SCD1U25V3KX-GP
SC10U25V6KX-1GP
1
1
10KR2F-2-GP
SI7686DP-T1-GP
S
D
D
S
D
S
D
G
PR4753
1KR2J-1-GP
DY
1KR2J-1-GP
1KR2J-1-GP
DY
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
DY
PR4769 PR4724
2
10KR2F-2-GP
2
B
PG4715
PR4705
PHASE2_R
1R2F-GP
2
NTC 10K close to Choke of Phase1
X01 20091124
1
PR4732 PR4713
1
1SNUBBER_1
2
2
3K65R2F-1-GP
2
VSUM-
+1.05V_VTT
1
10KR2F-2-GP
2
2
1
PR4748
Intel support POC (Power On Configuration).
2
2
1
2
1
PC4701
SC1KP50V2KX-1GP
PR4701 PR4709
PTC4704
+PWR_SRC
B
2
1
2
VSUMISEN1
PR4721
NTC-10K-26-GP
1SNUBBER_2
2
4
3
2
1
2
ISEN2
PTC4705
+VCC_CORE_PHASE2
9
3
X02-20100108
DY
LGATE2
PHASE3
UGATE3
LGATE3
VSUM+
ISL6208CRZ-TGP-U
DY
PR4728
2D2R5J-1-GP
5
6
7
8
BOOT
7
8
4
6208_PHASE3
1
1
PHASE
UGATE
LGATE
+VCC_CORE
2
IND-D36UH-9-GP
PC4733
SC330P50V2KX-3GP
1
1VSUM_RR
2
5
VCC
FCCM
2D2R3J-2-GP
PC4723
SCD22U16V3KX-1-GP
GND
GND
6208_PWM
6208_FCCM
6
PWM
1
PC4742
SCD01U25V2KX-3GP
1
4
3
2
1
1
1
PU4706
2
PR4750
2K61R2F-1-GP
PR4736
2
2
1
1
PC4741
PU4705
PR4734
SC1U10V2KX-1GP
BOOT3
1
2
VSUM+
VSUM_RC
2
PC4734
1
2
2
2
1
1
X02-20091223
C
PL4702
1
+5V_RUN
1 PR4731 2
0R0402-PAD
VSS_SENSE 12
PC4717
2
1
2
5
6
7
8
1
2
2
2
2
2
1
BOOT1
UGATE1
20
19
IMON
18
VIN
17
ISUM+
ISUM-
VDD
16
15
1
2
PC4730
SCD22U10V2KX-1GP
PC4712
X02-20100116
UGATE2
PHASE2
12
X01 20091111
2
2
X01 20091111
PC4714
DY
PG4713
1
PR4723
0R0402-PAD
PR4786
100KR2F-L1-GP
11KR2F-L-GP
1
PR4776
SCD01U16V2KX-3GP
2
PU4704
PC4713
GAP-CLOSE-PWR-3-GP
PC4729
SCD22U25V3KX-GP
SCD33U16V3KX-1GP
PC4711
SC330P50V2KX-3GP
DY
PC4715
PG4712
+5V_RUN
10KR2F-2-GP
GAP-CLOSE-PWR-3-GP
1
2
2
PR4759
1R2F-GP
PR4725
82D5R2F-1-GP
12 VCC_SENSE
X02-20091223
IMVP_IMON
6K98R2-GP
PC4721
SC330P50V2KX-3GP
1
SC1U10V2KX-1GP
SC390P50V2KX-GP
2
1K82R2F-1-GP
PC4722
PC4716
262883_FB_VSEN1
2
10KR2F-2-GP
2
SIR460DP-T1-GE3-GP
D
S
D
S
D
S
D
G
X01 20091121
+1.05V_VTT
X02-20091223
0R0402-PAD
2
+PWR_SRC
1R2F-GP
2
PC4732
2
PC4708
PHASE1
21
2
1
LGATE1
22
PR4722
BOOT1 1
2BOOT1_PHASE1
2D2R3J-2-GP
PR4754
1
PC4718
SC330P50V2KX-3GP
4
3
2
1
62883_PWM3
Design Current = 48A
52.8A<OCP<67.2A
PR4751
0R0603-PAD
1
32
VID1
33
VID2
34
VID3
VID0
24
23
ISEN3
PTC4702
+PWR_SRC
2
PC4736
SCD22U25V3KX-GP
X01 20091124
PR4737
PR4775
2D2R5J-1-GP
5
6
7
8
2
2
2
2
2
2
VID4
31
62883_VCCP
1
1
12 VSS_SENSE
25
UGATE1
62883_VIN
ISEN1
62883_ISUM- 14
13
ISL62883HRTZ-T-GP
62883_VDD
RTN
VSEN
GND
PHASE1
ISEN1
41
1
PR4712
35
37
36
VID5
VID6
VSSP1
ISEN2
2
1
PR4714
562R2F-GP
2
2
2
2
39
38
VR_ON
CLK_EN#
DPRSLPVR
ISEN3/FB2
10
PC4707
2
VSUM-
LGATE2
4K02R2F-GP
2
PTC4703
SCD1U50V3KX-GP
1
262883_COMP_R
1
2
PC4740
PR4752
SC150P50V2JN-3GP
324KR2F-GP
LGATE1
1
2
PC4710
SCD22U16V3KX-1-GP
26
ISEN2
X02-20091223
2
3K65R2F-1-GP
SC10U25V6KX-1GP
1
2
PC4735
SC22P50V2JN-4GP
PWM3/LGATE1#
FB
27
VSUMPR4770
1
DY
10KR2F-2-GP
2
SC10U25V6KX-1GP
ISEN3
1
COMP
PHASE2
B00T2_R
2
SC10U25V6KX-1GP
1
2
PC4738
SC33P50V2JN-3GP
ISEN2
1PC4702
2
VCCP
28
2
1
PR4756
1
PR4767
1
PR4742
1
PR4716
1
PR4738
SI7686DP-T1-GP
S
D
D
S
D
S
D
G
2
DY
9
LGATE2
VW
2D2R3J-2-GP
PC4709
DY
0R2J-2-GP
8
ISEN3
NTC
UGATE2
SCD22U16V3KX-1-GP
PR4744
1
7
62883_FB
SCD22U25V3KX-GP
SCD22U25V3KX-GP
PC4719
SC1KP50V2KX-1GP
C
62883_COMP
2
VSSP2
BOOT2
SC1U10V2KX-1GP
1
6
PHASE2
VR_TT#
5
62883_VW
RBIAS
30
29
SC1U10V2KX-1GP
SCD01U25V2KX-3GP
PC4737
1
2
PR4726
8K06R2F-GP
4
BOOT2
UGATE2
12
DY2
3
VSUM+
PSI#
11
1
40
62883_CLK_EN#
PR4735
62883_DPRSLPVR
PR4749
62883_VR_ON
PR4773
62883_VID6
PR4718
62883_VID5
PR4755
62883_VID4
PR4746
62883_VID3
PR4730
62883_VID2
PR4762
62883_VID1
PR4729
62883_VID0
PR4766
2
1
2
6266A_NTC_R1
1
DY 2
PR4774
4K02R2F-GP
PGOOD
2
ISEN1
+5V_RUN
PR4772
1
PG4706
PR4771
DY2 NTC-470K-1-GP
1
DY
LGATE1
X01 20091111
GAP-CLOSE-PWR-3-GP
NTC 470K close to H/S MOSFET of Phase1
1
2 62883_PGOOD
PR4704
0R0402-PAD
1
2 62883_PSI#
PR4733
0R0402-PAD
1
2 62883_RBIAS
PR4781
147KR2F-GP
1
DY 2H_PROCHOT#_R
PR4758
4K02R2F-GP 62883_NTC
DY
PG4708
12 PSI#
PU4703
2
IND-D36UH-9-GP
GAP-CLOSE-PWR-3-GP
37 IMVP_PWRGD
9 H_PROCHOT#
1
D
1
SIR460DP-T1-GE3-GP
D
S
D
S
D
S
D
G
PU4701
PR4720
1K91R2F-1-GP
+VCC_CORE
PL4701
PHASE1
PR4745
1K91R2F-1-GP
+3.3V_RUN
2
5
6
7
8
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_VID0
UGATE1
X02-20091223
PC4705
X02-20100116
4
3
2
1
1
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
0R0402-PAD
1
2
SE100U25VM-11GP
1
2
SE100U25VM-11GP
PU4702
PC4704
DY
SCD1U50V3KX-GP
+3.3V_RUN
PC4703
SC10U25V6KX-1GP
D
TC4703
DY
12
SI7686DP-T1-GP
D
S
D
S
D
S
D
G
TC4702
H_VID[6..0]
SC10U25V6KX-1GP
RB551V-30-2GP
SC10U25V6KX-1GP
DY
DY
PC4706
PM_SLP_S3# 22,37,42,50,51,89
2
K
1
X01 20091111
1
A
2
7 VR_CLKEN#
+PWR_SRC
2
+PWR_SRC
PM_DPRSLPVR 12
IMVP_VR_ON 37
D4701
1
5
A
1R2F-GP
2
10KR2F-2-GP
2
10KR2F-2-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
ISL62883_CPU_CORE
Size
A2
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
47
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
48
of
92
5
4
3
2
1
TPS51218 for +1.05V_VTT
+PWR_SRC
+PWR_SRC_VTT
PG4901
1
2
GAP-CLOSE-PWR
PG4902
1
2
+PWR_SRC_VTT
GAP-CLOSE-PWR
PG4903
1
2
2
2
1
DY
1
PTC4901
PTC4902
2
1
2
1
2
1
1
2
2
PC4911
VTT_SENSE 12
PR4906
10R2J-2-GP
R1
Vout=0.704V*(R1+R2)/R2
PR4909
100KR2J-1-GP
PR4908
10KR2J-3-GP
51218_VTT_VFB
2
X01
10KR2F-2-GP
PR4907
2
1+1.05V_VTT_VOUT
2
1
SC330P50V2KX-3GP
5
6
7
8
DY
1
PC4910
DY
C
1
C
1
2
1
1
5
6
7
8
1
151218_SW_GND_VTT 2
4
3
2
1
4
3
2
1
5
6
7
8
2
+3.3V_ALW
2
4
3
2
1
4
3
2
1
5
6
7
8
1
1
2
2
1
SIS402DN-T1-GE3-GP
S
S
S
G
SIS402DN-T1-GE3-GP
S
S
S
G
PC4901
SC1KP50V2KX-1GP
PU4905
PG4916
+1.05V_VTT
SE330U2VDM-L-GP
D
D
D
D
D
D
D
D
PU4904
DY 2D2R5J-1-GP
SE330U2VDM-L-GP
PR4905
SCD1U10V2KX-5GP
PC4909
SC1U10V2KX-1GP
PC4912
+3.3V_RUN
x01 change tolerant 20091117
PL4901
1
2
IND-D56UH-12-GP
SC4D7U6D3V3KX-GP
TPS51218DSCR-GP-U1
DIS(Arrandale 1.05V_VTT)
Design Current = 20.57A
30.79A<OCP<36.39A
X02-20100116
+5V_ALW
51218_DRVL_VTT
D
PC4906
PC4908
SCD1U25V3KX-GP
PR4902
2D2R3J-2-GP
1
251218_VBST_VTT12
1
GAP-CLOSE-PWR-3-GP
PR4904
470KR2F-GP
DY
51218_VBST_VTT
51218_DRVH_VTT
51218_SW_VTT
PC4903
X02-20091223
11
10
9
8
7
6
GND
VBST
DRVH
SW
V5IN
DRVL
SCD1U25V2KX-GP
2
0R0402-PAD
PGOOD
TRIP
EN
VFB
CCM
PC4904
1
PR4903
1
2
3
4
5
SC10U25V6KX-1GP
RUNPWROK
PU4901
51218_VTT_TRIP
51218_VTT_EN
51218_VTT_VFB
51218_VTT_CCM
2
78K7R2F-GP
PU4903
SIS406DN-T1-GE3-GP
S
S
S
G
37,50 1.05VTT_PWRGD
1
PR4901
50,51,89,90
SIS406DN-T1-GE3-GP
S
S
S
G
M96_X01-20091124
PU4902
DY
X01
PC4902
D
D
D
D
GAP-CLOSE-PWR
D
D
D
D
GAP-CLOSE-PWR
PG4907
1
2
SC10U25V6KX-1GP
X02-20100111
2
X01 EMI stuff 20091118
GAP-CLOSE-PWR
PG4904
1
2
SC10U25V6KX-1GP
D
4
+1.05V_VTT
1
R2
2
DY
H_VTTPWRGD_R
20KR2F-L-GP
5
3
PC4913
PR4910
6
2
2N7002EDW-GP
PR4911
1KR2J-1-GP
84.27002.F3F
2
1
2
SCD1U10V2KX-5GP
1
1
2
PQ4901
1.05VTT_PWRGD
H_VTTPWRGD
A00 20100329
H_VTTPWRGD 9
Frequency setting
470K -->290KHz
200K -->340KHz
100K -->380KHz
39K -->430KHz
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/[email protected]/ 84.00402.037
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51218_+1.05V_VTT
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A2
Document Number
Date:
Tuesday, April 06, 2010
Rev
A00
Berry
Sheet
1
49
of
92
5
4
3
2
1
SSID = PWR.Plane.Regulator_1p5v0p75v
1
+5V_ALW
x01-20091124
5
PR5001
5D1R3J-GP
+5V_ALW
S3 Power Reduction X01 20091111
PQ5003
1
2
1
2
2
PC5008
SC1U10V2KX-1GP
2
5
6
7
8
PU5002
GAP-CLOSE-PWR
PG5006
2
1
GAP-CLOSE-PWR
Design Current = 14.45A
22.71A<OCP< 26.84A
S3
Lo
Hi
On
On
Off(Hi-Z)
S4/S5
Lo
Lo
Off
Off
Off
PC5022
SC330P50V2KX-3GP
TPS51116_VDDQSNS
1
1
PTC5001
2
DY
2
1
2
PC5021
SCD1U10V2KX-5GP
1
2
PC5020
SC4D7U6D3V3KX-GP
2
1
5
6
7
8
1
2
1
DY
PTC5002
x01 change tolerant 20091117
1
On
TPS51116_PHS_SET
PG5017
GAP-CLOSE-PWR-3-GP
On
PR5012
2D2R5F-2-GP
1
On
DY
2
VTT
Hi
PU5004
DY
4
3
2
1
DY
PC5023
SC18P50V2JN-1-GP
1
TPS51116_VDDQSET
2
PR5013
30KR2F-GP
X02-20100201
2
VTTREF
Hi
B
IND-1D5UH-34-GP
SE330U2VDM-L-GP
VDDR
PU5003
x01 change to 330uF 20091124
2
SE330U2VDM-L-GP
S5
S0
1
SIR460DP-T1-GE3-GP
S
S
S
G
TPS51116_LGT
S3
TPS51116_PHS
2
PC5019
SCD1U25V3KX-GP
GAP-CLOSE-PWR
+1.5V_SUS
PL5001
4
3
2
1
TPS51116_VBST1 1
GAP-CLOSE-PWR
PG5016
2
1
x01 change tolerant 20091117
State
X02-20100116
TPS51116_UGT
5
6
7
8
1
2
1
+0.75V_DDR_VTT
PG5001
1
D
D
D
D
PC5018
SC10U6D3V5MX-3GP
2
SIR460DP-T1-GE3-GP
S
S
S
G
PC5017
SC10U6D3V5MX-3GP
2
1
2
+0D75V_DDR_P
D
D
D
D
PC5016
SC10U6D3V5MX-3GP
1
2
B
PC5015
SCD1U10V2KX-5GP
4
3
2
1
PC5010
SCD033U16V3KX-GP
DY
1
5
1 PR5011 2
0R0603-PAD
2
+PWR_SRC_1D5V
SI7686DP-T1-GP
S
S
S
G
1TPS51116_REF
3
DY
+V_DDR_REF
GAP-CLOSE-PWR
PG5004
2
1
x01 change tolerant 20091117
2
0R2J-2-GP
1
GND
DY
PC5014
SC4D7U25V5KX-GP
1
PR5010
1
2
6
GAP-CLOSE-PWR
PG5003
2
1
2
VCCA
C
PC5006
SCD1U10V2KX-5GP
DY
PC5013
SCD1U25V2KX-GP
FB
TPS51116_VDDQSET
1
TPS51116_VDDQSNS
9
+PWR_SRC_1D5V
PG5002
1
2
2
8
+PWR_SRC
1D5V_EN
2
0R0402-PAD
1
VDDQS
1
PR5007
22,37 PM_SLP_S4#
+5V_ALW
25
1
2
2
18
17
VTTS
Design Current = 0.7A
PC5004
SCD1U10V2KX-5GP
X02-20091223
PGND1
PGND1
VTT
2
x01 change tolerant 20091117
x01 change tolerant 20091118
TON
24
0D75V_EN 9
DY
PC5012
SC10U25V6KX-1GP
PGND2
PM_SLP_S3#
84.2N702.D31
PC5011
SC10U25V6KX-1GP
1
X02-20091224
1
3
1
19 TPS51116_LGT
D
D
D
D
+0D75V_DDR_P
1
A
DL
22,37,42,47,51,89
2N7002E-1-GP
2
NC#7
DY
S
PR5015
0R2J-2-GP
PR5018
10KR2J-3-GP
2 PR5019 1
0R0402-PAD
PR5003
1 DY
2
0R2J-2-GP
0D75V_EN_L
D
1
VTTIN
7
4
DY
+0D75V_DDR_P
23
DY
1
PC5007
SC1KP50V2KX-1GP
LX
20 TPS51116_PHS
REF
X02-20091223
DY
TPS51116RGER-GP-U
TPS51116_TON
2
0R0402-PAD
VTTEN
2
1
PR5009
PR5017
PQ5001
2
11.5V_RUN_CPU_EN 1 DY PMBS3904-1-GP
4K7R2J-2-GP
PC5024
DY SCD1U10V2KX-5GP
2
1M1R2J-GP
+1.5V_SUS
C
TPS51116_VBST1
EN/PSV
VSSA
DY 2
DH
21 TPS51116_UGT
1
+1.5V_SUS
PR50081
2
2
x01 change tolerant 20091117
+5V_ALW
PR5005
22 TPS51116_VBST 1
0R3J-0-U-GP
NC#12
11
0D75V_EN 10
PC5005
SC1U6D3V2KX-GP
84.2N702.D31
PQ5002
2
2
1D5V_EN
RT: ASM
TI: Non_ASM
2N7002E-1-GP
1.5V_RUN_CPU_EN# G
BST
D
1.05VTT_PWRGD 37,49
+3.3V_RUN
PR5016
100KR2J-1-GP
DY
+1.5V_RUN_CPU
PGD
TPS51116_NC#12 12
1
2
PR5006 620KR2F-GP
15
14
VDDP
ILIM
1
RUNPWROK
DY
.
49,51,89,90
13
PU5001
PD5001
RB551V-30-2GP
.
.
. .
PR5004
20KR2F-L-GP
VDDP
16
2
TPS51116_VDD_R
0D75V_EN
D
S
K
1
2
+PWR_SRC_1D5V
+5V_ALW
2
1
PC5003
SC1U10V2KX-1GP
2
PC5002
+3.3V_RUN SC1KP50V2KX-1GP
PC5001
SC1U10V2KX-1GP
1
.
D
G
18,42 PS_S3CNTRL
+5V_ALW
PC5009
SC10U25V6KX-1GP
TPS51116_VDD
2
14K7R2F-L-GP
.
.
. .
1
2
PR5002
Modified net name
A
VDDQ (V)
VTTREF and VTT
NOTE
GND
2.5
VVDDQSNS/2
DDR
V5IN
1.8
VVDDQSNS/2
DDR2
FB Resistors
Adjustable
VVDDQSNS/2
PR5014
30KR2F-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 220U 2V EEFCX0D221ER 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
Switching freq-->400KHz
Close to VFB Pin (pin5)
2
VDDQSET
<Core Design>
A
Wistron Corporation
1.5 V < VVDDQ < 3 V
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51116_+1.5V_SUS
Size
Document Number
Custom
Rev
Berry
Date:
5
4
3
2
http://laptop-motherboard-schematic.blogspot.com/
A00
Sheet
Monday, March 29, 2010
1
50
of
92
5
4
3
2
1
SSID = PWR.Plane.Regulator_1p8v
APL5930 for +1.8V_RUN
VIN#5
VIN#9
5
9
VOUT#3
VOUT#4
3
4
2
1
PC5114
SC4700P50V2KX-1GP
2
1
1
1
PC5111
PC5112
DY
2
PC5108
1
PR5111
SC22U6D3V5MX-2GP
SC68P50V2JN-1GP
SO-8-P
+1.8V_RUN
PG5105
2
GAP-CLOSE-PW R
PG5108
1
2
GAP-CLOSE-PW R
C
Vout=0.8V*(R1+R2)/R2
PR5110
13K3R2F-L1-GP
2
DY
2
1
APL5930KAI-TRG-GP
C
+1.8V_RUN_P
+1.8V_RUN_P
16K5R2F-2-GP
FB
Design Current =1.23A
2
EN
1
POK
2
8
1
1D8V_RUN_EN
2
0R0402-PAD
2
7
1
PR5109
1
PM_SLP_S3#
1.8V_RUN_POK
2
0R0402-PAD
PC5113
DY
SC22U6D3V5MX-2GP
22,37,42,47,50,89
1
PR5113
5912_1.8V_RUN_FB
49,50,89,90 RUNPW ROK
PU5101
6
X02-20091223
VCNTL
GAP-CLOSE-PW R
GND
GAP-CLOSE-PW R
PG5106
2
1
PC5109
SC10U6D3V5MX-3GP
PC5110
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
PG5107
2
1
D
+1.8V_RUN_VIN
1
+5V_ALW
1
+1.8V_RUN_VIN
2
+3.3V_ALW
2
D
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
APL5930_+1.8V_RUN
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
51
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
52
of
92
5
4
3
2
1
SSID = CPU.GFX.Regulator
+PWR_SRC
+VGFXCORE_PWR_SRC
PG5301
2
1
2
0R0402-PAD
GAP-CLOSE-PWR
PG5305
1
2
51611_VREFF
GAP-CLOSE-PWR
PG5308
1
2
51611_VREFF
1
2
1
2
2
2
5
6
7
8
4
3
2
1
51611_DPRSLP_1
51611_VID6
51611_VID5
51611_VID4
UMA
1
1
2
UMA UMA
2
1
DY
2
1
DY
2
1
DY
2
1
1
2
PG5323
2
2D2R3J-2-GP
2
1
UMA
GAP-CLOSE-PWR-3-GP
DY
GAP-CLOSE-PWR-3-GP
PU5304
5
6
7
8
PU5303
74.51611.073
PG5322
SC470P50V2KX-3GP
2
1
4
3
2
1
5
6
7
8
DY
S
S
S
G
UMA
1
2
IND-D56UH-12-GP
PR5324
SC3300P50V2KX-1GP
5
6
7
8
1
1
2
1
51611_VR_ON
25
51611_CLKEN
17
51611_PHASE
2D2R3J-2-GP
PC5316
1
2 6236A_BOOT_C
1
2
PR5323 UMA
SCD22U16V3KX-2-GP
51611_UGATE
UMA
VID0
16
VID1
15
VID4
12
VID5
11
51611_PGOOD
51611_TRIPSEL
1
PR5316
1
PR5317
1
PR5318
51611_TONSEL
26
VR_ON
51611_OSRSEL
TRIPSEL
51611_ISLEW
28
27
TONSEL
51611_V5FILT
29
ISLEW
51611_DROOP
30
V5FILT
51611_VREFF
32
31
VID6
51611_BOOT
4
3
2
1
2
19
18
PRN5301
13 GFX_DPRSLPVR
13 GFX_VID6
13 GFX_VID5
13 GFX_VID4
+CPU_GFX_CORE
PL5301
51611_RF
1
DRVH
SC2D2U10V3KX-1GP
D
D
D
D
9
IMON
20
2
SIR460DP-T1-GE3-GP
2
VBST
1
UMA
S
S
S
G
1
LL
VR_TT#
Design Current =17.6A
27.2<OCP<32.15A
X02-20100116
21
D
D
D
D
PC5317
THERM
UMA
UMA
DRVL
UMA
PC5301
22
SCD1U25V2KX-GP
SE330U2VDM-L-GP
PTC5302
8
TPS51611RHBR-GP
VSNS
23
UMA
PC5304
SC22U6D3V5MX-2GP
PC5311
7
V5IN
PU5302
SI7686DP-T1-GP
SIR460DP-T1-GE3-GP
PR5325
18K7R2F-GP
6
MODE
UMA
GNDSNS
+5V_ALW
PC5303
UMA
SC22U6D3V5MX-2GP
PC5312
51611_THERM
2
NTC-100K-10-GP
51611_VR_TT
2
0R2J-2-GP
DY
DROOP
GND
5
PGOOD
CSN
DPRSLP
51611_VSNS
CSP
10
4
24
PC5302
UMA
SC22U6D3V5MX-2GP
PC5319
13 GFX_IMON
DY
251611_THERM_R
1
11K8R2F-GP
PR5321
1
PR5322
3
51611_GSNS
CLKEN#
+VGFXCORE_PWR_SRC
SC10U25V6KX-1GP
DY
9 PM_EXTTS#0_C
51611_CSN
GND
DY
S
S
S
G
1
PR5320
C
2
UMA
D
D
D
D
1
51611_CSP
PR5319
1K91R2F-1-GP
SC10U25V6KX-1GP
PU5301
33
X01 20091121
VREF
1
2
PC5315
SCD22U10V2KX-1GP
Close to VGA
DY UMA
1
PR5313
1
PR5314
1
PR5315
1K69R2F-2-GP
GAP-CLOSE-PWR
+3.3V_RUN
10KR2F-2-GP
UMA
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
UMA
DY
UMA
UMA 2
A00-20100224
+3.3V_RUN
DY
PR5301
1
PR5312
1
2
PC5313 SC2D2U10V3KX-1GP
UMA
2 PC5314
SC68P50V2JN-1GP
VID2
1
OSRSEL
UMA
VID3
6263AGND
51611_VREFF
D
GAP-CLOSE-PWR
PG5311
1
2
14
1
2
90K9R2F-GP
51611_VREFF
UMA
13
PR5311
D
4
3
2
1
1
PR5310
GAP-CLOSE-PWR
PG5303
1
2
+3.3V_ALW
X02-20091223
13 GFX_VR_EN
PTC5301
C
SE330U2VDM-L-GP
DYPC5318
51611_LGATE
SRN0J-7-GP
PRN5302
5
6
7
8
13 GFX_VID3
13 GFX_VID2
13 GFX_VID1
13 GFX_VID0
UMA
4
3
2
1
51611_VID3
51611_VID2
51611_VID1
51611_VID0
SRN0J-7-GP
Close to choke (L5301)
PR5327
PR5328
51611_CSP_R
2
1
1
330R2F-GP
PC5320
SC33P50V2JN-3GP
1
1
B
PR5330
86K6R2F-GP
51611_CSP_CSN
DY
UMA
1
1
PR5326
NTC-100K-10-GP
PR5331
29K4R2F-GP
UMA
2
2
PC5322
SC33P50V2JN-3GP
2
2
1
UMA
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
I0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
PC5326
SCD022U50V3KX-GP
1
UMA
PC5321
UMA
SCD022U50V3KX-GP
2
UMA
B
51611_CSP_G
2
UMA
24K3R2F-1-GP
2
1UMA
2
51611_CSP
PR5332
51611_CSN
1
51611_CSN_R
2
UMA
X01
20091124
330R2F-GP
PC5323
2
X01-0713
6263AGND
1
X01 20091118
UMA
+CPU_GFX_CORE
PC5324
SC33P50V2JN-3GP
51611_VSNS
PR5334
100R2F-L1-GP-U
PC5325
1
UMA
1
UMA
UMA
1
SC33P50V2JN-3GP
2
1 PR5333 2
0R0402-PAD
2
X02-20091223
51611_GSNS
PG5324
1
13 VCC_AXG_SENSE
2
SC33P50V2JN-3GP
2
GAP-CLOSE-PWR-3-GP
PG5325
1
13 VSS_AXG_SENSE
2
A
A
PR5335
100R2F-L1-GP-U
1
UMA
2
GAP-CLOSE-PWR-3-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51611_+GFX_CORE(UMA)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A2
Document Number
Date:
Monday, March 29, 2010
Rev
A00
Berry
Sheet
1
53
of
92
x02-20091208
SSID = VIDEO
SSID = Inverter
+3.3V_RUN_VGA
+3.3V_RUN
1
R5407
R5401
DY10KR2J-3-GP
UMA2
0R2J-2-GP
45
46
47
2
2
C5402
SC1U6D3V2KX-GP
1
GFX_PW R_SRC
F5401
1
2
1
R5408
C5406
SC1KP50V2KX-1GP
2
100KR2J-1-GP
1
POLYSW -1D1A24V-GP-U
C5407
SCD1U50V3KX-GP
RN5401
LVDSB_TX1 55
LVDSB_TX1# 55
BLON_OUT_C
LCD_CBL_DET#_C
LCD_TST_C
LCD_DET_G
LVDSB_TX0 55
LVDSB_TX0# 55
1
2
3
4
8
7
6
5
Main:69.50007.A41
Second:69.50007.A31
BLON_OUT 37
LCD_CBL_DET# 37
LCD_TST 37
SRN100J-4-GP
LVDSB_TXC 55
LVDSB_TXC# 55
LVDSA_TXC 55
LVDSA_TXC# 55
LVDSA_TX2 55
LVDSA_TX2# 55
LVDSA_TX1 55
LVDSA_TX1# 55
LVDSA_TX0 55
LVDSA_TX0# 55
GPU_LVDS_DATA 20,82
GPU_LVDS_CLK 20,82
A00-20100204
USB_CAMERA#
USB_CAMERA
1
R5409 1
R5411
+3.3V_CAMERA
2
2 0R0603-PAD
0R0603-PAD
USB_PN13 21
USB_PP13 21
SSID = VIDEO
49
IPEX-CONN40-2R-GP-U
+3.3V_RUN
LCD POWER
+LCDVDD
For Camera GND
Q5401
1 D
2 D
3 G
20.F1093.040
Close to LVDS connector
2
330KR2J-L1-GP
2
SCD1U25V2KX-GP
LVDSB_TXC
R5406
R5416
150R3J-L-GP
Q5402
1
DY
2
3
5
2
6
1
LCDVDD_1
2N7002EDW -GP
84.27002.F3F
55 LCDVDD_EN
1
+5V_ALW
1
DY
EC5402
SC33P50V2JN-3GP
1
DY
2
DY
1
EC5409
4
LCD_TST_C
EC5401
SC33P50V2JN-3GP
DY
EC5408
SC5D6P50V2CN-1GP
2
1
SC5D6P50V2CN-1GP
2
DY
2
1
DY
C5403
SC10U6D3V5MX-3GP
EC5407
1
EC5406
2
EC5405
SCD1U10V2KX-5GP
LCD_BRIGHTNESS
1
DY 100KR2J-1-GP
LVDSA_TXC
SC5D6P50V2CN-1GP
2
1 R5414 2
0R0603-PAD
LVDSA_TXC#
1
+3.3V_CAMERA
SC5D6P50V2CN-1GP
2
X02-20091222
2
1
Camera Power
SI3456DDV-T1-GE3-GP
FPVCC_CTL1
1
C5409
D 6
D 5
S 4
1
1
R5412
+15V_ALW
LVDSB_TXC#
+3.3V_RUN
+PW R_SRC
Change Poly-fuse
R5405
DY100KR2J-1-GP
LVDSB_TX2 55
LVDSB_TX2# 55
LCD_DET_G
LBKLT_CTL 55
LCD_BRIGHTNESS
1
3.3V_LCD_RUN
LCD_BRIGHTNESS
BLON_OUT_C
LCD_CBL_DET#_C
LCD_TST_C
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
51
100R2J-2-GP
2
2
44
x01 change tolerant 20091117
1
1
43
R5402
+LCDVDD
50
1
C5401
SCD1U10V2KX-5GP
42
2
48
41
INVERTER POWER
+3.3V_RUN
2
0R2J-2-GP
2
GFX_PW R_SRC
LCD1
DIS
2
LVDS CONNECTOR
1
R5404
1
3.3V_LCD_RUN
For EMI request
x01 change tolerant 20091117
D5401
R5415
2
100KR2J-1-GP
Q5403
3
LCDVCC_EN
1
R2
PDTC144EU-1-GP
2
BAT54C-U-GP
FPVCC_CTL3
3
R1
2
X01 change part-20091116
37 LCD_TST_EN
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
http://laptop-motherboard-schematic.blogspot.com/
LCD/Inverter Connector
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
54
of
92
5
4
3
LVDS Channel A
2
1
Panel BL brightness/Power En/BL En
RN5501
20
20
20
20
D
5
6
7
8
PCH_LVDSA_TX2#
PCH_LVDSA_TX2
PCH_LVDSA_TXC#
PCH_LVDSA_TXC
Impedance:85 ohm
UMA
4
3
2
1
SRN0J-7-GP
4
3
2
1
5
6
7
8
DIS
SRN0J-7-GP
GPU_LVDSA_TX2#
GPU_LVDSA_TX2
GPU_LVDSA_TXC#
GPU_LVDSA_TXC
Impedance:100 ohm
RN5502
20 PCH_VGA_BLEN
20 PCH_LCDVDD_EN
20 PCH_LBKLT_CTL
5
6
7
8
PCH_LVDSA_TX0#
PCH_LVDSA_TX0
PCH_LVDSA_TX1#
PCH_LVDSA_TX1
Impedance:85 ohm
PANEL_BLEN 37
LCDVDD_EN 54
LBKLT_CTL 54
D
5
6
7
8
DIS
4
3
2
1
SRN0J-7-GP
LVDSA_TX0# 54
LVDSA_TX0 54
LVDSA_TX1# 54
LVDSA_TX1 54
UMASRN0J-7-GP
4
3
2
1
GPU_LVDSA_TX0#
GPU_LVDSA_TX0
GPU_LVDSA_TX1#
GPU_LVDSA_TX1
Impedance:100 ohm
4
3
2
1
RN5504
82 VGA_BLEN
82 VGA_LBKLT_CTL
82 VGA_LCDVDD_EN
4
3
2
1
RN5508
82
82
82
82
UMA
SRN0J-7-GP
RN5507
20
20
20
20
5
6
7
8
Impedance:90 ohm
RN5503
82
82
82
82
LVDSA_TX2# 54
LVDSA_TX2 54
LVDSA_TXC# 54
LVDSA_TXC 54
5
6
7
8
Impedance:90 ohm
LVDSA_TX0# 54
LVDSA_TX0 54
LVDSA_TX1# 54
LVDSA_TX1 54
DISSRN0J-7-GP
C
C
LVDS Channel B
RN5505
5
6
7
8
20 PCH_LVDSB_TXC#
20 PCH_LVDSB_TXC
20 PCH_LVDSB_TX0#
20 PCH_LVDSB_TX0
Impedance:85 ohm
UMA
4
3
2
1
LVDSB_TXC# 54
LVDSB_TXC 54
LVDSB_TX0# 54
LVDSB_TX0 54
SRN0J-7-GP
Impedance:90 ohm
RN5510
82
82
82
82
B
4
3
2
1
GPU_LVDSB_TXC#
GPU_LVDSB_TXC
GPU_LVDSB_TX0#
GPU_LVDSB_TX0
Impedance:100 ohm
5
6
7
8
LVDSB_TXC# 54
LVDSB_TXC 54
LVDSB_TX0# 54
LVDSB_TX0 54
DISSRN0J-7-GP
B
RN5509
5
6
7
8
20 PCH_LVDSB_TX1#
20 PCH_LVDSB_TX1
20 PCH_LVDSB_TX2#
20 PCH_LVDSB_TX2
Impedance:85 ohm
4
3
2
1
LVDSB_TX1# 54
LVDSB_TX1 54
LVDSB_TX2# 54
LVDSB_TX2 54
UMASRN0J-7-GP
Impedance:90 ohm
RN5506
82
82
82
82
4
3
2
1
GPU_LVDSB_TX1#
GPU_LVDSB_TX1
GPU_LVDSB_TX2#
GPU_LVDSB_TX2
Impedance:100 ohm
DIS
5
6
7
8
LVDSB_TX1# 54
LVDSB_TX1 54
LVDSB_TX2# 54
LVDSB_TX2 54
SRN0J-7-GP
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LVDS_Switch
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Rev
Berry
Date:
Monday, March 29, 2010
A00
Sheet
1
55
of
92
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
LVDS_Switch
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
56
of
92
5
4
3
HDMI Level Shifter & CONNECTOR
1
HDMI CONN
+3.3V_RUN
+3.3V_RUN
22
20
1
44
45
R5703
R5704
47
48
20,82 HDMI_PCH_DATA2#
20,82 HDMI_PCH_DATA2
+3.3V_RUN
2
2
UMA
DY
HDMI_PC0
HDMI_PC1
1 4K7R2J-2-GP
1 4K7R2J-2-GP
3
4
OUT_D2OUT_D2+
IN_D3IN_D3+
OUT_D3OUT_D3+
IN_D4IN_D4+
OUT_D4OUT_D4+
UMA
PC0
PC1
SDA
SCL
HPD
HDMI_OE#
1 UMA 2 HDMI_DDC_EN
R5708
4K7R2J-2-GP
HDMI_LS_TX1#
HDMI_LS_TX1
SRN0J-6-GP
1
2
14
13
HDMI_LS_TX2#
HDMI_LS_TX2
SRN0J-6-GP
1
2
UMA
UMA
UMA
8
9
7
HDMI_DATA1#
HDMI_DATA1
HDMI_DATA2#
HDMI_DATA2
6
10
25
32
REXT
RT_EN#
OE#
DDC_EN
PCH_HDMI_DATA 20
PCH_HDMI_CLK 20
HDMI_PCH_DET
HPD_SINK
SDA_SINK
SCL_SINK
HPD_HDMI_CON
DDC_DATA_HDMI
DDC_CLK_HDMI
30
29
28
DY
2
D
G
SKT-HDMI19P-69-GP
22.10296.211
x01 change tolerant 20091117
+3.3V_RUN_VGA
DIS
1
R5711
20
R5707
20KR2J-L2-GP
R5710
200KR2J-L1-GP
C5705
SCD1U10V2KX-5GP
2HDMI_HPD_B
150KR2J-L1-GP
Q5702
PMBS3904-1-GP
1
DIS
HDMI_HPD_DET
DY
82
2
R5712 DIS
10KR2J-3-GP
2
PS8101-GP
Change from 5.1K to 4.7K.
1st Parade 71.P8101.003
2nd Pericom 71.03411.B03
HPD_HDMI_CON
1
17
16
HDMI_DATA0#
HDMI_DATA0
D
84.2N702.D31
+5V_RUN
DDC_CLK_HDMI
DDC_DATA_HDMI
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3.3V_RUN
SRN0J-6-GP
1
2
HDMI_CLK#
HDMI_CLK
1
5
12
18
24
27
31
36
37
43
49
DY
HDMI_REXT
2
R5706
4K7R2J-2-GP
1
UMA
499R2F-2-GP
HDMI_LS_TX0#
HDMI_LS_TX0
RN5703
4
3
RN5704
4
3
RN5706
4
3
RN5707
4
3
2
1
2
20
19
UMA
1
R5705
HDMI_LS_TXC#
HDMI_LS_TXC
Q5701
2N7002E-1-GP
.
.
. .
HDMI_CLK#
2
IN_D2IN_D2+
SRN0J-6-GP
1
2
23
22
HDMI_OE#
UMA .
HDMI_DATA0#
HDMI_CLK
1
20,82 HDMI_PCH_DATA1#
20,82 HDMI_PCH_DATA1
OUT_D1OUT_D1+
HDMI_DATA1#
HDMI_DATA0
2
41
42
20,82 HDMI_PCH_DATA0#
20,82 HDMI_PCH_DATA0
Close to HDMI Connector
IN_D1IN_D1+
R5709
20KR2J-L2-GP
1
38
39
20,82 HDMI_PCH_CLK#
20,82 HDMI_PCH_CLK
HDMI_DATA2#
HDMI_DATA1
HPD_HDMI_CON
2
2
HDMI_CCT2
HDMI_CCT1
35
34
U5701
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
UMA
Impedance:100 ohm
UMA
HDMI_DATA2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23
DY
NC#35
NC#34
C5701
2
11
15
21
26
33
40
46
1
SCD1U10V2KX-5GP
1
UMA
2
2
UMA
C5714
SCD1U10V2KX-5GP
1
C5715
SCD1U10V2KX-5GP
1
UMA
2
2
C5716
SCD1U10V2KX-5GP
1
UMA
D
SCD1U10V2KX-5GP
x01 change to 10V tolerant 20091117
C5717
R5701
4K7R2J-2-GP
DY
4K7R2J-2-GP
3
1
1
R5702
+3.3V_RUN
1
HDMI1
S
SSID = VIDEO
2
C
C
Impedance:100 ohm
HDMI DISCRETE/ UMA Co-lay
2
1
DIS
C5706
C5707
HDMI_DATA0#_R
HDMI_DATA0_R
3
4
RN5709
SRN0J-6-GP
RN5710
2
1
SRN0J-6-GP
3
4
1DIS 2
1DIS 2
C5708
C5709
1DIS 2
1DIS 2
HDMI_CLK#
HDMI_CLK
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA0#
HDMI_DATA0
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DIS
3
4
HDMI_DATA1#_R
HDMI_DATA1_R
C5713
C5710
1DIS 2
1DIS 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA1#
HDMI_DATA1
HDMI_DATA2#_R
HDMI_DATA2_R
C5711
C5712
1DIS 2
1DIS 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA2#
HDMI_DATA2
1
7
4
1OE
2OE
4
3
5V Tolerance
DY
1A
2A
VCC
GND
1B
2B
2
5
GPU_HDMI_CLK 82
GPU_HDMI_DATA 82
DDC_CLK_HDMI
DDC_DATA_HDMI
3
6
TSCBTD3305CPWR-GP
1
499R2F-2-GP
1
499R2F-2-GP
DIS
DIS
DIS
3
4
SRN0J-6-GP
2
R5721
2
2
1
R5722
1
499R2F-2-GP
1
499R2F-2-GP
DIS
2
R5719
R5720
1
499R2F-2-GP
DIS
2
1
499R2F-2-GP
DIS
R5718
2
DIS
2
DIS
2
2
R5715
RN5705
GPU_HDMI_CLK
GPU_HDMI_DATA
D
HDMI_PLL_GND
R5717
Close to HDMI Connector
Impedance:100 ohm
1
499R2F-2-GP
SRN0J-6-GP
R5716
RN5711
Impedance:100 ohm
DIS
1
499R2F-2-GP
2
1
DIS
HDMI_PCH_DATA2#
HDMI_PCH_DATA2
RN5701
SRN1K5J-GP
DY
U5702
+5V_RUN
8
HDMI_PCH_DATA1#
HDMI_PCH_DATA1
4
3
RN5702
SRN2K2J-1-GP
+3.3V_RUN_VGA
1
2
DIS
HDMI_CLK#_R
HDMI_CLK_R
1
2
HDMI_PCH_DATA0#
HDMI_PCH_DATA0
RN5708 SRN0J-6-GP
2
3
1
4
+5V_RUN
x01 change tolerant 20091117
Close to Level Shift
HDMI_PCH_CLK#
HDMI_PCH_CLK
+3.3V_RUN_VGA
Q5703
2N7002E-1-GP
.
DIS
B
B
S
84.2N702.D31
1
+5V_RUN
G
.
.
. .
R5714
100KR2J-1-GP
2
DY
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
HDMI Level Shifter/Connector
Size
A2
Document Number
Date:
Monday, March 29, 2010
Rev
A00
Berry
Sheet
1
57
of
92
5
4
3
2
1
SSID = User.Interface
ITP Connector
H_CPURST# use pull-up Resistor close
ITP connector 500 mil ( max ),
others place near CPU side.
D
CPU
D
ITP Connector
TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
C
C
SSID = Thermal
Fan Connector
B
B
3
*Layout* 15 mil
39 EMC2102_FAN_TACH
1
FAN1
AFTP5801
1
5
3
2
1
4
39 EMC2102_FAN_DRIVE
AFTP5802
1
EMC2102_FAN_TACH
AFTP5803
1
EMC2102_FAN_DRIVE
1
K
FOX-CON3-6-GP-U
D5801
RB551V-30-2GP
A
2
C5801
SC10U6D3V5MX-3GP
20.D0210.103
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
ITP/Fan Connector
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
58
of
92
SSID = SATA
SATA HDD Connector
2
DY DY
2
C5904
SC10U6D3V5MX-3GP
1
1
+3.3V_RUN
HDD1
C5901
SCD1U10V2KX-5GP
2
C5905
SC10U10V5KX-2GP
1
2
1
+5V_RUN
C5906
SCD1U10V2KX-5GP
x01 Change tolerant 20091117
24 SATA_TXP0
24 SATA_TXN0
C5903
C5902
1
1
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
SATA_RXP0
SATA_RXN0
x01 Change tolerant 20091117
V33
V33
V33
P7
P8
P9
V5
V5
V5
P13
P14
P15
V12
V12
V12
S2
S3
A+
A-
S6
S5
B+
B-
16
17
18
16
17
18
GND
GND
GND
GND
GND
GND
GND
GND
S1
S4
S7
P4
P5
P6
P10
P12
DAS/DSS
P11
SKT-SATA7P-15P-17-GP
62.10065.C71
ODD Connector
ODD1
8
NP1
S1
C5907 1
C5908 1
2SCD01U16V2KX-3GP
2SCD01U16V2KX-3GP
SATA_RXN1_C 24
SATA_RXP1_C 24
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil
x01 Change tolerant 20091117
SKT-SATA7P+6P-42-GP
+5V_RUN
1
P1
P2
P3
P4
P5
P6
NP2
9
C5909
SCD1U10V2KX-5GP
1
SATA_TXP1 24
SATA_TXN1 24
SATA_RX1-_C
SATA_RX1+_C
C5910
SC10U10V5KX-2GP
2
S2
S3
S4
S5
S6
S7
2
24 SATA_RXP0_C
24 SATA_RXN0_C
P1
P2
P3
x01 Change tolerant 20091117
62.10065.581
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
http://laptop-motherboard-schematic.blogspot.com/
Size
A3
Document Number
Date:
Monday, March 29, 2010
HDD/ODD
Rev
Berry
A00
Sheet
59
of
92
5
4
3
2
1
SSID = AUDIO
/,1(
287
6SHDNHU
&RQQHFWRU
D
D
SPK1
FOX-CON4-24-GP
BLM18BD601SN1D-GP
30 AUD_HP1_JD#
AUD_HP1_JD#
L6001
X01 modify to GND 20091120
SEC. 20.F0693.004
1
AFTP6002
AFTP6001
AFTP6005
AFTP6007
AFTP6009
1
1
1
1
1
AUD_HP1_JD#
1
AUD_HP1_JACK_L1
1
AUD_HP1_JACK_R1
AFTP6003
AUD_SPK_LAUD_SPK_L+
AUD_SPK_RAUD_SPK_R+
1
4
1
3
7
8
PHONE-JK383-GP
x02-20091224
AFTP6004
AFTP6008
6
5
2
AUD_HP1_JACK_R1
2
BLM18BD601SN1D-GP
2
1
L6002
EC6006
SC1KP50V2KX-1GP
2
1
1
2
EC6005
SC1KP50V2KX-1GP
2
AUD_HP1_JACK_R2
30 AUD_HP1_JACK_R2
LINEOUT1
AUD_HP1_JACK_L1
2
EC6008
SCD01U16V2KX-3GP
30 AUD_HP1_JACK_L2
1
1
AUD_HP1_JACK_L2
6
1
DY
2
2
DY
EC6004
SC100P50V2JN-3GP
1
EC6003
SC100P50V2JN-3GP
1
DY
2
2
DY
EC6002
SC100P50V2JN-3GP
30 AUD_SPK_L+
30 AUD_SPK_R30 AUD_SPK_R+
2
3
4
1
1
EC6001
SC100P50V2JN-3GP
30 AUD_SPK_L-
EC6007
SCD01U16V2KX-3GP
5
A00-20100406
AFTP6006
600ohm 100MHz
200mA 0.5ohm DC
1
22.10133.K31
C
C
0,&,1
X01 modify to GND 20091120
30 AUD_VREFOUT_B
2
1
,QWHUQDO
0LFURSKRQH
3
4
RN6001
SRN4K7J-8-GP
MICIN1
2
R6001
1
0R0603-PAD
MIC_IN_L_C
30 MIC_IN_R
2
R6002
1
0R0603-PAD
MIC_IN_R_C
2
5
6
1
30 INT_MIC_L_R
MIC1
MICROPHONE-40-GP-U1
EC6009
SC1KP50V2KX-1GP
23.42143.001
2
B
MIC1 is in DIP
1
2
30 MIC_IN_L
8
7
3
1
4
X02-20091222
B
PHONE-JK383-GP
22.10133.K31
1
1
2
2
30 EXT_MIC_JD#
EC6011
SC100P50V2JN-3GP
1
MIC_IN_L_C
1
MIC_IN_R_C
AFTP6011
AFTP6012
1
EXT_MIC_JD#
AFTP6013
SC100P50V2JN-3GP
EC6010
1
AFTP6010
DY
X01 modify to GND 20091120
X02-20100206
1
EC6012
2
SCD1U10V2KX-5GP
1
EC6013
2
SCD1U10V2KX-5GP
1
EC6014
2
SCD1U10V2KX-5GP
DY
1
EC6015
2
SCD1U10V2KX-5GP
1
EC6016
2
SCD1U10V2KX-5GP
<Core Design>
A
DY
1
EC6017
A
2
SCD1U10V2KX-5GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Document Number
Date:
Monday, April 26, 2010
Audio Jack
Rev
Berry
A00
Sheet
1
60
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
61
of
92
5
4
3
2
1
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH
+3.3V_RUN
2
C6201
SC10U6D3V5MX-3GP
RN6201
SRN4K7J-10-GP
C6202
SCD1U10V2KX-5GP
D
2
DY
D
8
7
6
5
1
1
+3.3V_RUN
1
2
3
4
x01 change tolerant 20091117
PCH_SPI_HOLD_0#
+3.3V_RUN
U6201
8
7
6
5
PCH_SPI_HOLD_0#
PCH_SPI_CLK 24
PCH_SPI_DO 24
MX25L3205DM2I-12G-GP
EC6203
SC4D7P50V2CN-1GP
1
VCC
NC#7
SCK
SI
DY DY
EC6204
SC4D7P50V2CN-1GP
2
DY
CS#
SO
WP#
GND
+KBC_PW R
1
+KBC_PW R
4
3
1
R6203
100KR2J-1-GP
DY
C
C6204
SCD1U10V2KX-5GP
2
C6203
SC10U6D3V5MX-3GP
X02 20091221
1
SPI FLASH ROM (256K byte) for KBC
2
C
1
2
3
4
PCH_SPI_DI_R
PCH_SPI_W P#
2
EC6202
SC4D7P50V2CN-1GP
2
R6202
15R2J-GP
1
1
1
2
PCH_SPI_CS0#
24 PCH_SPI_CS0#
24 PCH_SPI_DI
RN6202
SRN100KJ-6-GP
DY
1
2
2
x01 change tolerant 20091117
EC_SPI_HOLD#
+KBC_PW R
U6202
37 EC_SPI_CS#
37 EC_SPI_DI
37 EC_SPI_W P#_R
1
1
2
2
0R0402-PAD
0R0402-PAD
EC_SPI_DI_R
EC_SPI_W P#
CS#
SO
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI
EC_SPI_HOLD#
EC_SPI_CLK 37
EC_SPI_DO 37
1
DY DY
B
EC6206
SC4D7P50V2CN-1GP
1
2
EC6205
SC4D7P50V2CN-1GP
2
MX25L2005C-12G-GP
R6201
10KR2J-3-GP
1
R6208
100KR2J-1-GP
2
DY DY
2
EC6201
SC4D7P50V2CN-1GP
B
2
1
1
R6205
R6206
1
2
3
4
X02-20091221
+3.3V_RTC_LDO
SSID = RBATT
U6203
+RTC_CELL
2
+RTC_VCC
RTC1
3
2
R6210
1
1
2
NP1
NP2
2
1KR2J-1-GP
1
C6205
SC1U6D3V2KX-GP
RTC_PW R
1
SDMG0340LC7F-GP-U
1
PWR
GND
NP1
NP2
AFTP6203
BAT-CON2-1-GP-U
Width=20mils
A
<Core Design>
A
62.70001.011
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
+RTC_VCC
AFTP6202
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Document Number
Date:
Monday, March 29, 2010
Flash/RTC
Rev
Berry
A00
Sheet
1
62
of
92
5
4
3
2
1
SSID = USB
Close to I/O connector
IO Board USB Power
Support 2A
+5V_ALW
+5V_USB1
U6301
1
C6301
DY
37 USB_PW R_EN#
VOUT#8
VOUT#7
VOUT#6
OC#
8
7
6
5
D
1
GND
VIN
VIN
EN#
C6302
SC1U10V2KX-1GP
UP7534BRA8-15-GP
2
SCD1U10V2KX-5GP
USB POWER SW
Main UP7534BRA8-15 P/N:74.07534.079
SEC AP2101MPG-13 P/N: 74.02101.079
1
2
3
4
2
at least 80 mil
D
at least 80 mil
USB_OC#8_9 21
x01 Change tolerant 20091117
CRT Board USB Power
Close to CRT Board connector
C
C
Support 2A
+5V_ALW
+5V_USB2
U6302
37 USB_PW R_EN#
GND
VIN
VIN
EN#
VOUT#8
VOUT#7
VOUT#6
OC#
8
7
6
5
1
1
2
3
4
C6304
SC1U10V2KX-1GP
UP7534BRA8-15-GP
2
SCD1U10V2KX-5GP
DY
2
C6303
1
at least 80 mil
at least 80 mil
USB_OC#0_1 21
x01 Change tolerant 20091117
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Document Number
USB Power SW
Rev
Berry
Date:
Monday, March 29, 2010
A00
Sheet
1
63
of
92
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
Date: Wednesday, February 10, 2010
5
4
3
Rev
Berry
2
A00
Sheet
64
of
1
92
A
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
65
of
92
5
4
3
2
1
SSID = User.Interface
Power LED(White)
+5V_ALW
Q6602
R2
PW RLED#_C
B
E
R1
LED_PW R
C
1
D
37 W HITE_LED#_KBC
24 SATA_LED#
1
2
4
3
W HITE_LED_BAT#
SATA_LED#_C
84.00143.M11
DYSC220P50V2KX-3GP
2
PDTA143ET-GP
RN6601
SRN15KJ-3-GP
2
R6603
1 POW ER_SW _LED_B
1KR2J-1-GP
2
R6609
1 POW ER_SW _LED_C
1KR2J-1-GP
4
3
D
SATA HDD LED(White)
AMBER_LED_BAT#
PW RLED#_C
+5V_RUN
SRN15KJ-3-GP
Q6601
X02-20100108
R2
E
R6604
B
R1
SATA_LED_R
C
2
PDTA143ET-GP
DY
84.00143.M11
2
1
SATA_LED#_C
EC6604
SC220P50V2KX-3GP
1
2
PW R_LED_B
1
1KR2J-1-GP
X02-20100203
RN6602
37 AMBER_LED#_KBC
37 PW RLED#
2
R6601
EC6601
1
1KR2J-1-GP
SATA_LED
Battery LED1(White)
R2
W HITE_LED_BAT#
C
+5V_ALW
Q6603
LEDBD1
E
R6602
B
R1
W HITE_LED_BAT
2
1
C
EC6602
SC220P50V2KX-3GP
C
PDTA143ET-GP
DY
2
84.00143.M11
7
BAT_W HITE
1
1KR2J-1-GP
PW R_LED_B
1
SATA_LED
BAT_W HITE
BAT_AMBER
2
3
4
5
6
8
Battery LED2(Amber)
+5V_ALW
Q6604
R2
E
R6606
B
R1
AMBER_LED_BAT#
C
AMBER_LED_BAT
1
2
1KR2J-1-GP
BAT_AMBER
1
PDTA143ET-GP
DY
2
84.00143.M11
B
ACES-CON6-13-GP
EC6603
SC220P50V2KX-3GP
B
Power button LED(White)
1
R6605
37 KBC_PW RBTN#
PW RBTN1
2
100R2J-2-GP
5
1
X01 20091111
+5V_ALW
Q6605
2 PW R_BTN_LED#_C
15KR2J-1-GP
B
A00-20100205
E
DY
C
R1
A
DY
R2
37 PW R_BTN_LED#
1
R6607
A00-20100203
PDTA143ET-GP
84.00143.M11
POW ER_SW _LED_R
1
R6610
KBC_PW RBTN#_C
POW ER_SW _LED_C
POW ER_SW _LED_B
2
3
4
6
2 POW ER_SW _LED_C
DY 100R2J-2-GP
ACES-CON4-10-GP-U
20.K0320.004
<Core Design>
A
1 DY
2 POW ER_SW _LED_B
R6608
100R2J-2-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
LED Bard/Power Button
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
66
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
67
of
92
5
4
3
SSID = KBC
2
1
SSID = Touch.Pad
Internal KeyBoard Connector
D
D
TouchPad Connector
A00-20100203
KB1
1
AFTP6801
31
1
KB_DET# 37
AFTP6802
AFTP6803
AFTP6804
AFTP6805
AFTP6806
AFTP6807
AFTP6808
AFTP6809
AFTP6810
AFTP6811
AFTP6812
AFTP6813
AFTP6814
AFTP6815
AFTP6816
AFTP6817
AFTP6818
AFTP6819
AFTP6821
AFTP6823
AFTP6822
AFTP6824
AFTP6825
AFTP6826
AFTP6827
+5V_RUN
+5V_RUN
2
1
1
x01 change tolerant 20091117
37
KCOL[0..16]
37
RN6801
SRN10KJ-5-GP
TPAD1
6
4
3
2
DY DY
2
C6802
SC33P50V2JN-3GP
AFTP6820
20.K0320.004
AFTP6829
AFTP6830
AFTP6831
1
1
1
+5V_RUN
TPCLK
TPDATA
KB Backlight Connector
A00-20100205
+5V_RUN
B
+5V_KB_BL
L6801
2
DY
2
DY
2
0R2J-2-GP
C6805
SCD1U10V2KX-5GP
20.K0320.004
KBLIT1
5
R6804
DY
1
2KB_LED_DET_C
100R2J-2-GP
2
2
DY
A
SCD1U10V2KX-5GP
DY
100KR2J-1-GP
C6806
KB_BL_CTRL#
R6803
2
3
4
DY
+5V_KB_BL
KB_LED_BL_DET
KB_BL_CTRL#
6
ACES-CON4-10-GP-U
1
1
1
1
AFTP6832
AFTP6833
AFTP6834
AFTP6835
D
1
37 KB_LED_BL_DET
1
SC10U10V5KX-2GP
1
R6802
DY
BLM18PG181SN1D-GP
2
DY
FUSE-D5A6V-2-GP
1
1
C6804
KB_LED_PW R 1
1
F6801
1
5
ACES-CON4-10-GP-U
AFTP6828
B
2
C6803
SC33P50V2JN-3GP
1
ACES-CON30-8-GP
<Core Design>
Q6801
P8503BMG-GP
DY
A
Wistron Corporation
G
1
37 KB_BL_CTRL
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
S
R6801
100KR2J-1-GP
Title
2
DY
5
C
1
1
1
37 TPCLK
37 TPDATA
1
32
DY
C6801
SCD1U10V2KX-5GP
2
KROW [0..7]
2
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
4
KROW 7
KROW 6
KROW 4
KROW 2
KROW 5
KROW 1
KROW 3
KROW 0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Key Board/Touch Pad
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
68
of
92
5
4
3
2
1
+3.3V_ALW
AFTP6901
AFTP6902
+3.3V_ALW
LID_CLOSE#_1
1
1
x01 Change tolerant 20091117
D
1
D
+3.3V_ALW
1
2
C6903
SCD1U10V2KX-5GP
R6901
100KR2J-1-GP
2
DY
LID_CLOSE#
DY
2
1
37 LID_CLOSE#
HALLSW1
2
R6902
C6902
SCD047U16V2KX-1-GP
1
0R0402-PAD
LID_CLOSE#_1
2
VDD
3
OUT
VSS
1
S-5711ACDL-M3T1S-GP
X02-20091223
AFTP6903
1
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Rev
Berry
Date: Monday, March 29, 2010
5
Hall Sensor
A00
Sheet
69
of
1
92
A
5
4
3
2
1
D
D
+3.3V_RUN
DB1
1
2
3
4
5
6
7
8
9
10
11
12
24,37 LPC_LAD0
24,37 LPC_LAD1
24,37 LPC_LAD2
24,37 LPC_LAD3
24,37 LPC_LFRAME#
9,21,37,76,78,80 PLT_RST#
21 PCLK_FWH
DY
MLX-CON10-7-GP
C
C
20.D0183.110
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Rev
Berry
Date: Monday, March 29, 2010
5
Dubug connector
A00
Sheet
70
of
1
92
A
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
RESERVED
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
Date: Wednesday, February 10, 2010
5
4
3
Rev
Berry
2
A00
Sheet
71
of
1
92
A
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
RESERVED
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
72
of
92
5
4
3
2
1
SSID = User.Interface
Bluetooth Module conn.
D
D
BT1
AFTP7302
1
AFTP7304
AFTP7305
AFTP7314
1
1
1
BLUETOOTH_DET#
1
W LAN_ACT
BDC_ON
BLUETOOTH_EN
BT_LED
BLUETOOTH_GPIO3
BLUETOOTH_GPIO5
3
5
7
9
11
13
15
NP1
2
4
6
8
10
12
14
NP2
16
+3.3V_RUN
BT_ACT
x01 change tolerant 20091118
USB_PP5
USB_PN5
1
1
C7301
2
AFTP7301
1
SC2D2U6D3V3KX-GP
AFTP7313
HRS-CONN14D-GP-U
20.F0987.014
21 USB_PP5
21 USB_PN5
76 BT_ACT
37 BLUETOOTH_EN
76 W LAN_ACT
BT_ACT
BLUETOOTH_EN
W LAN_ACT
AFTP7316
AFTP7317
AFTP7315
AFTP7318
AFTP7319
AFTP7320
1
1
1
1
1
1
W LAN_ACT
BLUETOOTH_EN
BT_ACT
+3.3V_RUN
USB_PP5
USB_PN5
DY
R7304
10KR2J-3-GP
1
EC7302
SC220P50V2KX-3GP
2
1
2
DY
2
1
C
R7303
100KR2J-1-GP
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Document Number
Date:
Monday, March 29, 2010
Bluetooth
Rev
Berry
A00
Sheet
1
73
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Document Number
Reserved
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
74
of
92
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
Reserved
Date: Wednesday, February 10, 2010
5
4
3
2
Rev
Berry
A00
Sheet
75
of
1
92
A
5
4
3
2
1
IO Board CONN 80 pin
IOBD1
85
86
86% (6$7$
D
21 USB_PP9
1
21 USB_PN9
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
83
82
81
NP2
::$186%
21 USB_PP11
21 USB_PN11
86%
21 USB_PN8
21 USB_PP8
:/$186%
21 USB_PP2
21 USB_PN2
37 E51_RXD
37 E51_TXD
::$13&,(
::$13&,(
::$1:/$160%86
23 PCIE_RXP4
23 PCIE_RXN4
23 PCIE_TXP4
23 PCIE_TXN4
7,18,19,23 PCH_SMBDATA
7,18,19,23 PCH_SMBCLK
+DC_IN_SS
C
37 W IFI_RF_EN
23 W W AN_CLKREQ#
37 W W AN_RADIO_DIS#
37 PSID_DISABLE#
/$13&,(
/$13&,(
NP1
84
2
X02-20091230
23 PCIE_RXP3
23 PCIE_RXN3
23 PCIE_TXP3
23 PCIE_TXN3
SATA_TXN4 24
SATA_TXP4 24
6$7$ (6$7$
6$7$ (6$7$
SATA_RXN4_C 24
SATA_RXP4_C 24
PCIE_TXP2 23
PCIE_TXN2 23
PCIE_RXP2 23
PCIE_RXN2 23
D
:/$13&,(
:/$13&,(
CLK_PCIE_W LAN 23
CLK_PCIE_W LAN# 23
:/$1&/.
CLK_PCIE_LAN 23
CLK_PCIE_LAN# 23
/$1&/.
CLK_PCIE_W W AN 23
CLK_PCIE_W W AN# 23
::$1&/.
at least 80 mil
+5V_USB1
+5V_ALW
+3.3V_RUN
C
A00-20100203
+3.3V_ALW
+1.5V_RUN
PM_LAN_ENABLE 37
PLT_RST# 9,21,37,70,78,80
W LAN_CLKREQ# 23
PCIE_W AKE# 22
BT_ACT 73
W LAN_ACT 73
PSID_EC 37
ACES-CONN80D-GP
20.F1009.080
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
IO Board Connector
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
76
of
92
5
4
CRT Board Connector
3
2
1
A00-20100120
CRTBD1
USB_PN1_C
21
USB_PN1 21
1
+5V_RUN
2
86%3257
86%3257
FILTER-130-GP
TR7701
1
CRT_R
&575*%
CRT_G
CRT_B
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON
CRT_DDCDATA_CON
D
4
USB_PN0_C
USB_PP0_C
USB_PP1_C
&57+96<1&
&5760%86
USB_PP1 21
USB_PN0_C
USB_PN0 21
3
USB_PN1_C
USB_PP1_C
2
D
+5V_USB2
3
at least 80 mil
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
TR7702
FILTER-130-GP
1
4
ACES-CON20-1-GP-U
20.F0772.020
SEC. 20.F1035.020
USB_PP0_C
CRT RGB
X01 20091111
&575*%
RN7701
CRT_RED
CRT_GREEN
CRT_BLUE
SRN0J-7-GP
CRT DDCDATA & DDCCLK level shift
CRT_B
C
C7708
SC10P50V2JN-4GP
2
1
C7707
SC10P50V2JN-4GP
2
1
1
2
2
CRT Hsync & Vsync level shift
DY
C7705
SC8P250V2CC-GP
SRN150F-1-GP
DY
C7704
SC8P250V2CC-GP
8
7
6
5
8
7
6
5
1
2
3
4
UMA
DY
RN7708
1
1
2
FCM1608CF-220T05-GP
C7703
C7706
SC10P50V2JN-4GP
2
1
CRT_BLUE
RN7702
1
2
3
4
CRT_G
L7703
SRN0J-7-GP
20 PCH_CRT_RED
20 PCH_CRT_GREEN
20 PCH_CRT_BLUE
CRT_R
1
2
FCM1608CF-220T05-GP
1
DIS
8
7
6
5
X02-20100108
L7702
CRT_GREEN
2
1
2
3
4
82 VGA_CRT_RED
82 VGA_CRT_GREEN
82 VGA_CRT_BLUE
L7701
1
2
FCM1608CF-220T05-GP
CRT_RED
Filter design on CRT Board
SC8P250V2CC-GP
Close to CRT Board CONN
C
USB_PP0 21
Close to CRT Board CONN
+3.3V_RUN
Pull High 5V Design on CRT Board
2
1
A00-20100120
+3.3V_RUN
3.3V Tolerance
80,82 VGA_CRT_HSYNC
80,82 VGA_CRT_VSYNC
CRT_HSYNC_IN
2
1
CRT_VSYNC_IN
RN7706
1
4 CRT_HSYNC_CON
2
3 CRT_VSYNC_CON
0R4P2R-PAD
DIS
3
4
Need Level Shift
RN7703
SRN0J-6-GP
1
4
2
3
RN
UMA
RN7707
SRN2K2J-1-GP
Q7701
20 PCH_CRT_DDCDATA
20 PCH_CRT_DDCCLK
4
3
5
2
UMA
1
6
CRT_DDCDATA_CON
20 PCH_CRT_HSYNC
20 PCH_CRT_VSYNC
2.5V Tolerance?
2N7002EDW-GP
5V Tolerance
UMA
3
4
RN7704
SRN33J-5-GP-U
X02-20100105
84.27002.F3F
B
B
RN7709
2
1
82 VGA_CRT_DDCDATA
82 VGA_CRT_DDCCLK
DIS
3
4
CRT_DDCCLK_CON
SRN0J-6-GP
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A2
Document Number
Date:
Monday, March 29, 2010
CRT Board Connector
Rev
A00
Berry
Sheet
1
77
of
92
5
4
3
2
1
SSID = SDIO
D
D
Card Reader connector
+3.3V_RUN
x01 20091121
C
C
CARDBD1
7
9,21,37,70,76,80 PLT_RST#
1
A00-20100120
USB_PN4_C
USB_PP4_C
8
3
2
21 USB_PN4
2
3
4
5
6
MLX-CON6-21-GP
20.F1035.006
4
1
TR7801
B
B
FILTER-130-GP
21 USB_PP4
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CARD Reader CONN
Size
A4
Document Number
http://laptop-motherboard-schematic.blogspot.com/
Date: Monday, March 29, 2010
5
4
3
Rev
Berry
2
A00
Sheet
78
of
1
92
A
5
4
H2
HTE95BE95R29-R-5-GP
H3
HTE95BE95R29-R-5-GP
H4
HTE95BE95R29-R-5-GP
H6
HTE95BE95R29-R-5-GP
H5
HOLE256R111-GP
2
H7
HTE95BE95R29-R-5-GP
H8
HTE95BE95R29-R-5-GP
1
H9
HTE95BE95R29-R-5-GP
1
1
1
1
1
1
1
1
1
H1
HTE95BE95R29-R-5-GP
3
D
D
CPU Thermal module hole
H11
HOLE256R111-GP
HTML1
HOLE197R166-GP
HTML2
HOLE197R166-GP
GPU Thermal module hole
HTML3
HOLE197R166-GP
stand off
HGPU1
STF237R117H83-1-GP
HBT1
STF237R117H123-GP
1
1
1
DY
DY
DY
1
1
1
1
H10
HOLE335R115-GP
EMI Reserve
+PW R_SRC
1
EC7916
DY
X01 stuff 20091118
DY
SCD1U25V2KX-GP
EC7911
SCD1U25V2KX-GP
2
2
DY
2
EC7906
SCD1U25V2KX-GP
2
EC7909
1
1
1
1
+PW R_SRC_1D5V
1
2
SCD1U25V2KX-GP
EC7907
SCD1U25V2KX-GP
2
SCD1U25V2KX-GP
EC7938
2
2
SCD1U25V2KX-GP
EC7943
SCD1U25V2KX-GP
DY
EC7939
2
SCD1U25V2KX-GP
EC7905
1
2
1
DY
EC7941
C
+PW R_SRC_VTT
1
EC7903
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
DY
EC7940
2
+1.05V_VTT
EMI Reserve
B
1
1
2
2
1
2
2
1
2
1
2
2
2
1
EC7936
DY
1
1
EC7929
DY
2
DY
2
2
1
1
1
2
2
1
1
1
1
1
2
1
2
1
2
1
2
1
2
2
2
2
1
1
1
2
2
2
2
1
1
1
1
EC7927
UMA
EC7944
SCD1U25V2KX-GP
DY
EC7937
SC56P50V2JN-2GP
UMA DY
X02-20100209
56pF
EC7935
SC56P50V2JN-2GP
SC56P50V2JN-2GP
DY
SC56P50V2JN-2GP
DY
EC7934
EC7926
UMA
SCD1U25V2KX-GP
EC7931 EC7932
SC56P50V2JN-2GP
DY
SC56P50V2JN-2GP
DY
EC7930
EC7945
SCD1U25V2KX-GP
EC7928
DY
+5V_RUN
56pF*2
EC7924
UMA
+1.5V_SUS
+VCC_CORE
56pF*3
EC7923
SCD1U25V2KX-GP
56pF*1
SC56P50V2JN-2GP
DY
EC7947
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
0.1uF*2
EC7933
SCD1U25V2KX-GP
0.1uF*2
A
+1.5V_SUS
+VGA_CORE
+1.5V_SUS
EC7946
DY
EC7921
SCD1U25V2KX-GP
DY
EC7925
SC56P50V2JN-2GP
DY
EC7922
SC56P50V2JN-2GP
DY
EC7920
SC56P50V2JN-2GP
DY
EC7919
SC56P50V2JN-2GP
2
EC7917
SC56P50V2JN-2GP
DY
SC56P50V2JN-2GP
DY
SC56P50V2JN-2GP
+CPU_GFX_CORE
SC56P50V2JN-2GP
DY
EC7912 EC7913
+PW R_SRC
SCD1U25V2KX-GP
EC7908
56pF*7
SCD1U25V2KX-GP
DY
+PW R_SRC
SCD1U25V2KX-GP
56pF*1
SCD1U25V2KX-GP
DY
+PW R_SRC_1D5V
1
X01 RF Reserved-20091118
SPR1
SPRING-58-GP
A00-20100204
X02-20100208
2
2
EC7904
1
1
2
SCD1U25V2KX-GP
EC7902
SCD1U25V2KX-GP
DY
EC7942
SCD1U25V2KX-GP
2
DY
1
1
1
1
1
2
SCD1U25V2KX-GP
EC7901
B
+VGFXCORE_PW R_SRC
X01 stuff 20091119
SCD1U25V2KX-GP
C
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
UNUSED PARTS/EMI Capacitors
Document Number
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
79
of
92
5
4
8 PEG_TXP[0..15]
3
PEG_RXP[0..15] 8
1 OF 8
VGA1A
8 PEG_TXN[0..15]
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
x01 change tolerant 20091117
PEG_TXP1
PEG_TXN1
D
PEG_TXP2
PEG_TXN2
W38
V37
PCIE_TX0P
PCIE_TX0N
Y33
Y32
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33 PEG_C_RXP1
W32 PEG_C_RXN1
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33 PEG_C_RXP2
U32 PEG_C_RXN2
C8001
C8002
C8003
C8004
C8005
C8006
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP0
2 SCD1U10V2KX-5GP PEG_RXN0
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP1
2 SCD1U10V2KX-5GP PEG_RXN1
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP2
2 SCD1U10V2KX-5GP PEG_RXN2
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30 PEG_C_RXP3
U29 PEG_C_RXN3
C8008
C8007
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP3
2 SCD1U10V2KX-5GP PEG_RXN3
PEG_TXP4
PEG_TXN4
U38
T37
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
T33
T32
PEG_C_RXP4
PEG_C_RXN4
C8009
C8010
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP4
2 SCD1U10V2KX-5GP PEG_RXN4
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
T30
T29
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP5
2 SCD1U10V2KX-5GP PEG_RXN5
PCIE_TX6P
PCIE_TX6N
P33 PEG_C_RXP6
P32 PEG_C_RXN6
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP6
2 SCD1U10V2KX-5GP PEG_RXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
T35
R36
R38
P37
P35
N36
N38
M37
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PEG_TXP9
PEG_TXN9
M35
L36
PCIE_RX9P
PCIE_RX9N
PEG_TXP10
PEG_TXN10
L38
K37
PCIE_RX10P
PCIE_RX10N
PEG_TXP11
PEG_TXN11
K35
J36
PCIE_RX11P
PCIE_RX11N
PEG_TXP12
PEG_TXN12
J38
H37
PCIE_RX12P
PCIE_RX12N
PEG_TXP13
PEG_TXN13
H35
G36
PEG_TXP14
PEG_TXN14
G38
F37
PEG_TXP15
PEG_TXN15
F35
E37
PCIE_RX13P
PCIE_RX13N
PCI EXPRESS INTERFACE
V35
U36
PEG_TXP6
PEG_TXN6
B
Y35
W36
PCIE_RX0P
PCIE_RX0N
PEG_TXP3
PEG_TXN3
PEG_TXP5
PEG_TXN5
C
AA38
Y37
PEG_C_RXP0
PEG_C_RXN0
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_TX7P
PCIE_TX7N
PEG_C_RXP5
PEG_C_RXN5
P30 PEG_C_RXP7
P29 PEG_C_RXN7
C8011
C8012
C8013
C8014
C8016
C8015
1
DIS
1
DIS
N33 PEG_C_RXP8
N32 PEG_C_RXN8
PCIE_TX9P
PCIE_TX9N
N30 PEG_C_RXP9
N29 PEG_C_RXN9
C8018
C8017
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP8
2 SCD1U10V2KX-5GP PEG_RXN8
C8020
C8019
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP9
2 SCD1U10V2KX-5GP PEG_RXN9
PCIE_TX10P
PCIE_TX10N
L33
L32
PEG_C_RXP10 C8021
PEG_C_RXN10 C8022
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP10
2 SCD1U10V2KX-5GP PEG_RXN10
PCIE_TX11P
PCIE_TX11N
L30
L29
PEG_C_RXP11 C8023
PEG_C_RXN11 C8024
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP11
2 SCD1U10V2KX-5GP PEG_RXN11
PCIE_TX12P
PCIE_TX12N
K33 PEG_C_RXP12 C8025
K32 PEG_C_RXN12 C8026
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP12
2 SCD1U10V2KX-5GP PEG_RXN12
PCIE_TX13P
PCIE_TX13N
J33
J32
PEG_C_RXP13 C8028
PEG_C_RXN13 C8027
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP13
2 SCD1U10V2KX-5GP PEG_RXN13
PCIE_TX14P
PCIE_TX14N
K30 PEG_C_RXP14 C8030
K29 PEG_C_RXN14 C8029
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PEG_RXP14
2 SCD1U10V2KX-5GP PEG_RXN14
PCIE_TX15P
PCIE_TX15N
H33 PEG_C_RXP15 C8032
H32 PEG_C_RXN15 C8031
PARK
37,70,76,78
PLT_RST#
2
1 R8020
0R2J-2-GP DY
CALIBRATION
PW RGOOD
10KR2F-2-GP
AJ21
AK21
AH16
2VGA_RST# AA30
NC#AJ21
NC#AK21
PWRGOOD
37 PLTRST_DELAY#
TX_DEEMPH_EN
GPIO1
X
1
BIF_GEN2_EN_A
GPIO2
0:Advertises the PCIe device as 2.5GT/s capable at power on.
1:Advertises the PCIe device as 5.0GT/s capable at power on.
0
0
GPIO5_AC_BATT
GPIO5
optional input allow the system to request a fast
power reduction by setting GPIO5 to low.
?
0
RESERVED
GPIO8
RESERVED
0
0
GPIO9
ROMIDCFG[2:0]
GPIO[13:11]
RESERVED
GPIO21
PCIE_CALRP
PCIE_CALRN
V2SYNC
0:VGA Controller capacity enabled
1:The device won't be recognized as the system's VGA controller
BIOS_ROM_EN=1, Config[2:0] defines the ROM type
BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size
R8017
1
2
1K27R2F-L-GP
PCIE_CALRN
Y29
1
R8019
Y30 PCIE_CALRP
2 SCD1U10V2KX-5GP PEG_RXP15
2 SCD1U10V2KX-5GP PEG_RXN15
DIS
0
X
X
X
0
X
VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is connected on the VIP Host interface.
D
0
0 0 1
(256MB)
0
RESERVED
0:Disable external BIOS ROM device
1:Enable external BIOS ROM device
0
X
0
RSVD
H2SYNC
RESERVED
0
0
RSVD
GENERICC
RESERVED
0
0
AUD[1]
HSYNC
X
1
AUD[0]
VSYNC
X
1
AUD[1:0]:11-Audio for both DisplayPort and HDMI
+3.3V_RUN_VGA
PIN STRAPS
DIS
1
C
R8001
1
82 TX_DEEMPH_EN
R8002
1
82 BIF_GEN2_EN_A
R8003
1
R8004
1
82 VGA_DIS
R8005
1
82 CONFIG0
R8006
1
82 CONFIG1
R8007
1
82 CONFIG2
R8008
1
R8009
1
R8010
1
R8012
1
R8013
1
82 BIOS_ROM_EN
R8014
1
82 GPIO5_AC_BATT
R8015
1
R8016
1
82 GPIO8_ROMSO
+1.0V_RUN_VGA
77,82 VGA_CRT_VSYNC
2
2KR2F-3-GP
77,82 VGA_CRT_HSYNC
PERST#
82 VSYNC_DAC2
MADISON-PRO-2-GP
R8021
1
2
0R0402-PAD
X
BIOS_ROM_EN GPIO_22_ROMCSB
PCIE_REFCLKP
PCIE_REFCLKN
X02-20091208
PLATFORM
SETTING
PCIE TRANSMITTER DE-EMPHASIS ENABLED
0:Tx de-emphasis disabled 1:Tx de-emphasis enabled
82 TX_PW RS_ENB
1
DIS
1
DIS
RECOMMEND
DESCRIPTION OF DEFAULT SETTINGS
GPIO0
VGA_DIS
2 SCD1U10V2KX-5GP PEG_RXP7
2 SCD1U10V2KX-5GP PEG_RXN7
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
Transmitter Power Savings Enable
0: 50% Tx output swing 1: Full Tx output swing
TX_PWRS_ENB
CLOCK
AB35
AA36
23 CLK_PCIE_VGA
23 CLK_PCIE_VGA#
PIN
STRAPS
VIP_DEVICE_STRAP_EN
PCIE_TX8P
PCIE_TX8N
1
CONFIGURATION STRAPS
PEG_RXN[0..15] 8
PEG_TXP0
PEG_TXN0
1
R8018
2
82 HSYNC_DAC2
DIS
82 GPIO21_BB_EN
DY
DY
DY
DY
DY
DIS
DY
DY
DIS
DIS
DY
DY
DY
DY
DY
2
3KR2J-2-GP
2
3KR2J-2-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
B
X02-20091224
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
A3
Date:
GPU_PCIE/STRAPPING(1/5)
Document Number
Rev
A00
Berry
Monday, March 29, 2010
Sheet
1
80
of
92
CKEA0
CKEA1
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
WEA0#
WEA1#
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
MAA0_8
MAA1_8
QSAN_0
QSAN_1
QSAN_2
QSAN_3
QSAN_4
QSAN_5
QSAN_6
QSAN_7
85
85
85
85
86
86
86
86
J21
G19
88 MDB[32..63]
ODTA0 85
ODTA1 86
H27
G27
CLKA0 85
CLKA0# 85
J14
H14
CLKA1 86
CLKA1# 86
K23
K19
RASA0# 85
RASA1# 86
K20
K17
CASA0# 85
CASA1# 86
K24
K27
CSA0#_0
85
M13
K16
CSA1#_0
86
X01-20091116
+3.3V_RUN_VGA
K21
J20
CKEA0 85
CKEA1 86
K26
L15
WEA0# 85
WEA1# 86
H23
J19
DIS
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0#
CLKB1
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
CSB0#_0
CSB0#_1
CSB1#_0
CSB1#_1
CKEB0
CKEB1
MVREFDB
MVREFSB
TESTEN
CLKTESTA
CLKTESTB
MAB0_8
MAB1_8
DRAM_RST#
MAB0 87,88
MAB1 87,88
MAB2 87,88
MAB3 87,88
MAB4 87,88
MAB5 87,88
MAB6 87,88
MAB7 87,88
MAB8 87,88
MAB9 87,88
MAB10 87,88
MAB11 87,88
MAB12 87,88
B_BA2 87,88
B_BA0 87,88
B_BA1 87,88
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSBP_0
QSBP_1
QSBP_2
QSBP_3
QSBP_4
QSBP_5
QSBP_6
QSBP_7
87
87
87
87
88
88
88
88
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSBN_0
QSBN_1
QSBN_2
QSBN_3
QSBN_4
QSBN_5
QSBN_6
QSBN_7
87
87
87
87
88
88
88
88
T7
W7
ODTB0 87
ODTB1 88
L9
L8
CLKB1 88
CLKB1# 88
T10
Y10
RASB0# 87
RASB1# 88
W10
AA10
CASB0# 87
CASB1# 88
P10
L10
CSB0#_0
87
AD10
AC10
CSB1#_0
88
U10
AA11
CKEB0 87
CKEB1 88
N10
AB11
T8
W8
R8103
Rb
A
2
51R2J-2-GP
R8102
2K2R2J-2-GP
MEM_RST 85,86,87,88
R_MEM_1
C8103
SC68P50V2JN-1GP
R8105
DIS10KR2J-3-GP
2
X01-20091118
B
DIS
R8119
100R2F-L1-GP-U
C8106
SCD1U10V2KX-5GP
DIS
R8116
40D2R2F-GP
DIS
Designator
Rb
For Mannhatton For M96-M2/M92-M2
MVREFSB
DIS
R8120
100R2F-L1-GP-U
R_MEM_1
10K
2.2nF
R_MEM_2
51R
0R/Short
R_MEM_3
DNI
DNI
C_MEM
68pF
10K
C8107
SCD1U10V2KX-5GP
DIS
x01 Change tolerant 20091117
DDR3/GDDR3 Memory Stuff Option(Mad/Park)
DIS
DIS
1
Ra
MVREFDB
1
C8105
SCD1U10V2KX-5GP
2
2
M96
R8118
100R2F-L1-GP-U
R8115
40D2R2F-GP
DIS
2
2
Rb
M96
1
2
2
C8104
SCD1U10V2KX-5GP
1
M96
R8117
100R2F-L1-GP-U
M96
MVREFSA
1
1
1
MVREFDA
R_MEM_2
DRAM_RST
basic topology should be used for DRAM_RST for
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
1
Ra
1
R8114
40D2R2F-GP
M96
2
Ra
R_MEM_3
DY
MAB13 87,88
** This
+1.5V_RUN
2
R8113
40D2R2F-GP
2
Ra
M96
Rb
+1.5V_RUN
1
+1.5V_RUN
1
+1.5V_RUN
+1.5V_RUN
WEB0# 87
WEB1# 88
DIS
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
2MEM_CALRP2
C
CLKB0 87
CLKB0# 87
AD8
AD7
AH11
87
87
87
87
88
88
88
88
2
MADISON-PRO-2-GP
M96
D
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
C_MEM
20100210
2MEM_CALRP0
2
DY
R8112 1
243R2F-2-GP
2MEM_CALRP1
1
DY
3
4
DIS
R8111 1
243R2F-2-GP
AD28
CLKTESTA AK10
CLKTESTBAL10
MADISON-PRO-2-GP
B
R8110 1
243R2F-2-GP
DDBIB0_0/QSB_0#/WDQSB_0
DDBIB0_1/QSB_1#/WDQSB_1
DDBIB0_2/QSB_2#/WDQSB_2
DDBIB0_3/QSB_3#/WDQSB_3
DDBIB1_0/QSB_4#/WDQSB_4
DDBIB1_1/QSB_5#/WDQSB_5
DDBIB1_2/QSB_6#/WDQSB_6
DDBIB1_3/QSB_7#/WDQSB_7
WEB0#
WEB1#
RN8101
SRN4K7J-8-GP
2 MEM_CALRN2
R8107
DIS
Y12
AA12
TEST_EN
MAA13 85,86
R8122
10KR2J-3-GP
MVREFDB
MVREFSB
R8121
10KR2J-3-GP
DY
1
MVREFDA
MVREFSA
A34
E30
E26
C20
C16
C12
J11
F8
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
1
CSA1#_0
CSA1#_1
85
85
85
85
86
86
86
86
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0#_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0#_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1#_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1#_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7
1
MEM_CALRN1
R8106
CSA0#_0
CSA0#_1
QSAP_0
QSAP_1
QSAP_2
QSAP_3
QSAP_4
QSAP_5
QSAP_6
QSAP_7
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
2
2
CASA0#
CASA1#
C34
D29
D25
E20
E16
E12
J10
D7
85
85
85
85
86
86
86
86
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
2
DY
1
243R2F-2-GP
MEM_CALRN0
R8104
M12
M27
AH12
CLKA1
CLKA1#
RASA0#
RASA1#
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
2
1
PARK
1
243R2F-2-GP
2
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
CLKA0
CLKA0#
A32
C32
D23
E22
C14
A14
E10
D9
2
DY
1
243R2F-2-GP
L27
N12
AG12
ADBIA0/ODTA0
ADBIA1/ODTA1
MAA0 85,86
MAA1 85,86
MAA2 85,86
MAA3 85,86
MAA4 85,86
MAA5 85,86
MAA6 85,86
MAA7 85,86
MAA8 85,86
MAA9 85,86
MAA10 85,86
MAA11 85,86
MAA12 85,86
A_BA2 85,86
A_BA0 85,86
A_BA1 85,86
1
X02-20091208
+1.5V_RUN
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
DDBIA0_0/QSA_0#/WDQSA_0
DDBIA0_1/QSA_1#/WDQSA_1
DDBIA0_2/QSA_2#/WDQSA_2
DDBIA0_3/QSA_3#/WDQSA_3
DDBIA1_0/QSA_4#/WDQSA_4
DDBIA1_1/QSA_5#/WDQSA_5
DDBIA1_2/QSA_6#/WDQSA_6
DDBIA1_3/QSA_7#/WDQSA_7
GDDR5
C
WCKA0_0/DQMA_0
WCKA0#_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0#_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1#_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1#_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
2
L18
L20
86 MDA[32..63]
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
1
MVREFDA
MVREFSA
D
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
1
4 OF 8
DDR2
GDDR5/GDDR3
DDR3
VGA1D
DDR2
GDDR3/GDDR5
DDR3
87 MDB[0..31]
2
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MEMORY INTERFACE A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
2
GDDR5
3 OF 8
DDR2
GDDR5/GDDR3
DDR3
VGA1C
DDR2
GDDR3/GDDR5
DDR3
85 MDA[0..31]
3
1
4
MEMORY INTERFACE B
5
DDR3/GDDR3 Memory Stuff Option(M92/M96)
GDDR5
GDDR3
DDR3
MVDDQ
1.5V
1.8V/1.5V
1.5V
MVDDQ
GDDR3
DDR3
1.8V/1.5V
Ra
40.2R
40.2R
40.2R
1.5V
Ra
40.2R
100R
Rb
100R
100R
100R
Rb
100R
100R
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
C
Date:
GPU Memory(2/5)
Document Number
Rev
A00
Berry
Sheet
Monday, March 29, 2010
1
81
of
92
4
3
2
MEMORY ID Table
LVDS Interface
Description
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
MUTI GFX
DPA
TX0P_DPC2P
TX0M_DPC2N
DPC
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
2
1
2
80 CONFIG0
80 CONFIG1
80 CONFIG2
1
10KR2J-3-GP
JTAG_TMS_VGA
80 GPIO21_BB_EN
80 BIOS_ROM_EN
JTAG SIGNAL OPTION
7 CLK_VGA_27M_SS
Debug
mode
pilot run
mode
TESTEN
"1"(PU) "1"(PU)
JTAG_TRST# "0"(PD) "1"(PU)
JTAG_TCK
JTAG_TMS
CLK
NC
"1"(PU)
+1.8V_RUN_VGA
NC
"1"(PU) "1"(PU)
B
For new version no 27M
"0"(PD)
NC
PLACE VREFG DIVIDER AND CAP
CLOSE TO ASIC
+1.8V_RUN_VGA
GPU_VREFG
R8217
249R2F-GP
2
DIS DIS
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2
R2#
G2
G2#
B2
B2#
H2SYNC
V2SYNC
HPD1
AN31
XTALIN
AV33
XTALOUT AU34
1
2
DIS
AW34
AW35
DY
39 VGA_THERMDC
TP8214
C8226
SC470P50V2JN-GP
AF29
AG29
1 TPAD14-GP
XTALIN
FAN_PWM
AK32
TSVDD
DPLL_VDDC
XTALIN
XTALOUT
PLL/CLOCK
DIS
1
C8224
SC1U6D3V2KX-GP
DIS
C8225
SCD1U10V2KX-5GP
DDC1CLK
DDC1DATA
AUX1P
AUX1N
DDC2CLK
DDC2DATA
XO_IN
AUX2P
AUX2N
XO_IN2
DDCCLK_AUX3P
DDCDATA_AUX3N
DPLUS
DMINUS
THERMAL
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
DDC6CLK
DDC6DATA
TS_A
DDCCLK_AUX7P
DDCDATA_AUX7N
TSVDD
TSVSS
MADISON-PRO-2-GP
2
DY
1
AJ32
AJ33
2
C8223
SC4D7U6D3V3KX-GP
R2SET
([email protected] TSVDD)
1
2
+1.8V_RUN_VGA
L8204 DIS
1
2
BLM15BD121SS1D-GP
2
1
AL31
R8213
150R2F-1-GP
AT21
AR20
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AU22
AV21
AT23
AR22
A
TXOUT_L3P
TXOUT_L3N
DIS
AD39
AD37
VGA_CRT_RED
AE36
AD35
VGA_CRT_GREEN
AF37
AE38
VGA_CRT_BLUE
GPU_LVDSA_TX0 55
GPU_LVDSA_TX0# 55
AR37
AU39
GPU_LVDSA_TX1 55
GPU_LVDSA_TX1# 55
AP35
AR35
GPU_LVDSA_TX2 55
GPU_LVDSA_TX2# 55
AN36
AP37
77
+1.8V_RUN_VGA
77
([email protected] AVDD)
L8202 DIS
1
2
BLM15BD121SS1D-GP
77
RN8204
AB34
VGA_CRT_HSYNC
VGA_CRT_VSYNC
GPU_RSET
AVDD
AD34
AE34
1
R8214
VGA_CRT_BLUE
1
VGA_CRT_GREEN 2
VGA_CRT_RED
3
4
77,80
77,80
DIS
2
499R2F-2-GP
C8201
SC4D7U6D3V3KX-GP
8
7
6
5
DIS
DIS
SRN150F-1-GP
L8203 DIS
1
2
BLM15BD121SS1D-GP
VDD1DI
AC33
AC34
X02-20091222
AVSSQ
C8202
SC4D7U6D3V3KX-GP
1
C
C8204
DISSC1U6D3V2KX-GP
AVSSQ
VDD1DI
x01 Change tolerant 20091117
DIS
2
0R0402-PAD
AD30
AD31
C8203
DIS
([email protected] VDD1DI)
R8206
AC30
AC31
AVDD
x01 Change tolerant 20091117
1
+3.3V tolerant
AC36
AC38
C8206
C8207
SCD1U10V2KX-5GP
DIS
DIS
AVSSQ
([email protected] VDD2DI)
AF30
AF31
x01 Change tolerant 20091117
DY
DY
AC32
AD32
AF32
SCD1U10V2KX-5GP
AD29
AC29
HSYNC_DAC2
VSYNC_DAC2
80
80
+3.3V_RUN_VGA
AD33
AF33
AA29
SC1U6D3V2KX-GP
A2VDDQ)
DIS
SCD1U10V2KX-5GP
A2VDDQ
AG33
C8210
A2VDDQ
L8205 DIS
([email protected]
1
2
BLM15BD121SS1D-GP
C8212
+1.8V_RUN_VGA
AG31
AG32
DPLL_PVDD
DPLL_PVSS
39 VGA_THERMDA
2
1
SC1U6D3V2KX-GP
2
1
2
DIS
XO_IN
1PARK 2
R8210
0R2J-2-GP
1 M96 2
R8211
0R2J-2-GP
7 CLK_VGA_27M_NSS
SCD1U10V2KX-5GP
DY
C8222
VREFG
DDC/AUX
X02 20091208
C8221
A2VDDQ
A2VSSQ
AM32
AN32
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
GPU_LVDSA_TXC 55
GPU_LVDSA_TXC# 55
AW37
AU35
C8209
C
Y
COMP
DPLL_PVDD
x01 Change tolerant 20091117
2
BLM18PG471SN1D-GP
C8220
SC4D7U6D3V3KX-GP
M96
AH13
DPLL_VDDC
([email protected] DPLL_VDDC)
([email protected] DPLL_VDDC For M96/M92)
DIS
X02-20091210
Voltage Swing:1.8V
1
1
1
DIS
DIS
C8217
2
2
+1.0V_RUN_VGA
C8218
2
SC1U6D3V2KX-GP
2
1
1
C8219
DY
SCD1U10V2KX-5GP
C8205
SC4D7U6D3V3KX-GP
2
124R2F-U-GP
HSYNC
VSYNC
A2VDD
SCD1U10V2KX-5GP
L8201
1
2
BLM18PG471SN1D-GP
CLK_VGA_27M_NSS 1
R8212
B
B#
R8216
499R2F-2-GP
DIS
DPLL_PVDD
DIS
M96
G
G#
VDD2DI
VSS2DI
([email protected] DPLL_PVDD)
1
L8207
AK24
57 HDMI_HPD_DET
1
Normal
mode
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
DAC1
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCS#
GPIO_23_CLKREQ#
JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DAC2
GENERICF
GENERICG
1
Signal
2
DY
AU20
AT19
AP34
AR34
2
80 GPIO8_ROMSO
80 VGA_DIS
R8205
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
1
+3.3V_RUN_VGA
VGA_BLEN
210KR2J-3-GP
2
1
80 GPIO5_AC_BATT
DIS
1
AH20
AH18
AN16
AH23
AJ23
AH17
GPIO6_VGA
1
AJ17
TP8207
TPAD14-GP
AK17
55 VGA_BLEN
AJ13
AH15
AJ16
AK16
AL16
AM16
VPIO14_VGA
1
AM14
TP8208
TPAD14-GP
AM13
89 PWRCNTL_0
GPIO16_SSIN
TPAD14-GP
1
AK14
GPIO17_VGA
TP8203
TPAD14-GP
1
AG30
GPIO18_VGA
TP8213
TPAD14-GP
1
AN14
THERMTRIP_VGA
TP8209
AM17
AL13
89 PWRCNTL_1
AJ14
AK13
AN13
23 PEG_CLKREQ#
JTAG_TRST#_VGA
AM23
JTAG_TDI_VGA
R8204
TP8202
TPAD14-GP
1
AN23
JTAG_TCK_VGA
1 DY
2
AK23
JTAG_TMS_VGA
AL24
JTAG_TDO_VGA AM24
TP8205
0R2J-2-GP
1 TPAD14-GP
GEN_A
1 TPAD14-GP
AJ19
X01-20091116 TP8206
GEN_B
TP8211
1 TPAD14-GP
AK19
GENERICC
TP8218
1 TPAD14-GP
AJ20
GENERICD
TP8219
1 TPAD14-GP
AK20
GENERICE_HPD4
TP8212
1 TPAD14-GP
AJ24
GENERICF
TP8220
1 TPAD14-GP
AH26
GENERICG
TP8221
1 TPAD14-GP
AH24
80 TX_PWRS_ENB
80 TX_DEEMPH_EN
80 BIF_GEN2_EN_A
R8202
1
MADISON-PRO-2-GP
R
R#
GENERAL PURPOSE I/O
C
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AT17
AR16
SCL
SDA
SRN0J-6-GP
10KR2J-3-GP
LVTMDP
AU16
AV15
2
1
Straps
AT15
AR14
GPU_LVDSB_TX2 55
GPU_LVDSB_TX2# 55
AF35
AG36
1
R8203
DY
1 GPU_LVDS_CLK_C AK26
2 GPU_LVDS_DATA_C AJ26
DIS
TXOUT_U3P
TXOUT_U3N
C8213
DIS
B
x01 Change tolerant 20091117
R2SET
1
R8218
DIS
+3.3V_RUN_VGA
([email protected] A2VDD)
2
715R2F-GP
1
10KR2J-3-GP
TX5P_DPD0P
TX5M_DPD0N
RN8202
4
3
20,54 GPU_LVDS_CLK
20,54 GPU_LVDS_DATA
AU14
AV13
GPU_LVDSB_TX1 55
GPU_LVDSB_TX1# 55
AG38
AH37
D
2
2
I2C Bus for LVDS
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
GPU_LVDSB_TX0 55
GPU_LVDSB_TX0# 55
AH35
AJ36
AM26
AN26
VGA_CRT_DDCCLK 77
VGA_CRT_DDCDATA 77
DDC1 channel for CRT
AM27
AL27
AM19
AL19
GPU_HDMI_CLK 57
GPU_HDMI_DATA 57
C8215
DY
1
JTAG_TCK_VGA
DY
TX4P_DPD1P
TX4M_DPD1N
I2C
3
4
2
R8201
DPD
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AT33
AU32
GPU_LVDSB_TXC 55
GPU_LVDSB_TXC# 55
AJ38
AK37
DY
C8216
SCD1U10V2KX-5GP
2
DIS
X01-20091116
TX3P_DPD2P
TX3M_DPD2N
RN8201
SRN4K7J-8-GP
AR32
AT31
AK35
AL36
1
JTAG_TRST#_VGA
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
VGA_LBKLT_CTL 55
VGA_LCDVDD_EN 55
2
37 THERMTRIP_VGA_GATE
TXCCP_DPC3P
TXCCM_DPC3N
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AV31
AU30
AK27
AJ27
SC1U6D3V2KX-GP
X02-20100104
H_THERMTRIP#
TX5P_DPB0P
TX5M_DPB0N
AR30
AT29
VARY_BL
DIGON
SCD1U10V2KX-5GP
S
84.2N702.D31
TX4P_DPB1P
TX4M_DPB1N
LVDS CONTROL
1
D
2
3
2
1
.
.
. .
G
9,25,37,42
Q8202
2N7002E-1-GP
.
DY
DY
DPB
HDMI_PCH_DATA2 20,57
HDMI_PCH_DATA2# 20,57
2
1
4
5
6
10KR2J-3-GP
2N7002EDW-GP
Q8203
84.27002.F3F
THERMTRIP_VGA#
DY R8208
X02-20100104
TX3P_DPB2P
TX3M_DPB2N
HDMI_PCH_DATA1 20,57
HDMI_PCH_DATA1# 20,57
AT27
AR26
SC1U6D3V2KX-GP
THERMTRIP_R
THERMTRIP_VGA
TXCBP_DPB3P
TXCBM_DPB3N
AU26
AV25
1
Hynix
TX2P_DPA0P
TX2M_DPA0N
2
64M*16
DVPDATA[0:3] Default:Pull down
D
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
2
DDR3 SAMSUNG-K4W1G1646E-HC12 (800MHz)
AR8
AU8
AP8
AW8
+1.8V_RUN_VGA
AR3
AR1
MEM_ID0
R8207 1
2 10KR2J-3-GP
AU1
MEM_ID1
R8209 1
2 10KR2J-3-GP
AU3
MEM_ID2 AW3
1
VRAM_1G
TP8222
TPAD14-GP MEM_ID3
1
AP6
TP8223 TPAD14-GP
AW5
AU5
AR6
AW6
37
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
+3.3V_RUN_VGA
AW12
AU12
AP12
1
0000
TX1P_DPA1P
TX1M_DPA1N
MEM_ID Control
X02-20091222
4
3
DIS
SRN10KJ-5-GP
SC1U6D3V2KX-GP
DDR3 SAMSUNG K4W2G1646B-HC12 (800MHz) 128M*16
HDMI_PCH_DATA0 20,57
HDMI_PCH_DATA0# 20,57
7 OF 8
VGA1G
1
DDR3 Hynix-H5TQ2G63BFR-12C (800MHz) 128M*16
0010
1
2
AT25
AR24
2
0011
RN8203
HDMI_PCH_CLK 20,57
HDMI_PCH_CLK# 20,57
1
DDR3 Hynix-H5TQ1G63BFR-12C (800MHz) 64M*16
AU24
AV23
2
DVPDATA[0:3]
0001
1
2 OF 8
VGA1B
2
5
DDC2 channel for HDMI
AN20
AM20
DDC1/DDC2/DDC6 have 5V-tolerant
AL30
AM30
AL29
AM29
AN21
AM21
X8201
AJ30
AJ31
C8227
2
AK30
AK29
1
XTALIN
1
4
DY
SC18P50V2JN-1-GP
2
DIS
DY
C8228
3
XTALOUT
1
2
SC18P50V2JN-1-GP
XTAL-27MHZ-85-GP
DY
A
x01 Change tolerant 20091117
<Core Design>
Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or
b) 27MHz (1.8V) oscillator connected to XTALIN or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A2
Document Number
Date:
Monday, March 29, 2010
Rev
A00
Berry
Sheet
1
82
of
92
4
3
PCIE
NC_VDDRHB
NC_VSSRHB
PCIE_PVDD
PLL
M96
VOLTAGE
SENESE
AF28
TP8301
1FB_VDDC
TPAD14-GP
1FB_VDDCI
TPAD14-GP
AG28
TP8302
M96
1
R8304
FB_VDDC
FB_VDDCI
2 FB_GND AH29
0R2J-2-GP
ISOLATED
CORE I/O
FB_GND
MADISON-PRO-2-GP
SPV18
SC1U6D3V2KX-GP
2
2
PARK
1
C8390
C8391
PARK
(Park: [email protected] MPV18)
SC4D7U6D3V3KX-GP
PARK
1
1
2
2
1
2
1
1
2
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
DIS
1
C8365
2
1
C8364
2
1
DIS
2
1
2
1
1
2
1
2
1
2
2
1
2
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
C8363
COLAY
1
1
C8373
2
DIS
2
1
2
C8372
DY
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
+VGA_CORE
DIS
1
C8386
C8387
SC1U6D3V2KX-GP
DIS
2
DIS
1
C8385
2
DIS
1
C8384
2
DIS
1
C8383
2
DIS
1
1
C8382
X02-20091224
DIS
C8388
A00 change 22uF 20100329
B
DIS
NOTE4:
For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
1
C8393
DIS
C8396
PARK
2
PARK
2
A
SC1U6D3V2KX-GP
2
1
1
C8392
SCD1U10V2KX-5GP
BLM18PG471SN1D-GP
C8362
NOTE3:
M97 VDDC and VDDCI ball assignments are different from M96.
If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
MPV18
PARK 2
DIS
NOTE2:
FB_VDDC, FB_VDDCI and FB_GND are not support on M96
(M97, Broadway and Madison: [email protected] MPV18)
1
L8305
C8361
2
1
1
PARK
SCD1U10V2KX-5GP
C8389
SC4D7U6D3V3KX-GP
R8301
0R3J-0-U-GP
UMA
NOTE1:
Back Bias is not supported on M97, Broadway, Madison and Park
For the M96 Back Bias circuitry, refer to REF134
([email protected] SPV18)
BLM15BD121SS1D-GP
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
2
SPVSS
M97, Broadway, Madison and Park only
PARK 2
DY
SC22U6D3V5MX-2GP
2
AN10
DIS
VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair
1
L8304
DIS
SC1U6D3V2KX-GP
C8381
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
SC1U6D3V2KX-GP
X02-20091208
SPV10
C8345
SC1U6D3V2KX-GP
DIS
(GDDR3/DDR3 [email protected] VDDCI)
SC1U6D3V2KX-GP
x01 change tolerant 20091117
B
C8371
DIS
SC1U6D3V2KX-GP
DIS
AN9
DIS
x01 change tolerant 20091117
C8360
A00 change 22uF 20100329
SCD1U10V2KX-5GP
C8380
DIS
M97, Broadway, Madison and Park only
M96 do not support core vsense feature
SPV18
SPV10)
SCD1U10V2KX-5GP
C8379
SC4D7U6D3V3KX-GP
DIS
C8359
(GDDR5 [email protected] VDDCI)
AM10
PARK
(For M96 SPV10 = VDDC)
(For M97, Broadway, Madison and Park SPV10 = 1.0V)
MPV18
MPV18
SPV18
1
1
DIS
PCIE_PVDD
H7
H8
2
DIS
AB37
MPV18
+VGA_CORE
SPV10
L8307
1
2
BLM18PG471SN1D-GP
+1.0V_RUN_VGA
L8303
(120mA
1
2
BLM18PG471SN1D-GP
SC1U6D3V2KX-GP
2
1
2
DIS
X02-20091208
C8378
1
C8376
SC4D7U6D3V3KX-GP
C8377
2
1
2
BLM15BD121SS1D-GP
SCD1U10V2KX-5GP
DIS
SC1U6D3V2KX-GP
2
1
([email protected] PCIE_PVDD)
1
L8302
C8344
x01 change tolerant 20091117
1
2
NC_VDDRHA
NC_VSSRHA
V12
U12
DIS
2
1
SC1U6D3V2KX-GP
2VSSRHB
0R2J-2-GP
1
R8303
M20
M21
1
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1
1
SC4D7U6D3V3KX-GP
2
SC1U6D3V2KX-GP
2
1
1
2
x01 change tolerant 20091117
M96
DIS
2
1
SC4D7U6D3V3KX-GP
1
2
1
2
VDDRH
1 M96
2VSSRHA
R8302
0R2J-2-GP
C8343
C
C8370
2
SC1U6D3V2KX-GP
2
1
1
1
2
1
2
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
2
1
1
2
1
2
1
2
1
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
1
2
1
SC10U6D3V5KX-1GP
2
SC10U6D3V5KX-1GP
2
C8394
M96
DIS
SC1U6D3V2KX-GP
2
BLM15BD121SS1D-GP
C8350
C8342
SCD1U10V2KX-5GP
M96
1
L8306
120ohm, 0.3A
DIS
SC1U6D3V2KX-GP
+1.5V_RUN
DIS
DIS
For UMA +VGA_CORE connect to GND
SC22U6D3V5MX-2GP
C8375
D
DIS DIS SC1U6D3V2KX-GP
C8358
SC10U6D3V5KX-1GP
X02-20091208
DIS
C8357
SC22U6D3V5MX-2GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
C8374
DIS
VDDR4
VDDR4
VDDR4
VDDR4
C8349
C8341
x01 change tolerant 20091117
C8356
SC22U6D3V5MX-2GP
AD12
AF11
AF12
AG11
C8334
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
VDDR4
VDDR4
VDDR4
VDDR4
DIS
SC1U6D3V2KX-GP
AF13
AF15
AG13
AG15
DIS
DIS
SC1U6D3V2KX-GP
C8369
DY
C8340
SC1U6D3V2KX-GP
VDDR3
VDDR3
VDDR3
VDDR3
C8348
SCD1U10V2KX-5GP
I/O
AF23
AF24
AG23
AG24
C8302
DIS
SC1U6D3V2KX-GP
VDD_CT
VDD_CT
VDD_CT
VDD_CT
C8333
DIS
SC1U6D3V2KX-GP
DIS
DIS
DIS
SC1U6D3V2KX-GP
AF26
AF27
AG26
AG27
C8355
C8332
DIS
+VGA_CORE
C8339
SC1U6D3V2KX-GP
DIS
DIS
C8331
DIS
SC1U6D3V2KX-GP
C8368
C8354
SC1U6D3V2KX-GP
DIS
DIS
C8347
SC1U6D3V2KX-GP
DIS
C8367
DIS
C8353
SC1U6D3V2KX-GP
C
C8366
C8352
SC1U6D3V2KX-GP
+3.3V_RUN_VGA
C8351
DIS
DIS
DIS
SC1U6D3V2KX-GP
2
BLM15BD121SS1D-GP
POWER
DIS
SCD1U10V2KX-5GP
1
L8301
C8346
C8337
SCD1U10V2KX-5GP
LEVEL
TRANSLATION
VDDC_CT
DIS
SC1U6D3V2KX-GP
x01 change tolerant 20091117
([email protected] VDD_CT)
C8336
SC1U6D3V2KX-GP
+1.8V_RUN_VGA
+1.0V_RUN_VGA
([email protected] PCIE_VDDC)
SC1U6D3V2KX-GP
DIS
C8317
SC4D7U6D3V3KX-GP
DIS
X02-20091224
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
SC1U6D3V2KX-GP
DIS
VDDC
CORE
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
C8330
DIS
C8316
DIS
SC1U6D3V2KX-GP
C8335
C8329
DIS
C8315
DY
SC1U6D3V2KX-GP
C8303
C8328
DIS
SC1U6D3V2KX-GP
x01 change tolerant 20091117
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
C8314
DIS
SC1U6D3V2KX-GP
DY
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
DY
SC1U6D3V2KX-GP
DY
C8327
C8313
SC1U6D3V2KX-GP
DY
C8326
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
SC1U6D3V2KX-GP
DY
C8325
DIS
([email protected] PCIE_VDDR)
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
SC1U6D3V2KX-GP
DY
C8324
DIS
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
SC1U6D3V2KX-GP
DIS
C8323
DIS
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
C8312
SCD1U10V2KX-5GP
DIS
C8322
DIS
C8311
SC1U6D3V2KX-GP
DIS
C8321
DIS
C8310
SC1U6D3V2KX-GP
C8320
DIS
C8309
SC1U6D3V2KX-GP
DIS
DIS
C8308
SC1U6D3V2KX-GP
DIS
C8319
C8307
SC1U6D3V2KX-GP
C8318
C8306
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
D
DIS
SCD1U10V2KX-5GP
DIS
C8305
SCD1U10V2KX-5GP
C8304
1
+1.8V_RUN_VGA
x01 change tolerant 20091117
MEM I/O
x01 change tolerant 20091117
C8301
2
5 OF 8
VGA1E
2
5
For DDR3/GDDR5, MVDDQ = 1.5V
+1.5V_RUN
A
x02-20091208
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A2
Date:
GPU_POWER(4/5)
Document Number
Rev
A00
Berry
Wednesday, March 31, 2010
1
Sheet
83
of
92
5
4
3
2
8 OF 8
VGA1H
DPA_VDD18
AP22
AP23
DPD_VDD18
DPD_VDD18
DPB_VDD18
DPB_VDD18
DPD_VDD10
DPD_VDD10
DPB_VDD10
DPB_VDD10
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
+1.8V_RUN_VGA
DPA_VDD18
C8406
PARK
SC4D7U6D3V3KX-GP
x01 change tolerant 20091117
AP25
AP26
+1.0V_RUN_VGA
PARK
1
R8402
([email protected] DPD_VDD10)
([email protected] DPB_VDD10)
AN33
AP33
2
0R2J-2-GP
C8409
SC4D7U6D3V3KX-GP
DY
DPB_PVDD
DPB_PVSS
2
([email protected] DPF_VDD10)
DP mode
2
DPC_PVDD
DPC_PVSS
2
AK33
AK34
1
DIS
DPF_VDD10
DPF_VDD10
DPF_PVDD
DPF_PVSS
DPF_VDD10
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
1
2
DPD_VDD18
PARK
([email protected] DPB_PVDD)
1
R8405
AV29
AR28
([email protected] DPD_VDD18)
2
0R2J-2-GP
C8415
SC4D7U6D3V3KX-GP
DY
C8434
2DPEF_CALR
1
PARK
C8422
SCD1U10V2KX-5GP
x01 change tolerant 20091117
C
AV19
AR18
AM37
AN38
AL38
AM35
([email protected] DPF_PVDD) L8406
PARK
DPF_PVDD_1 1
R8407
2
0R2J-2-GP
C8429
DIS
PARK
1
R8408
2
0R2J-2-GP
x02 20091208
C8430
DIS
DIS
DIS
1
2
BLM15BD121SS1D-GP
C8416
SC4D7U6D3V3KX-GP
DIS
DPEF_CALR
MADISON-PRO-2-GP
DIS
R8406
150R2F-1-GP
1
2
1
2
SC1U6D3V2KX-GP
DIS
C8421
DY
x01 change tolerant 20091117
AM39
C8433
DIS
AU18
AV17
DPF_PVSS
x01 change tolerant 20091117
DIS
DIS
C8411
PARK
SCD1U10V2KX-5GP
([email protected] DPE_PVDD)
C8428
SCD1U10V2KX-5GP
AF39
AH39
AK39
AL34
AM34
DY
DPF_PVDD
DPF_VDD18
DPF_VDD18
DPE_PVDD
DPE_PVSS
DIS
C8410
([email protected] DPD_PVDD)
DPD_PVDD
DPD_PVSS
AF34
AG34
DPB_VDD18
C8414
SC4D7U6D3V3KX-GP
1
2
2
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
C8425
SCD1U10V2KX-5GP
DPF_VDD18
2
2
LVDS mode
([email protected] DPF_VDD10)
L8407
1
2
BLM15BD121SS1D-GP
C8426
SC4D7U6D3V3KX-GP
DIS
C8427
DIS
+1.0V_RUN_VGA
DIS
1
1
+1.8V_RUN_VGA
DIS
([email protected] DPC_PVDD)
AN34
AP39
AR39
AU37
1
1
1
2
([email protected] DPF_VDD18)
([email protected] DPF_VDD18)
SC1U6D3V2KX-GP
C8424
DIS
C8413
DIS
2
DPE_VDD10
DPE_VDD10
x01 change tolerant 20091117
LVDS mode
L8405 DIS
1
2
BLM18PG471SN1D-GP
C8423
SC4D7U6D3V3KX-GP
DIS
1
AL33
AM33
DIS
DP mode
C8412
DIS
AU28
AV27
DISSCD1U10V2KX-5GP
DPE_VDD10
D
DIS
2
L8408
1
2
BLM15BD121SS1D-GP
C8404
SC4D7U6D3V3KX-GP
C8419
DPA_PVDD
DPA_PVSS
1
+1.0V_RUN_VGA
DIS
DPE_VDD18
DPE_VDD18
2
([email protected] DPE_VDD10)
C8418
AH34
AJ34
1
2
AW28DPAB_CALR
150R2F-1-GP
SC1U6D3V2KX-GP
([email protected] DPE_VDD10)
DP mode
1
SC1U6D3V2KX-GP
DIS
2
LVDS mode
1
1
2
BLM18PG471SN1D-GP
C8401
SC4D7U6D3V3KX-GP
DPAB_CALR
DP PLL POWER
DP E/F POWER
C8408
PARK
SCD1U10V2KX-5GP
L8404
1
2
BLM15BD121SS1D-GP
1
DPCD_CALR
([email protected] DPE_VDD18)
SCD1U10V2KX-5GP
2
1
L8401
2
LVDS mode
DIS
PARK
([email protected] DPA_PVDD)
R8404
SC1U6D3V2KX-GP
([email protected] DPE_VDD18)
+1.8V_RUN_VGA
C8407
+1.8V_RUN_VGA
DPA_PVDD
x01 change tolerant 20091117
R8401 DIS
1
2DPCD_CALR AW18
150R2F-1-GP
DPE_VDD18
SCD1U10V2KX-5GP
2
1
DP mode
AN29
AP29
AP30
AW30
AW32
1
AN19
AP18
AP19
AW20
AW22
x01 change tolerant 20091117
([email protected] DPB_VDD18)
2
AP14
AP15
DPA_VDD18)
1
PARK
1
L8402
([email protected]
1
2
BLM15BD121SS1D-GP
2
1
1
2
C8405
SC10U6D3V5KX-1GP
1
+1.0V_RUN_VGA
DPB_VDD18
DIS
DNI for M96/M92
2
DPD_VDD18
C8403
DIS
2
DIS
AN27
AP27
AP28
AW24
AW26
DIS
2
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
SC1U6D3V2KX-GP
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
SCD1U10V2KX-5GP
2
1
AN17
AP16
AP17
AW14
AW16
C8402
2
+1.0V_RUN_VGA
L8403
1
2
BLM15BD121SS1D-GP
([email protected] DPA_VDD10)
AP31
AP32
1
DPA_VDD10
DPA_VDD10
1
DPC_VDD10
DPC_VDD10
DPA_VDD10
AP13
AT13
2
DPA_VDD18
DPA_VDD18
SC1U6D3V2KX-GP
DPC_VDD18
DPC_VDD18
([email protected] DPC_VDD10)
SC1U6D3V2KX-GP
2
1
+1.0V_RUN_VGA
AN24
AP24
SC1U6D3V2KX-GP
2
1
AP20
AP21
DP A/B POWER
1
DP C/D POWER
DPB_VDD18
SC1U6D3V2KX-GP
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
SCD1U10V2KX-5GP
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND/PX_EN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
C
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
2
D
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
1
6 OF 8
VGA1F
B
For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
VSS_MECH
VSS_MECH
VSS_MECH
A39 VSS_MECH1
AW1 VSS_MECH2
AW39VSS_MECH3
TPAD14-GP1
TPAD14-GP1
TPAD14-GP1
TP8401
TP8402
TP8403
MADISON-PRO-2-GP
DIS
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_DPPWR/GND(5/5)
Size
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
A2
Date:
Document Number
Rev
Berry
A00
Sheet
Monday, February 22, 2010
1
84
of
92
5
4
3
2
+1.5V_RUN
+1.5V_RUN
VRAM1
VRAM1_VREF
VRAM2_VREF
1
R8503
C
M96
2
VRAM_ZQ1
243R2F-2-GP
1
1
R8507
56R2F-1-GP
1
GPU_CLKA0_T
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,86 A_BA0
81,86 A_BA1
81,86 A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
81 CKEA0
81 DQMA2
81 DQMA0
K9
CKE
D3
E7
DMU
DML
M96
81 WEA0#
81 CASA0#
81 RASA0#
L3
K3
J3
W E#
CAS#
RAS#
B
QSAP_2 81
QSAN_2 81
DQSL
DQSL#
F3
G3
ODT
K1
ODTA0 81
CS#
RESET#
L2
T2
CSA0#_0 81
MEM_RST 81,86,87,88
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
C8519
SCD1U10V2KX-5GP
2
1
SC1U6D3V2KX-GP
2
1
M96 M96
C8521
M96
C8522
1
C8517
SC1U6D3V2KX-GP
2
1
1
C8518
SCD1U10V2KX-5GP
2
1
DQSU
DQSU#
C7
B7
SC1U6D3V2KX-GP
2
MDA20
MDA19
MDA23
MDA18
MDA22
MDA16
MDA21
MDA17
C8516
SC1U6D3V2KX-GP
2
1
D7
C3
C8
C2
A7
A2
B8
A3
C8524
SC1U6D3V2KX-GP
2
1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
M96 M96M96
M96
VRAM2_VREF
VRAM1_VREF
QSAP_0 81
QSAN_0 81
1
R8504
M96
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
2VRAM_ZQ2 L8
243R2F-2-GP
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,86 A_BA0
81,86 A_BA1
81,86 A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
81 CKEA0
K9
CKE
81 DQMA1
81 DQMA3
D3
E7
DMU
DML
L3
K3
J3
W E#
CAS#
RAS#
81 CLKA0
81 CLKA0#
81 WEA0#
81 CASA0#
81 RASA0#
81
E3
F7
F2
F8
H3
H8
G2
H7
MDA29
MDA24
MDA30
MDA26
MDA28
MDA27
MDA25
MDA31
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA8
MDA14
MDA9
MDA10
MDA15
MDA12
MDA13
MDA11
DQSU
DQSU#
C7
B7
QSAP_1 81
QSAN_1 81
DQSL
DQSL#
F3
G3
QSAP_3 81
QSAN_3 81
ODT
K1
ODTA0 81
CS#
RESET#
L2
T2
CSA0#_0 81
MEM_RST 81,86,87,88
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
D
C
DUMMY-K4W2G1646B-HC12-GP
M96
x01 20091121
MDA[0..31]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VREFDQ
VREFCA
ZQ
81,86 MAA0
81,86 MAA1
81,86 MAA2
81,86 MAA3
81,86 MAA4
81,86 MAA5
81,86 MAA6
81,86 MAA7
81,86 MAA8
81,86 MAA9
81,86 MAA10
81,86 MAA11
81,86 MAA12
81,86 MAA13
DUMMY-K4W2G1646B-HC12-GP
2
C8503
SCD01U16V2KX-3GP
VREFDQ
VREFCA
ZQ
2
M96
2
M96
H1
M8
L8
81,86 MAA0
81,86 MAA1
81,86 MAA2
81,86 MAA3
81,86 MAA4
81,86 MAA5
81,86 MAA6
81,86 MAA7
81,86 MAA8
81,86 MAA9
81,86 MAA10
81,86 MAA11
81,86 MAA12
81,86 MAA13
81 CLKA0
81 CLKA0#
R8508
56R2F-1-GP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M96
M96
M96
C8520
2
M96
A8
A1
C1
C9
D2
E9
F1
H9
H2
C8515
1
C8505
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
MDA3
MDA7
MDA1
MDA6
MDA2
MDA4
MDA0
MDA5
C8525
SCD1U10V2KX-5GP
2
1
1
M96
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E3
F7
F2
F8
H3
H8
G2
H7
2
1
2
M96
SC10U6D3V5KX-1GP
C8502
1 SC1U6D3V2KX-GP
2
1
M96 M96 M96M96
2
C8514
SC1U6D3V2KX-GP
2
1
C8513
K8
K2
N1
R9
B2
D9
G7
R1
N9
81
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
2
1
C8511
VRAM2
x01 change tolerant 20091117
MDA[0..31]
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
2
1
M96 M96M96
C8512
SC1U6D3V2KX-GP
2
C8510
SC1U6D3V2KX-GP
2
1
1
C8509
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
2
D
C8507
SCD1U10V2KX-5GP
2
1
x01 change tolerant 20091117
C8508
1
M96
B
+1.5V_RUN
1
1
+1.5V_RUN
R8513
2K1R2F-GP
2
R8510
2K1R2F-GP
2
M96
M96
VRAM2_VREF
2
M96
C8504
SCD1U10V2KX-5GP
1
R8512
2K1R2F-GP
2
M96
M96
C8506
SCD1U10V2KX-5GP
2
1
R8511
2K1R2F-GP
2
1
1
VRAM1_VREF
M96
x01 change tolerant 20091117
x01 change tolerant 20091117
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
GPU-VRAM1,2 (1/4)
Document Number
Custom
Date:
Rev
A00
Berry
Monday, March 29, 2010
Sheet
1
85
of
92
5
4
3
2
+1.5V_RUN
+1.5V_RUN
VRAM3
M96
VRAM3_VREF
VRAM4_VREF
1
R8603
M96
H1
M8
2VRAM_ZQ3 L8
243R2F-2-GP
81,85 MAA0
81,85 MAA1
81,85 MAA2
81,85 MAA3
81,85 MAA4
81,85 MAA5
81,85 MAA6
81,85 MAA7
81,85 MAA8
81,85 MAA9
81,85 MAA10
81,85 MAA11
81,85 MAA12
81,85 MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
81,85 A_BA0
81,85 A_BA1
81,85 A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
C
1
1
81 CLKA1
81 CLKA1#
R8608
56R2F-1-GP
2
M96
M96
1
GPU_CLKA1_T
81 CKEA1
K9
CKE
81 DQMA5
81 DQMA4
D3
E7
DMU
DML
81 WEA1#
81 CASA1#
81 RASA1#
L3
K3
J3
W E#
CAS#
RAS#
M96
QSAP_5 81
QSAN_5 81
F3
G3
ODT
K1
ODTA1 81
CS#
RESET#
L2
T2
CSA1#_0 81
MEM_RST 81,85,87,88
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
C8615
SC1U6D3V2KX-GP
2
1
C8616
SC1U6D3V2KX-GP
2
1
C7
B7
C8624
SCD1U10V2KX-5GP
2
1
DQSU
DQSU#
C8617
C8619
M96
VRAM4_VREF
VRAM3_VREF
QSAP_4 81
QSAN_4 81
1
R8604
M96
M96
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
2VRAM_ZQ4 L8
243R2F-2-GP
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,85 A_BA0
81,85 A_BA1
81,85 A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
81 CKEA1
K9
CKE
81 DQMA6
81 DQMA7
D3
E7
DMU
DML
81 WEA1#
81 CASA1#
81 RASA1#
L3
K3
J3
W E#
CAS#
RAS#
81 CLKA1
81 CLKA1#
81
E3
F7
F2
F8
H3
H8
G2
H7
MDA61
MDA57
MDA63
MDA60
MDA59
MDA56
MDA62
MDA58
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA50
MDA55
MDA49
MDA52
MDA48
MDA54
MDA51
MDA53
DQSU
DQSU#
C7
B7
QSAP_6 81
QSAN_6 81
DQSL
DQSL#
F3
G3
QSAP_7 81
QSAN_7 81
ODT
K1
ODTA1 81
CS#
RESET#
L2
T2
CSA1#_0 81
MEM_RST 81,85,87,88
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
D
C
DUMMY-K4W2G1646B-HC12-GP
M96
x01 20091121
MDA[32..63]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VREFDQ
VREFCA
ZQ
81,85 MAA0
81,85 MAA1
81,85 MAA2
81,85 MAA3
81,85 MAA4
81,85 MAA5
81,85 MAA6
81,85 MAA7
81,85 MAA8
81,85 MAA9
81,85 MAA10
81,85 MAA11
81,85 MAA12
81,85 MAA13
DUMMY-K4W2G1646B-HC12-GP
2
C8603
SCD01U16V2KX-3GP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
MDA46
MDA43
MDA45
MDA40
MDA44
MDA41
MDA47
MDA42
DQSL
DQSL#
2
R8607
56R2F-1-GP
VREFDQ
VREFCA
ZQ
D7
C3
C8
C2
A7
A2
B8
A3
M96
M96 M96 M96M96
SC10U6D3V5KX-1GP
2
1
1
C8608
2
1
2
M96
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8606
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C8625
SCD1U10V2KX-5GP
2
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M96 M96M96
SC10U6D3V5KX-1GP
2
1
A8
A1
C1
C9
D2
E9
F1
H9
H2
x01 change tolerant 20091117
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
MDA36
MDA38
MDA33
MDA39
MDA32
MDA34
MDA35
MDA37
C8622
SC1U6D3V2KX-GP
2
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E3
F7
F2
F8
H3
H8
G2
H7
C8623
SC1U6D3V2KX-GP
2
1
K8
K2
N1
R9
B2
D9
G7
R1
N9
81
C8618
SCD1U10V2KX-5GP
2
1
M96M96 M96 M96 M96
VRAM4
x01 change tolerant 20091117
MDA[32..63]
C8621
SCD1U10V2KX-5GP
2
1
C8613
SC1U6D3V2KX-GP
2
1
C8614
SC1U6D3V2KX-GP
2
1
C8611
SC1U6D3V2KX-GP
2
1
M96M96
C8612
SC1U6D3V2KX-GP
2
1
C8609
SC1U6D3V2KX-GP
2
1
D
C8610
SC1U6D3V2KX-GP
2
1
C8607
SC1U6D3V2KX-GP
2
1
C8602
SC1U6D3V2KX-GP
2
1
x01 change tolerant 20091117
M96
1
M96
B
B
+1.5V_RUN
1
+1.5V_RUN
1
R8605
2K1R2F-GP
2
1
2
1
M96
R8606
2K1R2F-GP
C8601
SCD1U10V2KX-5GP
2
1
R8602
2K1R2F-GP
1
VRAM4_VREF
VRAM3_VREF
2
M96
M96
M96
C8605
SCD1U10V2KX-5GP
2
2
R8601
2K1R2F-GP
M96
M96
x01 change tolerant 20091117
x01 change tolerant 20091117
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM3,4 (2/4)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
Document Number
Custom
Rev
A00
Berry
Date:
Monday, March 29, 2010
Sheet
1
86
of
92
5
4
3
2
+1.5V_RUN
+1.5V_RUN
VRAM5
VRAM5_VREF
VRAM6_VREF
1
R8704
C
20090902
2
DIS
VRAM_ZQ5
243R2F-2-GP
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,88 B_BA0
81,88 B_BA1
81,88 B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
R8708
56R2F-1-GP
2
DIS
2
DIS
81 CKEB0
K9
81 DQMB3
81 DQMB1
D3
E7
DMU
DML
81 W EB0#
81 CASB0#
81 RASB0#
L3
K3
J3
WE#
CAS#
RAS#
1
2
DIS
VRAM6
F3
G3
ODT
K1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
CKE
H1
M8
L8
VREFDQ
VREFCA
ZQ
81,88 MAB0
81,88 MAB1
81,88 MAB2
81,88 MAB3
81,88 MAB4
81,88 MAB5
81,88 MAB6
81,88 MAB7
81,88 MAB8
81,88 MAB9
81,88 MAB10
81,88 MAB11
81,88 MAB12
81,88 MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,88 B_BA0
81,88 B_BA1
81,88 B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
81 CKEB0
K9
CKE
81 DQMB0
81 DQMB2
D3
E7
DMU
DML
81 W EB0#
81 CASB0#
81 RASB0#
L3
K3
J3
WE#
CAS#
RAS#
C8718
QSBP_3 81
QSBN_3 81
C8725
SCD1U10V2KX-5GP
2
1
DIS
C7
B7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SC10U6D3V5KX-1GP
2
1
DIS
DQSU
DQSU#
A8
A1
C1
C9
D2
E9
F1
H9
H2
DY
C8724
SC1U6D3V2KX-GP
2
1
DIS
MDB26
MDB27
MDB30
MDB24
MDB31
MDB25
MDB29
MDB28
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C8722
SC1U6D3V2KX-GP
2
1
DIS
D7
C3
C8
C2
A7
A2
B8
A3
K8
K2
N1
R9
B2
D9
G7
R1
N9
C8723
SC1U6D3V2KX-GP
2
1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSL
DQSL#
GPU_CLKB0_T
C8703
SCD01U16V2KX-3GP
MDB14
MDB13
MDB12
MDB15
MDB11
MDB8
MDB9
MDB10
C8721
SCD1U10V2KX-5GP
2
1
DIS
VREFDQ
VREFCA
ZQ
E3
F7
F2
F8
H3
H8
G2
H7
C8720
SC1U6D3V2KX-GP
2
1
DIS
H1
M8
L8
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
C8715
SC1U6D3V2KX-GP
2
1
DIS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
1
1
A8
A1
C1
C9
D2
E9
F1
H9
H2
81,88 MAB0
81,88 MAB1
81,88 MAB2
81,88 MAB3
81,88 MAB4
81,88 MAB5
81,88 MAB6
81,88 MAB7
81,88 MAB8
81,88 MAB9
81,88 MAB10
81,88 MAB11
81,88 MAB12
81,88 MAB13
81 CLKB0
81 CLKB0#
R8707
56R2F-1-GP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C8717
SC1U6D3V2KX-GP
2
1
DIS
C8714
SC1U6D3V2KX-GP
2
1
DIS
C8708
K8
K2
N1
R9
B2
D9
G7
R1
N9
x01 change tolerant 20091117
MDB[0..31] 81
SC10U6D3V5KX-1GP
2
1
DIS
C8706
SC10U6D3V5KX-1GP
2
1
DIS
C87013
SC1U6D3V2KX-GP
2
1
DIS
C87012
SC1U6D3V2KX-GP
2
1
DIS
SC10U6D3V5KX-1GP
2
1
DIS
C87011
SC1U6D3V2KX-GP
2
1
DIS
C8709
SCD1U10V2KX-5GP
2
1
DIS
C8710
SC1U6D3V2KX-GP
2
1
DIS
C8707
SCD1U10V2KX-5GP
2
1
DIS
C8702
SC1U6D3V2KX-GP
2
1
DIS
x01 change tolerant 20091117
D
1
C8719
VRAM6_VREF
VRAM5_VREF
QSBP_1 81
QSBN_1 81
1
R8706
2
DIS
VRAM_ZQ6
243R2F-2-GP
ODTB0 81
CSB0#_0 81
MEM_RST 81,85,86,88
81 CLKB0
81 CLKB0#
DUMMY-K4W 2G1646B-HC12-GP
E3
F7
F2
F8
H3
H8
G2
H7
MDB16
MDB18
MDB20
MDB19
MDB22
MDB17
MDB23
MDB21
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB1
MDB5
MDB2
MDB4
MDB3
MDB7
MDB0
MDB6
DQSU
DQSU#
C7
B7
QSBP_0 81
QSBN_0 81
DQSL
DQSL#
F3
G3
QSBP_2 81
QSBN_2 81
ODT
K1
ODTB0 81
CS#
RESET#
L2
T2
CSB0#_0 81
MEM_RST 81,85,86,88
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
D
C
DUMMY-K4W 2G1646B-HC12-GP
DIS
x01 20091121
MDB[0..31] 81
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DIS
B
B
1
+1.5V_RUN
1
+1.5V_RUN
R8701
2K1R2F-GP
R8703
2K1R2F-GP
2
DIS
2
DIS
1
C8705
SCD1U10V2KX-5GP
2
DIS
DIS
2
R8705
2K1R2F-GP
2
DIS
DIS
1
1
R8702
2K1R2F-GP
VRAM6_VREF
C8701
SCD1U10V2KX-5GP
2
1
VRAM5_VREF
x01 change tolerant 20091117
x01 change tolerant 20091117
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM5,6 (3/4)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
87
of
92
5
4
3
2
+1.5V_RUN
+1.5V_RUN
VRAM7
DIS
VRAM7_VREF
VRAM8_VREF
1
R8803
C
2
DIS
VRAM_ZQ7
243R2F-2-GP
H1
M8
L8
VREFDQ
VREFCA
ZQ
81,87 MAB0
81,87 MAB1
81,87 MAB2
81,87 MAB3
81,87 MAB4
81,87 MAB5
81,87 MAB6
81,87 MAB7
81,87 MAB8
81,87 MAB9
81,87 MAB10
81,87 MAB11
81,87 MAB12
81,87 MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,87 B_BA0
81,87 B_BA1
81,87 B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
R8807
56R2F-1-GP
R8808
56R2F-1-GP
2
DIS
2
DIS
81 CKEB1
81 DQMB4
81 DQMB5
D3
E7
DMU
DML
81 W EB1#
81 CASB1#
81 RASB1#
L3
K3
J3
WE#
CAS#
RAS#
1
GPU_CLKB1_T
DIS
2
B
ODT
ODTB1 81
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
DY
C8817
DIS
QSBP_4 81
QSBN_4 81
C8825
SCD1U10V2KX-5GP
2
1
DIS
QSBP_5 81
QSBN_5 81
K1
C8824
SC1U6D3V2KX-GP
2
1
DIS
DQSL
DQSL#
F3
G3
DY
C8823
SC1U6D3V2KX-GP
2
1
C7
B7
C8822
SC1U6D3V2KX-GP
2
1
DQSU
DQSU#
C8821
SCD1U10V2KX-5GP
2
1
DIS
MDB36
MDB35
MDB39
MDB32
MDB37
MDB33
MDB38
MDB34
C8820
SC1U6D3V2KX-GP
2
1
DIS
D7
C3
C8
C2
A7
A2
B8
A3
C8819
SC1U6D3V2KX-GP
2
1
DIS
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DY
C8818
DIS
VRAM8_VREF
VRAM7_VREF
1
R8804
CSB1#_0 81
MEM_RST 81,85,86,87
2
DIS
VRAM_ZQ8
243R2F-2-GP
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
81,87 MAB0
81,87 MAB1
81,87 MAB2
81,87 MAB3
81,87 MAB4
81,87 MAB5
81,87 MAB6
81,87 MAB7
81,87 MAB8
81,87 MAB9
81,87 MAB10
81,87 MAB11
81,87 MAB12
81,87 MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
81,87 B_BA0
81,87 B_BA1
81,87 B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
81 CKEB1
K9
CKE
81 DQMB7
81 DQMB6
D3
E7
DMU
DML
81 W EB1#
81 CASB1#
81 RASB1#
L3
K3
J3
WE#
CAS#
RAS#
81 CLKB1
81 CLKB1#
DUMMY-K4W 2G1646B-HC12-GP
E3
F7
F2
F8
H3
H8
G2
H7
MDB53
MDB51
MDB55
MDB49
MDB54
MDB48
MDB52
MDB50
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB61
MDB62
MDB58
MDB59
MDB63
MDB56
MDB57
MDB60
DQSU
DQSU#
C7
B7
QSBP_7 81
QSBN_7 81
DQSL
DQSL#
F3
G3
QSBP_6 81
QSBN_6 81
ODT
K1
ODTB1 81
CS#
RESET#
L2
T2
CSB1#_0 81
MEM_RST 81,85,86,87
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
D
C
DUMMY-K4W 2G1646B-HC12-GP
DIS
x01 20091121
MDB[32..63] 81
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DIS
1
+1.5V_RUN
1
+1.5V_RUN
B
R8801
2K1R2F-GP
R8805
2K1R2F-GP
2
DIS
2
DIS
1
C8801
SCD1U10V2KX-5GP
R8806
2K1R2F-GP
DIS
C8804
SCD1U10V2KX-5GP
2
DIS
2
DIS
DIS
1
1
R8802
2K1R2F-GP
VRAM8_VREF
2
1
VRAM7_VREF
2
C8803
SCD01U16V2KX-3GP
MDB40
MDB43
MDB47
MDB44
MDB41
MDB45
MDB42
MDB46
1
81 CLKB1
81 CLKB1#
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
SC10U6D3V5KX-1GP
2
1
C8807
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SC10U6D3V5KX-1GP
2
1
C8806
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VRAM8
x01 change tolerant 20091117
MDB[32..63] 81
C8816
SC1U6D3V2KX-GP
2
1
C8814
SC1U6D3V2KX-GP
2
1
DIS
K8
K2
N1
R9
B2
D9
G7
R1
N9
SC10U6D3V5KX-1GP
2
1
C8813
SC1U6D3V2KX-GP
2
1
DIS
SC10U6D3V5KX-1GP
2
1
DIS
C8812
SCD1U10V2KX-5GP
2
1
DIS
C8811
SCD1U10V2KX-5GP
2
1
DIS
C8810
SC1U6D3V2KX-GP
2
1
DIS
C8809
SC1U6D3V2KX-GP
2
1
DIS
C8808
SC1U6D3V2KX-GP
2
1
DIS
C8802
SC1U6D3V2KX-GP
2
1
DIS
x01 change tolerant 20091117
D
1
x01 change tolerant 20091117
x01 change tolerant 20091117
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM7,8 (4/4)
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
88
of
92
5
4
3
2
1
RT8208BGQW for +VGA_CORE
SSID = Video.PWR.Regulator
D
D
X01
DYRB551V-30-2GP
1
PC8907
SC2200P50V2KX-2GP
2
2
1
1
2
DIS
PTC8903 C
DIS
2
PC8915
SCD1U10V2KX-5GP
2
1
1
1
SC10P50V2JN-4GP
DY
PTC8902
2
PC8917
DIS
PTC8901
DY
PC8913
1
1
SC10P50V2JN-4GP
DY
2
DY
PR8908
10KR2F-2-GP
+GFX_CORE_FB
PC8912
SCD1U10V2KX-5GP
PR8909
150KR2F-L-GP
x01 change tolerant 20091117
DIS
Madison-LP
PWRCNTL_1
+VGA_CORE
H
H
0.9V
L
H
0.95V
H
L
1.05V
L
L
1.12V
PWRCNTL_0
PWRCNTL_1
+VGA_CORE
H
H
0.9V
L
H
0.95V
L
L
1.12V
PR8912
44K2R2F-1-GP
2
DIS
B
PWRCNTL_1#
PWRCNTL_0#
Park-XT
PWRCNTL_0
PR8911
49K9R2F-L-GP
DIS
2
B
1
1
x01 20091124
2
DY
1
1
2
X02-20100201
+GFX_CORE_EN_R
A
2
1
1
2
DY
+GFX_CORE_VOUT
PC8910
2
K
D8901
20091111
DIS
1
PM_SLP_S3#
1
22,37,42,47,50,51
DY
SC330P50V2KX-3GP
RT8208B:74.08208.A73
2
0R0402-PAD
DIS
S
S
S
G
S
S
S
G
RT8208BGQW -GP
1
PR8921
2
4
3
2
1
+GFX_CORE_VOUT
A00-20100204
37 GFX_CORE_EN
2D2R5F-2-GP
PG8920
GAP-CLOSE-PWR-3-GP
1
PW RCNTL_1 82
PU8904
2
VOUT
PU8903
1
GND
PW RCNTL_1#
PW RCNTL_0#
DIS
PR8906
PW RCNTL_0 82
2
EM/DEM
+GFX_CORE_FB
1VGA_CORE_DIV
1
2
7
3
14
5
6
SE330U2VDM-L-GP
17
G0
FB
G1
D1
D0
DIS
1
2
IND-D56UH-12-GP
SE330U2VDM-L-GP
+GFX_CORE_EN_R 15
DIS
PGOOD
CS
D
D
D
D
PC8904
SC1U10V2KX-1GP
4
10
7K15R2F-L-GP
12
11
8
D
D
D
D
PR8905
UGATE
PHASE
LGATE
+VGA_CORE
x01 change tolerant 20091117
PL8901
2
49,50,51,90 RUNPW ROK
VDD
X02-20100116
PR8902
PC8906
+GFX_CORE_BOOT
2
1 DIS
2
DIS 1+GFX_CORE_BOOT_C
1R3J-L1-GP
SCD1U25V3KX-GP
+GFX_CORE_UGATE
+GFX_CORE_PHASE
+GFX_CORE_LGATE
SE330U2VDM-L-GP
C
2
13
Vout=0.75V*(R1+R2)/R2
Design Current = 21.94A
24.14A<OCP< 28.53A
SIR460DP-T1-GE3-GP
4
3
2
1
+GFX_CORE_VDD
20091124
DIS 2+GFX_CORE_CS
1
BOOT
SIR460DP-T1-GE3-GP
4
3
2
1
2
1
DIS
10R2F-L-GP
TON
VDDP
DIS
S
S
S
G
PU8901
16
9
DIS
DIS
249KR2F-GP
PR8903
X01
PR8910
1
DIS 2
+GFX_CORE_TON
DIS
5
6
7
8
1
PC8908
SC1U10V2KX-1GP
DIS
PC8911
SCD1U25V2KX-GP
5
6
7
8
D
D
D
D
PU8902
SI7686DP-T1-GP
2
DIS
2
DIS
+5V_RUN
PC8903
SC10U25V6KX-1GP
1
PC8914
SC10U25V6KX-1GP
20091111
5
6
7
8
X01
SC10U25V6KX-1GP
PC8905
X01 EMI stuff 20091118
+PW R_SRC
M96-LP
PWRCNTL_0
PWRCNTL_1
H
H
+VGA_CORE
0.9V
L
H
0.95V
L
L
1.0V
<Core Design>
A
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L
H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
5
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
RT8208B_+VGA_CORE
http://laptop-motherboard-schematic.blogspot.com/
4
3
A
2
Size
A3
Date:
Document Number
Rev
Arsenal DJ1 Discrete
W ednesday, March 31, 2010
Sheet
1
89
A00
of
92
5
4
3
2
1
APL5930 for +1.8V_RUN_VGA
+1.8V_RUN_VGA_P
1
GAP-CLOSE-PWR
PG9004
2
1
+1.8V_RUN_VGA
1
DIS
DIS
1
1
PC9006
PC9007
DY
1
3
PC9005
2
DIS
SO-8-P
84.27002.F3F
Vout=0.8V*(R1+R2)/R2
M96
PR9006
13K3R2F-L1-GP
DIS
2
10R2J-2-GP
2
1.8V_DIS 1
R9005
PR9003
2
GND
2
1
APL5930KAI-TRG-GP
FB
1
SC4700P50V2KX-1GP
2
1
4
+1.8V_RUN_VGA_P
2
1
1.8V_DIS_GATE
6
5
2
M96
5
9
3
4
SC68P50V2JN-1GP
X02-20091230
VIN#5
VIN#9
VOUT#3
VOUT#4
DIS
PC9001
Design Current =1.13A
SC22U6D3V5MX-2GP
EN
DY
PQ9001
2N7002EDW-GP
1
POK
8
16K5R2F-2-GP
Vo=0.8*(1+(R1/R2))
7
GAP-CLOSE-PWR
SC22U6D3V5MX-2GP
1
R9009
PR9002
1
21.8V_VGA_RUN_EN_C
0R0402-PAD
RUNPWROK
37 1.8V_VGA_RUN_EN
1
49,50,51,89
R9006
100KR2J-1-GP
5912_1.8V_DELAY_FB
2
M96
21.8V_RUN_VGA_POK
0R2J-2-GP
2
PU9001
M96
VCNTL
GAP-CLOSE-PWR
+5V_ALW
X02-20091230
DIS
D
PC9004
DY
6
X02-20091230
PC9003
GAP-CLOSE-PWR
PG9003
1
2
2
DIS
1
1
PC9002
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
PG9001
2
1
PG9002
2
+1.8V_RUN_VGA_VIN
2
+5V_RUN
SC10U6D3V5MX-3GP
D
+1.8V_RUN_VGA_VIN
2
+3.3V_RUN
+1.8V_RUN_VGA
1.8V_VGA_RUN_EN
C
C
X02-20091208
+5V_ALW
1.0V_DIS 1
R9010
+1.0V_RUN_VGA
SO-8-P
1
2
1
2
M96
M96
M96
2
10R2J-2-GP
PC9013
M96
2
0R5J-5-GP
R9011
1
1
1
PC9012
X01 20091120
DYPC9014
2
2
APL5930KAI-TRG-GP
PR9009
2
GND
FB
PARK
1
3
4
2
VOUT#3
VOUT#4
M96
X02-20091208
1
EN
+1.05V_VTT
5
9
SCD01U16V2KX-3GP
3
84.27002.F3F
+1.0V_RUN_VGA
Design Current: 1.51A
+1.0V_RUN_VGA
VIN#5
VIN#9
1
4
B
5930_1.0VRUN_FB
1
R9008
M96
2 1.0V_RUN_VGA_EN
0R2J-2-GP
DY
2
0R2J-2-GP
1
1
R9003
Vout=0.8V*(R1+R2)/R2
M96
RUNPWROK
PR9011
32K4R2F-1-GP
2
6
5
2
1
8
PC9011
DY
PQ9002
2N7002EDW-GP
M96
1.0V_DIS_GATE_EN
SC4700P50V2KX-1GP
2
1
1
21.0V_RUN_VGA_EN_C
0R0402-PAD
X02-20091224
PC9010
DY
6
1
2
37 1.0V_RUN_VGA_EN
B
37 3.3V_RUN_VGA_EN
POK
PR9007
3
3.3V_RUN_VGA_1
7
RUNPWROK
M96
SC10U6D3V3MX-GP
2
49,50,51,89
PC9009
SC10U6D3V3MX-GP
1
R9004
100R2J-2-GP
12KR2F-L-GP
M96
PU9002
1.0V_DIS_GATE
1
4
5
6
M96
2N7002EDW-GP
84.27002.F3F
R9007
100KR2J-1-GP
M96
3.3V_ALW_1
Q9002
M96
2
2
Id: 2A
Rds: 0.15ohm
G
1
2
M96
PC9008
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
R9002
100KR2J-1-GP
D
SI2301CDS-T1-GE3-GP
M96
SC10U6D3V5MX-3GP
+3.3V_ALW
S
+3.3V_RUN
+1.5V_SUS
+3.3V_RUN_VGA
VCNTL
2
0R2J-2-GP
Q9001
1
PARK
1
R9001
APL5930KAI for +1.0V_RUN_VGA
2
+3.3V_RUN_VGA
X01-20091116
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DISCRETE VGA POWER
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
C
Document Number
Date:
Monday, March 29, 2010
Rev
Berry
A00
Sheet
1
90
of
92
5
4
3
2
1
D15 Intel-Power Up Sequence
(AC mode)
(DC mode)
red word: KBC GPIO
+RTC_VCC
+RTC_VCC
T1
T1
PCH_RTCRST#
PCH_RTCRST#
+PWR_SRC
+PWR_SRC
T2
+3.3V_RTC_LDO
D
red word: KBC GPIO
T2
+3.3V_RTC_LDO
T3
S5_ENABLE
KBC GPIO36 control
Press Power button
KBC_PWRBTN_EC#
T4
+5V_ALW
T5
+3.3V_ALW
T6
T4
S5_ENABLE
+5VALW_PCH_VCC5REFSUS
KBC GPIO36 control
T5
+5V_ALW
+15V_ALW
T7
T8
T9
T10
>10ms
PCH_RSMRST#(EC Delay 40ms)
T11
+5V_ALW & +3.3V_ALW need meet 0.7V difference
T7
+5V_ALW & +3.3V_ALW need meet 0.7V difference
+5VALW_PCH_VCC5REFSUS
PCH to KBC GPI94
SUS_PWR_DN_ACK
T6
+3.3V_ALW
TPS51125 to KBC GPIO46
3V_5V_POK
D
KBC_PWRBTN_EC# GPIO3
EC_ENABLE# (GPIO51) keep low
T3
+KBC_PWR
KBC GPIO43 to PCH
+15V_ALW
PCH to KBC GPIO00
3V_5V_POK
PCH_SUSCLK_KBC
T8
T9
TPS51125 to KBC GPIO46
T10
KBC GPO84 to PCH
PM_PWRBTN#
PCH to KBC GPI94
T12 <200ms
AC_PRESENT_EC
SUS_PWR_DN_ACK
T11
KBC GPIO43 to PCH
PCH_RSMRST#
Press Power button
T12 >10ms
T13
PCH_SUSCLK_KBC
AC KBC_PWRBTN_EC#
PCH to KBC GPIO01
KBC_PWRBTN_EC# GPIO3
3V_5V_POK
T13
DC PCH_RSMRST#
KBC GPO84 to PCH
T14
AC PM_PWRBTN#
PM_SLP_S4#
AC PM_PWRBTN#
T14
T15
>30us
PM_SLP_S3#
T16
PM_LAN_ENABLE
PM_SLP_S4#
T15
>30us
PM_SLP_S3#
C
KBC GPO16 to LAN
T17
+3.3V_LAN
T16
PM_LAN_ENABLE
KBC GPO16 to LAN
T17
+3.3V_LAN
+1.5V_SUS
T18
+V_DDR_REF(0.9V)
T19
+5V_RUN
+5V_RUN & +3.3V_RUN need meet 0.7V difference
T21
T18
+V_DDR_REF(0.9V)
T19
C
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5V_RUN
T20
+3.3V_RUN
T21
T22
+5VS_PCH_VCC5REF
T20
+3.3V_RUN
+1.5V_SUS
T22
+5VS_PCH_VCC5REF
+1.5V_RUN
T23
+1.8V_RUN
T24
T25 >1ms
H_PWRGD
KBC GPIO71 to RT8208B
+1.5V_RUN
T23
+1.8V_RUN
T24
T25 >1ms
GFX_CORE_EN(Discrete only)
H_PWRGD
KBC GPIO71 to RT8208B
GFX_CORE_EN(Discrete only)------Delay 5ms
T27
T28
T28
KBC GPIO30 to APL5930
T30
T31
+1.8V_RUN_VGA(Discrete only)
T30
KBC GPIO66 to APL5930
+3.3V_RUN_VGA(Discrete only)
T31
T32
+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved
T32
+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved
1.8V_VGA_RUN_EN(Discrete only)------Delay 5ms
+1.8V_RUN_VGA(Discrete only)
KBC GPIO66 to APL5930
1.8V_VGA_RUN_EN(Discrete only)
T29
+1.0V_RUN_VGA(Discrete only)
KBC GPIO30 to APL5930
T29
+1.0V_RUN_VGA(Discrete only)
1.0V_RUN_VGA_EN(Discrete only)------Delay 4ms
+3.3V_RUN_VGA(Discrete only)
T27
1.0V_RUN_VGA_EN(Discrete only)
T26
+VGA_CORE(Discrete only)
T26
+VGA_CORE(Discrete only)
KBC GPI95
T33
-->Reserved for sequence
KBC GPI95
RUNPWROK
T33
-->Reserved for sequence
T34
T35
+1.05V_VTT
RUNPWROK
1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output
T34
T35
+1.05V_VTT
B
1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output
T37
+0.75V_DDR_VTT
TPS51218 to KBC GPI34
T36
for s3 reduction)
TPS51218 to KBC GPI34
T36
for s3 reduction)
B
T38
H_VTTPWRGD
T37
+0.75V_DDR_VTT
T38
H_VTTPWRGD
+1.05V_VTT
T39
CPU to TPS51611
GFX_VR_EN(UMA only)
+1.05V_VTT
T39
UMA GFX CORE Power
T40
+CPU_GFX_CORE(UMA only)
CPU to TPS51611
GFX_VR_EN(UMA only)
UMA GFX CORE Power
T40
+CPU_GFX_CORE(UMA only)
1.5CPU_1.05VTT_PWRGD
T41
( >99ms )
T41
T42
( >99ms )
CLKIN_BCLK(from CK505) stable
CPU CORE Power
<3ms
43 >1ms
CLK_CPU_BCLK
CLKIN_BCLK(from CK505) stable
43
ISL62883 to CLOCKGEN
1.5CPU_1.05VTT_PWRGD
1.5CPU_1.05VTT_PWRGD
T46 >5ms
ISL62884 to KBC GPO14
3ms<
+1.5V_RUN_CPU
T46 >5ms
KBC GPIO47 to PCH
Delay 10ms
3ms<
PM_PWROK
+1.5V_RUN_CPU
T47 <20ms
T49 >100ns
PM_DRAM_PWRGD
T47 <20ms
T49 >100ns
PM_PWROK
+VCC_CORE
(for S3 Reduction)
H_VTTPWRGD
T50 >1ms
PM_PWROK
+VCC_CORE
T51 >1ms
0.05ms<
T52 <650ms
H_PWRGD
T53
0.05ms<
T52 <650ms
>1ms
PLT_RST#
T53
>1ms
PLTRST_DELAY#
PLTRST_DELAY#
KBC LRESET#
T54
5
KBC GPIO45
<Core Design>
T55
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
http://laptop-motherboard-schematic.blogspot.com/
4
KBC LRESET#
T54
H_CPURST#
KBC GPIO45
T55
H_CPURST#
A
T51 >1ms
T50 >1ms
H_PWRGD
PLT_RST#
T48 >1ms
T48 >1ms
(for S3 Reduction)
H_VTTPWRGD
T45
Delay 10ms
T45
KBC GPIO47 to PCH
PM_PWROK
ISL62884 to KBC GPO14
T44 >1ms
IMVP_PWRGD
CK_PWRGD
T44 >1ms
ISL62883 to CLOCKGEN
CK_PWRGD
>1ms
IMVP_PWRGD
PM_DRAM_PWRGD
CPU CORE Power
CLK_CPU_BCLK
T42
+VCC_CORE
<3ms
+VCC_CORE
KBC GPO53 to ISL62883
IMVP_VR_ON
A
KBC GPO53 to ISL62883
IMVP_VR_ON
1.5CPU_1.05VTT_PWRGD
3
2
Title
Power Sequence
Size
A1
Date:
Document Number
Rev
Berry
Tuesday, March 02, 2010
1
A00
Sheet
91
of
92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5
http://laptop-motherboard-schematic.blogspot.com/
4
3
2
Size
A3
Date:
Change History
Document Number
Rev
Berry
W ednesday, February 10, 2010
A00
Sheet
1
92
of
92
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