Telechargé par Abir Ayed

02 IO Peripheral Interfaces

publicité
Processor Interfacing
Emir DAMERGI
INSAT 2018/19
Introduction:
Control Bus
Processor
Address Bus
Memory
Data Bus
In processor based systems (Computers, Embedded systems), the processor is
connected to Memory through :
• Control Bus:
• Address Bus:
• Data Bus:
DAMERGI Emir – INSAT 2019
2
The processor: Busses
/ RD
/ WR
Byte Enable
Control Bus:
/RD = Read  When active (0), the Processor
reads from Memory.
/WR = Write  When active (0), the processor
writes to Memory.
Byte enable: A group of lines that indicate the
nbr of bytes to read.
AN-1
Processor
A1
A0
Address Bus:
N Address lines = Address bus size
 The processor can address up to 2N Words.
DM-1
D1
D0
Data Bus:
M data lines = Data Bus size = Word Size
(8, 16, 32 , 64 bits)
DAMERGI Emir – INSAT 2019
3
The Processor : Data Size
/ RD
/ WR
Byte enable
32 bits Processors are processors
with 32 bits data bus
 For 32 bits processors:
• Word = 32 bits
AN-1
Processor
A1
A0
DM-1
D1
D0
• Halfword = 16 bits
• Doubleword = 64 bits
Data Bus:
M data lines = Data Bus size = Word Size
(8, 16, 32 , 64 bits)
DAMERGI Emir – INSAT 2019
4
The Processor: Addressing Capabilty/Space
/RD
/WR
Byte enable
Processor Addressing Capabilty =
2N * Words = 2N * M/8 Bytes
(expressed in Bytes)
AN-1
Processor
A1
A0
Processor Address Space :
0 -> (2N * M/8) – 1
0  Addr Capability (in Bytes)
DM-1
D1
D0
1KByte =210 , 1MByte = 220 and 1GByte = 230
DAMERGI Emir – INSAT 2019
5
The Processor: Addressing Capabilty/Space
/RD
/WR
Byte enable
Example : A processor with 30 Address lines
and 32 Data lines
Processor Addressing Capabilty:
= 230 * 32/8 = 1073741824 * 4 Bytes
AN-1
Processor
= 4294967296 Bytes = 4 GB (Giga Byte)
A1
A0
Processor Adrress Space:
0  4294967295
DM-1
D1
D0
1KByte =210 , 1MByte = 220 and 1GByte = 230
DAMERGI Emir – INSAT 2019
6
The Processor: Addresses
2N * M/8 -1
A N-1
Each byte in the processor
…
….
Processor
A0
address space has its own
D M-1
unique address.
…
….
D0
0
Processor Address Space
DAMERGI Emir – INSAT 2019
7
The Processor: Addresses
Processor with Data Bus Size M=8  Addressing capability = 2N bytes
Example: N =10
Byte
Address
2N-1
Processor
A0
D M-1
…
….
D0
Address Space = 0..1023
Byte Address
A N-1
…
….
Addressing Capability = 210*(8/8)=1024
…
1023
…
2
1
0
…
1
0
M=16 (2 Bytes)
M=8 (1 Byte)
DAMERGI Emir – INSAT 2019
8
The Processor: Addresses
Processor with Data Bus Size M=16  Addressing capability= 2*2N
Example: N =10
Byte Address
(2*2N)-1 (2*2N)-2
Address Space = 0..2047
Processor
A N-1
Addressing Capability = 210*(16/8)=2048
…
…
Byte Address
A0
…
…
2047
2046
D M-1
5
4
3
2
…
…
1
0
3
2
1
0
…
….
…
….
D0
M=16 (2 Bytes)
M=16 (2 Bytes)
DAMERGI Emir – INSAT 2019
9
The Processor: Addresses
Processor with Data Size M=32  Addressing capability= 4*2N Bytes
Byte Address
Processor
(4*2N)-1 (4*2N)-2
A N-1
…
….
2N Words
A0
…
…
D M-1
…
…
11
10
9
8
7
6
5
4
3
2
1
0
…
….
D0
1 word =
32 bits = 4bytes
M=32 (4 Bytes)
DAMERGI Emir – INSAT 2019
10
The Processor: Addresses
Example: N =10
Addressing Capability = 210 * (32/2) = 4096
Address Space = 0..4095
Byte Address
4095
4094
4093
4092
…
…
11
10
9
8
7
6
5
4
3
2
1
0
1024 Words
M=32 (4 Bytes)
DAMERGI Emir – INSAT 2019
11
The Processor: Aligned/Unaligned Memory Access
No support for unaligned data:
The whole Data must reside
in the same memory
address
Support for unaligned data:
The Data can be split into
many memory locations
long (32)
char (8)
long (32)
char (8) char (8) char (8)
Data
aligned
int (16)
long (32)
int (16)c
char (8)
long (32)
char (8)
long (32) …
… long
char (8) char (8) char (8)
int (16)
long (32) …
… long
int (16)c
char (8)
int (16)
long …
… long (32)
int (16)
long (32)
Unused (wasted) space
Fast Access (1 cycle) for all data
Free space for the rest of the application
Slow Access (2 cycles) for splitted Data
DAMERGI Emir – INSAT 2019
12
12
The Memory:
Chip Enable: when active (0), the Chip
« Memory » is enabled, else disabled
Control Bus:
/RD = Read
/WR = Write
Byte enable
/CE
/RD
/WR
Byte enable
An-1
n Address lines  Memory contains 2n words
m Data lines  m= Memory Data Width
A1
A0
Memory
Dm-1
D1
D0
The Memory Size : 2n * m/8 Bytes
DAMERGI Emir – INSAT 2019
13
The memory: Address Offset
Example: n =10, m = 32
Memory Size = 210* (32/4) Bytes = 1024 * 4 = 4096 Bytes
Each Byte in the memory has its own Address Offset*
Bytes in mem : Address Offset
4095
4094
4093
4092
…
…
7
6
5
4
3
2
1
0
M=32 (4 Bytes)
*) The effective address of a byte is defined relatively to the Processor Adress Space and may vary
DAMERGI Emir – INSAT 2019
14
The Memory: Chip Enable
0
/CE
Chip
Processor
When the Chip enable signal
is active (0)  the chip
outputs are connected to the
Data Bus.
DATA BUS
1
Processor
/CE
When the Chip enable signal
Chip
is inactive (1)  the chip
outputs
are
in
high
impedance state (tristate)
DATA BUS
=
Disconnected (elecrically)
from the Data Bus.
Chip : can be a memory or a peripheral interface
DAMERGI Emir – INSAT 2019
15
The Memory: Chip Enable
Processor
0
0
/CE0
/CE1
Chip 0
Chip 1
Di
Di
0
1
DATA BUS
0V
3,3V
If more than one chip can access (is connected to) the Data Bus:
Chip 0 writes ‘0’ (0V) on line Di
Chip 1 writes ‘1’ (+V = 3,3V) on line Di
 2 different electrical voltages on the same line : short Circuit
Chip : can be a memory or a peripheral interface
DAMERGI Emir – INSAT 2019
16
The Memory: Chip Enable
Processor
1
0
1
/CE
/CE
/CE
Chip
Chip
Chip
DATA BUS
Chip enable role :
At a given time a unique chip must be active (0), all others must be inactive (1).
Chip : can be a memory or a peripheral interface
DAMERGI Emir – INSAT 2019
17
Processor /Memory Interfacing:
Control Bus
A N-1
…
….
Processor
A0
D M-1
…
….
D0
A n-1
Address Bus
…
….
A0
Memory
D m-1
Data Bus
…
….
D0
To connect a processor to a memory (chip) , some conditions must be fullfilled:
• M = m  The Processor Data Size and Memory Data Width must be equal
• n <= N  The Memory Size <= Processor Addressing Capability.
DAMERGI Emir – INSAT 2019
18
Processor /Memory Interfacing:
Simplest Case: M = m and N = n
Memory Size (Bytes)
Proc. Addressing Capability
= 2n*m/8 = 2N * M/8
= 2N * M/8
/CE
A n-1
…
….
A0
A N-1
D m-1
…
….
Processor
Memory
…
….
A0
D0
D M-1
…
….
Memory width
=m=M
D0
Data Bus Size= M
DAMERGI Emir – INSAT 2019
19
Processor /Memory Interfacing:
Simplest Case: M=m and N=n
0
/CE
Control Bus
A N-1
…
….
Processor
A0
D M-1
…
….
D0
Address Bus
Data Bus
A n-1
…
….
A0
Memory
D m-1
…
….
D0
All N address lines must be tied together.
All M data lines must be tied together.
/CE can be set to ‘0’ (A unique Memory is connected to the
processor)
DAMERGI Emir – INSAT 2019
20
Processor /Memory Interfacing:
M=m and N=n
0
/CE
Control Bus
A N-1
A n-1
…
….
…
….
A0
A0
Processor
D M-1
D m-1
…
….
…
….
D0
Memory
D0
DAMERGI Emir – INSAT 2019
21
Processor /Memory Interfacing:
Case: N=n and M >m
Example : N = n =10 , M = 32 and m = 16
Memory Size =
Proc. Addr. Space : 0.. 4095
210 * 16/8 = 2048 bytes
A9
Processor
210 = 1024
…
….
A0
D 31
…
….
A9
…
….
A0
D15
210 = 1024
Proc. Addr. Capability : 4096 Byte
…
….
D0
D0
M = 32 bits
= 4 Bytes
M=32 ≠ m=16
m = 16 bits
= 2 Bytes
DAMERGI Emir – INSAT 2019
22
Processor /Memory Interfacing:
A9
…
….
2 Memories must be used
A0
Mem 1
D15
210 = 1024
N = n =10 , M = 32 and m = 16
…
….
A9
A9
…
….
A0
Processor
D 31
…
….
Mem 1
Mem 0
210 = 1024
…
….
A0
D15
Mem 0
210 = 1024
D0
…
….
D0
D0
m = 16 bits = 2 Bytes
M = 32 bits = 4 Bytes
DAMERGI Emir – INSAT 2019
23
Processor /Memory Interfacing:
Control Bus
A9
…
….
A0
Address Bus
0
0
/CE
/CE
A9
A9
…
….
A0
Mem 1
…
….
A0
Mem 0
Processor
D 31
…
D16
D15
…
D0
D 15
Data
Bus
…
….
D0
D 15
…
….
D0
DAMERGI Emir – INSAT 2019
24
Processor /Memory Interfacing:
A9
…
….
Processor
0
/CE
/CE
A9
A9
…
….
A0
A0
D 31
D 15
…
…
….
D16
0
D0
Mem 1
…
….
A0
Mem 0
D 15
…
….
D0
D15
…
D0
DAMERGI Emir – INSAT 2019
25
Processor /Memory Interfacing:
4095
4094
4093
4092
A9
A9
…
….
…
….
A0
…
…
11
10
9
8
D15
7
6
5
4
D0
3
2
1
0
…
….
Mem 1
A0
Mem 0
D15
7
3
6
2
2 Bytes
…
….
D0
5
4
1
0
210 = 1024
Processor
Byte Address
2 Bytes
Proc. Addr. Space :
0.. 4095
DAMERGI Emir – INSAT 2019
26
Processor /Memory Interfacing:
4 Memories must be used
A9
…
A9
Mem3
…
Mem2
A9
…
Mem1
A9
…
A0
A0
A0
A0
D7
D7
D7
D7
…
…
D0
D0
…
D0
Mem 0
210 = 1024
N = n =10 , M = 32 and m = 8
…
D0
m = 8 bits
= 1 Byte
A9
Mem 0
…
….
Mem 1
D 31
Mem 2
Processor
Mem 3
A0
210 = 1024
…
….
D0
M = 32 bits = 4 Bytes
DAMERGI Emir – INSAT 2019
27
Processor /Memory Interfacing:
Processor
A9
…
….
A0
0
0
0
0
/CE
/CE
/CE
/CE
Mem 3
Mem 2
Mem 1
Mem 0
A9
A9
A9
A9
…
….
…
….
…
….
A0
…
….
A0
D7
D7
D7
…
….
…
….
…
….
A0
D 31
D7
…
…
….
D24
D0
A0
D0
D0
D0
D23
…
D16
D15
…….
D8
D7
…
D0
DAMERGI Emir – INSAT 2019
28
…
A9
Mem3
…
…
D0
Processor
…
A0
A0
D7
A9
Mem2
7
D7
3
D0
…
A9
Mem1
…
A0
A0
D7
6
…
D0
2
Mem 0
5
D7
1
D0
…
4
0
Byte Address
4095
4094
4093
4092
…
…
11
10
9
8
7
6
5
4
3
2
1
0
210 = 1024
A9
210 = 1024
Processor /Memory Interfacing:
Proc. Addr. Space : 0.. 4095
DAMERGI Emir – INSAT 2019
29
Introduction:
A 32 bits data width memory can be constructed by association of
•
2 * 16 bits data width memory
•
4 * 8 bits data width memory
=
m = 32 bits
= 4 Bytes
+
m = 16 bits
= 2 Bytes
=
+
+
+
m = 8 bits
= 1 Byte
DAMERGI Emir – INSAT 2019
30
Processor /Memory Interfacing:
Example : N =10 and n=9 , M = 32 and m = 32
Proc. Addr. Capability : 4096 Bytes
Memory Size =
Proc. Addr. Space : 0.. 4095
210 = 1024 Words
A9
29 * 4 = 2048 bytes
…
….
A0
Processor
D 31
…
….
D0
M = 32 bits= 4 Bytes
?
A8
…
A
0
D31
…
D
M=32 =m
0
29 = 512 Words
Case: M = m and N>n
m = 32 bits
= 4 Bytes
Rq: n can be <N  It is not necesary to fill
completely the processor Address Space
DAMERGI Emir – INSAT 2019
31
Processor /Memory Interfacing:
Proc. Addr. Space : 0.. 4095 (4096 Bytes)
Address Offsets in Memory
4095
4094
4093
4092
…
….
…
…
…
…
…
…
2051
2050
2049
2048
2047
2046
2045
2044
..
..
..
..
…
…
..
4
3
2
1
0
2047
2046
2045
2044
…
..
..
4
3
2
1
0
…
29 = 512 Words
210 = 1024 Words
0..2047 (2048 Bytes)
m = 32 bits= 4 Bytes
M = 32 bits= 4 Bytes
Rq: n can be <N  It is not necesary to fill
completely the processor Address Space
DAMERGI Emir – INSAT 2019
32
Processor /Memory Interfacing:
• For N = 10 > n = 9 (m=M) : The Memory can be placed in one
of two possible address spaces : 0 ..2047 or 2048.. 4095.
• The First address where the Memory is placed is called :
Base Address (0 or 2048) .
• Each Byte in the Memory has an :
Address = Base Address + Address Offset
2047
2046
2045
2044
4095
4094
4093
4092
3
2
1
0
2051
2050
2049
2048
M=32 (4 Bytes)
M=32 (4 Bytes)
DAMERGI Emir – INSAT 2019
Processor /Memory Interfacing:
For N = 10 > n = 9 (m=M) :
•
The Data lines (D31..D0) must be connected together.
•
The common Address lines (A0 .. A8) must be connected together.
•
The remaining Address line(s) (A9) will be used to control the Memory /CE
signal and place the Memory in one of the 2 possible address spaces.
A9
A8
A8
Processor
…
….
…
….
A0
A0
D 31
…
….
D0
/CE
Control Bus
Data Bus
Memory
D 31
…
….
D0
DAMERGI Emir – INSAT 2019
Processor /Memory Interfacing:
To place the Memory in one of the 2 Address Spaces:
4095
A9
A8 A7 A6 A5 A4 A3 A2 A1A0
1
1
1 1 1 1
1 1 1 1
2048
1
0
0 0 0 0
0 0 0 0
2047
0
1
1 1 1 1
1 1 1 1
0
0
0
0 0 0 0
0 0 0 0
Addr. Space
A9
A8 ……..A0
0
0
x…….x
1
x…….x
.. 2047
2048 .. 4095
DAMERGI Emir – INSAT 2019
35
Processor /Memory Interfacing:
To place the Memory in one of the 2 Address Spaces:
0 .. 2047 : The Memory must be
active (/CE = 0) only when A9 =0.
Addr. Space
A9 A8 ……A0
0
1
.. 2047
2048 .. 4095
0
A9
/CE
0
0
1
1
/CE = A9
x……x
x……x
2048 .. 4095 : The Memory must be
active (/CE=0) only when A9=1.
A9
/CE
0
1
1
0
/CE = /A9
DAMERGI Emir – INSAT 2019
36
Processor /Memory Interfacing:
Memory placed in Address Space : 0 .. 2047 
/CE = A9
Control Bus
/CE
A9
Processor
A8
A8
…
….
…
….
A0
A0
D 31
…
….
D0
Data Bus
Memory
D 31
…
….
D0
• When the processor accesses Address Space 0 .. 2047, A9 =0 and /CE=0
 the memory is active.
• When the accessed address >2047, A9 =1 and /CE=1  The Memory is inactive
DAMERGI Emir – INSAT 2019
37
Processor /Memory Interfacing:
Memory placed in Address Space : 2048 .. 4095 
Control Bus
/CE = /A9
/CE
A9
Processor
A8
A8
…
….
…
….
A0
A0
D 31
…
….
D0
Data Bus
Memory
D 31
…
….
D0
• When the processor accesses the address space 0..2047, A9 =0 and /CE=/A9 = 1
 the memory is inactive.
• When the accessed address >2047, A9 =1 and /CE=1  The Memory is inactive
DAMERGI Emir – INSAT 2019
38
Processor /Memory Interfacing:
It is possible to use 2 Memories to fill completely the processor
4094
4093
4092
…
….
…
…
…
…
…
…
2051
2050
2049
2048
2047
2046
2045
2044
..
..
..
..
…
…
..
4
3
2
1
0
2047
/CE1 = /A9
2046
…
2044
Mem 1
…
..
..
3
2
1
0
2047
2046
2045
2044
…
/CE0 = A9
2045
Mem 0
…
..
..
3
2
1
0
29 =
512 Words
4095
29 =
512 Words
210 = 1024 Words
address space 0 .. 4095.
DAMERGI Emir – INSAT 2019
39
Processor /Memory Interfacing:
2 Memories with n bits address bus (9) can be associated to
A8
…
A0
n=9
=
512 Words
+
A8
…
A0
1024 Words
512 Words
construct a memory with n+1 bits address bus (10)
A9
…
….
n=10
A0
n=9
DAMERGI Emir – INSAT 2019
40
Processor /Memory Interfacing:
Processor
/CE0
Control Bus
Mem 0
A9
A8
…
….
A0
D 31
…
….
D0
Data Bus
/CE1
Mem 1
A8
A8
…
….
…
….
A0
A0
D 31
D 31
…
….
…
….
D0
D0
• When the processor accesses the address space 0..2047
 A9 = 0  /CE0 = A9 = 0 (Mem 0 enabled) & /CE1 = /A9 = 1 (Mem 1 disabled) .
• When the accessed address is in 2047..4095
 A9 = 1  /CE0 = A9 = 1 (Mem 0 disabled) & /CE1 = /A9 = 0 (Mem 1 enabled) .
DAMERGI Emir – INSAT 2019
41
Processor /Memory Interfacing:
•
For a processor with N address lines, a Memory with n address lines
(n<N) can occupy one of 2N/2n = 2(N-n) address Spaces *)
2(N-n) possible Address Spaces
•
The remaining (N-n) processor Address lines (An, An+1, …, AN-1) will be
used to control the /CE signal:
desired Address Space
AN-1
…….An+1
An
/CE
0
0 ….
0
1
0
0 ….
1
1
…….
0
1
*) M=m
1
1 ….
1
1
DAMERGI Emir – INSAT 2019
42
Processor /Memory Interfacing: Exercise
Example: A 32 bits processor with 10 bits Address Bus (N=10) and a
Memory with 8 addr. Lines (n=8) and 32 bits Data width.
A9
…
Processor
A0
D 31
…
D0
N=10
n=8
A7
….
A0
M=32
m=32
/CE
Memory
D 31
….
D0
1 – Is it possible to connect the Memory to the Processor?
Yes: The 2 conditions are :
•
M = m = 32 bits
•
N >=n  10> 8
DAMERGI Emir – INSAT 2019
43
Processor /Memory Interfacing: Exercise
2 – Give the Processor Addr. Capability, address space, and the
memory Size.
Proc. Addr capability = 210 * (32/8)
= 4096 Bytes
Memory Size = 28 * (32/8)
= 256 * 4
= 1024 Bytes
Proc Addr space = 0..4095
3 – Which address spaces could the Memory occupy?
The memory can occupy 2(N-n) = 2(10-8) = 22 = 4 Address spaces .
Each Address space is 4096/4 = 1024 Bytes long:
•
0
.. 1023
• 1024 .. 2047
• 2048 .. 3071
• 3072 .. 4095
DAMERGI Emir – INSAT 2019
44
Processor /Memory Interfacing: Exercise
4 – Give the Processor/Memory interfacing connections and
precise the /CE signal for each case (possible Address space).
•
Data lines connected.
•
Common Address lines connected: A0  A7
•
Remaining Proc. Address lines (A9 and A8 ) used to control /CE
A9
A8
Processor
Control Bus
A7
A7
…
….
A0
D 31
…
D0
/CE
A0
Data Bus
Memory
D 31
….
D0
DAMERGI Emir – INSAT 2019
45
Processor /Memory Interfacing: Exercise
4 – Give the Processor/Memory interfacing connections and precise
the /CE signal for each case (possible Address space).
/CE Truth Table
Addr. Spaces
A9 A8 A7 …A0
0 .. 1023
0
0
x…..x
3072 .. 4095
0
1
x…..x
2048 .. 3071
1
0
1023 .. 2047
1
1
Processor
A9
A8
A9 A8
0 ..
1023
1023..
2047
2048..
3071
3072..
4095
0
0
0
1
1
1
0
1
1
0
1
1
x…..x
1
0
1
1
0
1
x…..x
1
1
1
1
1
0
Control Bus
/CE
Memory
A7 .. A0
D32 .. D0
DAMERGI Emir – INSAT 2019
46
Processor /Memory Interfacing: Exercise
/CE Truth Table
4 – cont
A9 A8
Processor
0 .. 1023
1023 .. 2047
2048..3071
3072..4095
0
0
0
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
A9+A8
A9+/A8
A9
A8
Control Bus
/A9+A8
/A9+/A8
/CE
Memory
A7 .. A0
D32 .. D0
DAMERGI Emir – INSAT 2019
47
Processor /Memory Interfacing: Exercise
4 – Give the address spaces that the memory can occuupy and the
/CE signal for each case.
•
Data lines connected.
•
Common Address lines connected: A0  A7
•
Remaining Proc. Address lines (A9 and A8 ) used to control /CE
A9
A8
Processor
Control Bus
A7
A7
…
….
A0
D 31
…
D0
/CE
A0
Data Bus
Memory
D 31
….
D0
DAMERGI Emir – INSAT 2019
48
Processor /Memory Interfacing: Exercise
5 – How many memories must be used to fill completely the processor
address space? Give the proc/Memory Interface connections
I1 I0
• 4 Memories must be used : 4096/1024.
1 to 4 decoder
O0
O1
O2
O3
0
0
0
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
O0
Processor
A9
A8
I1
O1
I0
O2
O3
Control Bus
A7 .. A0
/CE3
/CE2
/CE1
/CE0
Mem 3
Mem 2
Mem 1
Mem 0
A7 .. A0
A7 .. A0
A7 .. A0
D32 .. D0
DAMERGI Emir – INSAT 2019
49
Processor /Memory Interfacing: Exercise
4 Memories with n bits address bus (8) can be associated to construct
A7
…
256
Words
+
A0
A7
…
256
Words
+
A0
A7
…
A0
n=8
n=8
n=8
=
1024 Words
256
Words
a memory with n+2 bits address bus (10)
A9
…
….
n=10
A0
256
Words
+
A7
…
A0
n=8
DAMERGI Emir – INSAT 2019
50
Processor /Memory Interfacing: Memories Association
2i Memories with n address lines can be associated to contruct a
Memory with (n+i) address lines:
+
=
+
=
+
+
DAMERGI Emir – INSAT 2019
51
Processor /Memory Interfacing: Memories Association
Memories can be associated to construct a Memory with a higher
Data Width and higher number of Address lines (Address Space)
+
+
=
+
+
DAMERGI Emir – INSAT 2019
52
Processor /Memory Interfacing: Memory Sticks
4 GB (1G * 32 bits) Memory Sticks are composed of
8 * 512 Mbytes Circuits
+
+
+
+
+
+
=
DAMERGI Emir – INSAT 2019
53
Memory Read/ Write
Operations
DAMERGI Emir – INSAT 2019
54
Processor/Memory Interfacing: Memory Read/Write Operations
When a variable is declared (example uint8_t var1)
 The compiler assigns a fixed address @ADR (in RAM)to the variable
 Each operation (Read or Write) on the variable is replaced by a
Memory Access operation
Write operation
Read operation
var1 = data;
…… = var1;
mov Rn, data
mov Rm, @ADR
mov Rm, @ADR
LDR Rn,[Rm]
STR Rn,[Rm]
Rn and Rm are processor Registers.
DAMERGI Emir – INSAT 2019
55
Processor /Memory Interfacing: Read Cycle
Read cycle triggered when instruction « LDR Rn,[Rm] » executed
Rm
DAMERGI Emir – INSAT 2019
56
Processor /Memory Interfacing: Read Cycle
To read Memory Address 06 = 110:
1) The processor activates Chip Enable (/CE) + READ (/RD) + sends (6=‘110’) on Address Bus
2) The memory content (Address 6= ‘110’) on Data Bus
Microprocesseur
/READ
0
0
WRITE
A2
A1
A0
/CE
Adresse
A2 A1 A0
/RD
1
1
1 (07)
1 1 0 1
1
1
0 (06)
11 0 00 11
1
0
1 (05)
0 1 0 0
1
0
0 (04)
1 1 0 0
WR
1
Contenu
D3 D2 D1 D0
1
A2
0
1
1 (03)
0 0 0 0
0
A1
0
1
0 (02)
1 0 0 0
A0
0
0
1 (01)
0 1 1 0
0
0
0 (00)
1 1 1 0
D3 D2 D1 D0
D3 D2 D1
D0
Bus de données
DAMERGI Emir – INSAT 2019
57
Processor /Memory Interfacing: Write Cycle
Write cycle triggered when instruction « STR Rn,[Rm] » executed
Rm
Rn
T cycle
DAMERGI Emir – INSAT 2019
58
Processor /Memory Interfacing: Write Cycle
To write Data ‘1111’ to memory address (6 = ‘110’)
1) The processor enables /CE and /WR Signals
2) The processor sends (6=‘110’) on Address Bus and Data=‘1111’ on Data Bus
0/CE
Microprocesseur
RD
READ
WRITE
0
A2
1
A1
1 1 1 1
D3 D2 D1 D0
A0
WR
A2
Adresse
A2 A1 A0
Contenu
D3 D2 D1 D0
1
1
1 (07)
1 1 0 1
1
1
0 (06)
1 0 0 1
1
0
1 (05)
0 1 0 0
1
0
0 (04)
1 1 0 0
1
1 (03)
0 0 0 0
1
A1
0
0
1
0 (02)
1 0 0 0
0
A0
0
0
1 (01)
0 1 1 0
0
0
0 (00)
1 1 1 0
Bus de données
D3 D2 D1 D0
DAMERGI Emir – INSAT 2019
Processor Interfacing: Peripheral Interfaces
•
Peripheral Interfaces are connected to the Processor through Address/Data
Busses. Exactly as the Memory.
Address Bus
Processor
Core
FLASH
RAM
Peripheral
Interface
i
Peripheral
interface
j
Data Bus
To periphs
•
the processor communicates with the peripherals through Peripheral Interfaces.
DAMERGI Emir – INSAT 2019
60
Processor Interfacing: Peripheral Interfaces
From Processor point of View: A Peripheral Interface is considered as
Memory, i.e a set of registers (with predefined addresses) that can be read
and written
Processor
READ
WRITE
AN-1
.
.
A0
RD
WR
AN-1
..
A0
DM DM-1… D0
Peripheral Interface
Register 2N-1
……..
Register 1
Register 0
DM-1 …………… D0
Data Bus
DAMERGI Emir – INSAT 2019
61
Processor Interfacing: Memory MAP
0x0000000
Register 1
FLASH
Register 2
0x00FF0000
Processor
Core
RAM
Peripheral
i
Peripherals
Peripheral
j
0xA000000
Register N
Each periph Register is
assigned a fixed address
DAMERGI Emir – INSAT 2019
62
Peripheral Interfaces
DAMERGI Emir – INSAT 2019
63
Processor Interfacing: Peripheral Interfaces
BUS
Internal Structure
Processor
Core
Config.
Registers
Status
Registers
Input Output
Registers
Digital Logic
Logic: could be simple (connections, Mux) or complex (SPP).
DAMERGI Emir – INSAT 2019
64
Processor Interfacing: Peripheral Interfaces
Some Bits of the Peripheral Interfaces are connected to external
connectors through SOC pins: they allow signals to flow from/to SOC
SOC pins
Peripheral Interface
b7
b6
b5
b4
b3
b2
b1
b0
Registre i
b7
b6
b5
b4
b3
b2
b1
b0
Registre i-1
DM-1 ……………
D0
DAMERGI Emir – INSAT 2019
65
Processor Interfacing: Peripheral Interfaces
Some Registers in Peripheral Interface can be configured in Input or output
The binary values written to registers  Voltage
• (+V = 3,3V/5V)  bit = ‘1’.
• (V = 0V)  bit = ‘0’.
Circuit d’interface
E/S
μP
READ
RD
WRITE
WR
+V
0V
1
0
1
1
0
0
AN-1
.
1 0 .
A0
AN-1
..
A0
b
b
b
b
b
b
b
b
7
6
5
4
3
2
1
0
Registre E/S
D7 D6… ..D0
D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
66
Processor Interfacing: Peripheral Interfaces
The Peripheral Interfaces Registers can be configured as INPUT (From Extern. Periph. To µp):
• V= 0V in Input  The read binary value is ‘0’
• V= 3,3V (5V) in Input  The read binary value is ‘1’
Circuit d’interface
E/S
0V
μP
RD
READ
WR
WRITE
0
X X X X X
AN-1
.
X 1 .
A0
D7 D6… ..D0
AN1
..
b
b
b
b
b
b
b
b
7
6
5
4
3
2
1
0
‘0‘
Registre E/S
+5V
‘1‘
A0 D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
67
Processor Interfacing: Periph. Register Programming
La programmation des interfaces d’E/S en langage ‘C’:
• Pour l’accès en écriture à un registre d’E/S :
#define Reg_name (type_data*) adr;
// Reg_name est un pointeur sur une donnée de type type_data occupant un espace mémoire
//commençant à l’adresse adr.
*Reg_name = valeur;
// Ecrire une valeur dans l’emplacement mémoire pointé par reg_name.
DAMERGI Emir – INSAT 2019
68
Processor Interfacing: Periph. Register Programming
La programmation des interfaces d’E/S en langage ‘C’:
• Pour l’accès en Lecture à un registre d’E/S :
#define Reg_name (type_data*) adr;
// Reg_name est un pointeur sur une donnée de type type_data occupant un espace mémoire
// commençant à l’adresse adr.
Variable = *Reg_name ;
// Lire le contenu de l’emplacement pointée par reg_name.
DAMERGI Emir – INSAT 2019
69
Processor Interfacing: Periph. Register Programming
Exemple1:
Un PC dispose d’un circuit d’interface E/S parallèle ‘8255’ contenant un registre 8 bits (Port A)
occupant l’ adresse 300 Hexa et connecté à 8 Diodes Leds (voir figure).
Ces Leds s’allument quand on leur applique V=+5V et s’éteignent quand on leur applique V = 0V.

Écrire un programme en ‘C’ qui permet de faire clignoter continuellement les 8 Leds.
(ne pas tenir compte de la configuration des pins du port)
8255
PA7
RD
μP
READ
WR
PA6
PA5
PA4
WRITE
A1
A0
D7 D6… ..D0
A1
A0
PA3
PA2
PA1
Led7
.
.
.
.
.
.
.
.
.
Led0
PA0
D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
70
Processor Interfacing: Periph. Register Programming
Commençons par modéliser le Fonctionnement du système par un diagramme:
Appliquer des ‘1’ à toutes
Les Leds pour les allumer.
Allumer les
Leds
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
1
1
1
1
1
1
1
1
F
Allumer les
Leds
F
= FF Hexa
Appliquer des ‘0’ à toutes
Les Leds pour les éteindre.
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
0
0
0
1
0
0
0
= 00 Hexa
DAMERGI Emir – INSAT 2019
71
Processor Interfacing: Periph. Register Programming
#define PortA (uint8_t*) 0x300;
// Répéter continuellement
While (1)
{
// Allumer les Leds
*PortA = 0x0FF;
// Éteindre les Leds
*portA = 0x00;
}
8255
μP
RD
READ
WR
WRITE
A1
A0
D7 D6… ..D0
Remarque: 0x est utilisé en ‘C’ pour
Indiquer les nombres hexadécimaux.
1
PA6
1
PA5
1
PA4
1
PA3
1
PA2
1
PA1
1
PA0
1
PA7
A1
A0
Led7
.
.
.
.
.
.
.
.
.
Led0
D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
72
Processor Interfacing: Periph. Register Programming
Le programme en ‘C’ :
#define PortA (uint8_t*) 0x300
// Répéter continuellement
While (1)
{
// Allumer les Leds
*PortA = 0x0FF;
// Éteindre les Leds
*portA = 0x00;
}
8255
PA7
μP
RD
READ
A0
D7 D6… ..D0
Remarque: 0x est utilisé en ‘C’ pour
Indiquer les nombres hexadécimaux.
PA5
WR
WRITE
A1
PA6
PA4
PA3
A1
PA2
PA1
A0
PA0
1
1
1
1
1
1
1
1
Led7
.
.
.
.
.
.
.
.
.
Led0
D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
73
Processor Interfacing: Periph. Register Programming
#define PortA (uint8_t*) 0x300;
// Répéter continuellement
While (1)
{
// Allumer les Leds
*PortA = 0x0FF;
8255
0
PA6
0
PA5
0
PA4
0
PA3
0
PA2
0
PA1
0
PA0
0
PA7
// Éteindre les Leds
*portA = 0x00;
}
μP
RD
READ
WRITE
A1
A0
D7 D6… ..D0
Remarque: 0x est utilisé en ‘C’ pour
Indiquer les nombres hexadécimaux.
WR
A1
A0
1
1
1
1
1
1
1
1
Led7
.
.
.
.
.
.
.
.
.
Led0
D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
74
Processor /Memory Interfacing:
#define PortA (uint8_t*) 0x300;
// Répéter continuellement
While (1)
{
// Allumer les Leds
*PortA = 0x0FF;
// Éteindre les Leds
*portA = 0x00;
}
8255
PA7
μP
RD
READ
A0
D7 D6… ..D0
Remarque: 0x est utilisé en ‘C’ pour
Indiquer les nombres hexadécimaux.
PA5
WR
WRITE
A1
PA6
PA4
PA3
A1
A0
PA2
PA1
PA0
0
0
0
0
0
0
0
0
Led7
.
.
.
.
.
.
.
.
.
Led0
D7 …. …………… D0
Bus de données
DAMERGI Emir – INSAT 2019
75
Processor Interfacing: Periph. Register Programming
Exemple2: Un PC dispose d’un circuit d’interface E/S parallèle ‘8255’ contenant un registre 8 bits
(noté port C) occupant l’ adresses 30E Hexa et connecté à un afficheur 7 segments (voir figure).
Chacun des segments s’allume quand on lui applique +5V et s’éteint quand on lui applique 0V.
 De telle sorte à pouvoir afficher n’importe quel nombre entre 0 et 9.

Écrire un programme en ‘C’ qui permet d’afficher ‘3’. (ne pas tenir compte de la configuration)
8255
μP
RD
READ
WR
WRITE
A1
A1
A0
A0
PC7
a
PC6
b
PC5
c
PC4
d
PC3
e
PC2
f
PC1
g
PC0
h
D7 D6… ..D0
D7 …. …………… D0
Bus de données
a
f
b
g
e
c
d
h
DAMERGI Emir – INSAT 2019
76
Processor Interfacing: Periph. Register Programming
Commençons par modéliser le fonctionnement
du système par un diagramme:
PC7
a
PC6
b
PC5
c
PC4
d
PC3
e e
PC2
f
PC1
g
PC0
h
a
f
Mettre à ‘1’ les segments
devant être allumés
b
g
c
d
h
Afficher ‘3’
 Allumer les
Segments:
a, b, c, d et g
PC7
PC6
PC5
PC4
(a)
(b)
(c)
1
1
1
F
PC2
(f)
PC1
(d)
PC3
(e)
(g)
PC0
(h)
1
0
0
1
0
2
= F2 Hexa
DAMERGI Emir – INSAT 2019
77
Processor Interfacing: Periph. Register Programming
#define PortC (uint8_t*) 0x30E;
// Allumer les segments a,b,c,d & g
*PortC = 0x0F2;
8255
1
PC6
1
PC5
1
PC4
1
PC3
0
PC2
0
PC1
1
PC0
0
PC7
RD
WR
A1
A0
a
a
b
c
f
d
e
b
g
e
c
f
g
d
h
h
D7 …. …………… D0
DAMERGI Emir – INSAT 2019
78
Processor Interfacing: Periph. Register Programming
#define PortC (uint8_t*) 0x30E;
// Allumer les segments a,b,c,d & g
*PortC = 0x0F2;
8255
PC7
RD
PC6
PC5
WR
A1
A0
PC4
PC3
PC2
PC1
PC0
1a
1b
1c
1d
0e
0f
1g
0h
a
f
b
g
e
c
d
h
D7 …. …………… D0
DAMERGI Emir – INSAT 2019
79
Processor Interfacing: Periph. Register Programming
8255
PA7
μP
RD
READ
PA1
WR
WRITE
A1
A1
A0
A0
D7 D6… ..D0
…
PA0
Led1
Led0
PC7
…
PC1
PC0
D7 …. …………… D0
Bus de données
BP1
BP0
Un bouton poussoir génère
0V au repos et +5V quand
il est appuyé
DAMERGI Emir – INSAT 2019
80
Processor Interfacing: Periph. Register Programming
Commençons par modéliser le
Fonctionnement du système par
un diagramme:
Configurer
l’interface 8255
Lire Etat BPs
 Lire Port C
PC7
Sinon
Appui BP0
PC6
PC5
PC4
PC3
PC2
BP1
BP0
PC1
PC0
Appui BP0
0
1
Appui BP1
1
0
= 01 Hexa
= 02 hexa
Appui BP1
Allumer
Led 0
Allumer
Led 1
Éteindre
Leds
Led1
Led0
PA1
PA0
Allumer Led0
0
1
Allumer Led1
1
0
Éteindre Leds
0
0
PA7
PA6
PA5
PA4
PA3
PA2
= 01 H
= 02 H
= 00 H
DAMERGI Emir – INSAT 2019
81
Processor Interfacing: Periph. Register Programming
Le programme en ‘C’:
// Déclaration des pointeurs
#define PortA (uint8_t*) 0x300;
#define PortC (uint8_t*) 0x30E;
Lire Port C
(30Eh)
Uint8_t etat_bouton; // variable 8 bits
Sinon
Port C = 01 h
Port C = 02 h
Port A (300h)
= 01 h
Port A (300h) Port A (300h)
= 02 h
= 00 h
// Lire État des Boutons Poussoir (Port C)
etat_bouton = * portC ;
// Test et traitement
switch (etat_bouton)
{
case 0x01: *portA = 0x01;
case 0x02: *portA = 0x02);
default
: *portA = 0x00);
}
DAMERGI Emir – INSAT 2019
82
Processor Interfacing: Periph. Register Programming
Dans la solution proposée, on a testé juste les
valeurs 01 et 02 H en supposant que les autres
Valeurs sont à 0.
Lire Port C
(30Eh)
Port C = 01
h
Sinon
Port C = 02
Port A (300h)
= 01 h
h
Port A (300h) Port A (300h)
= 02 h
= 00 h
Ceci n’est pas vrai car les autres entrées du port C
peuvent prendre des valeurs aléatoires inconnues
PC7
PC6
PC5
?
PC4
PC3
PC2
PC1
BP1
PC0
BP0
DAMERGI Emir – INSAT 2019
83
Téléchargement
Random flashcards
Ce que beaucoup devaient savoir

0 Cartes Jule EDOH

Le lapin

5 Cartes Christine Tourangeau

aaaaaaaaaaaaaaaa

4 Cartes Beniani Ilyes

découpe grammaticale

0 Cartes Beniani Ilyes

Fonction exponentielle.

3 Cartes axlb48

Créer des cartes mémoire