02 IO Peripheral Interfaces

Processor Interfacing
Emir DAMERGI
INSAT 2018/19

DAMERGI Emir – INSAT 2019
Introduction:
2
Processor Memory
Data Bus
Address Bus
Control Bus
In processor based systems (Computers, Embedded systems), the processor is
connected to Memory through :
• Control Bus:
• Address Bus:
• Data Bus:

DAMERGI Emir – INSAT 2019
The processor: Busses
3
Processor
/ RD
/ WR
A0
A1
AN-1
D0
D1
DM-1
Address Bus:
N Address lines = Address bus size
The processor can address up to 2NWords.
Byte Enable
Control Bus:
/RD = Read When active (0), the Processor
reads from Memory.
/WR = Write When active (0), the processor
writes to Memory.
Byte enable: A group of lines that indicate the
nbr of bytes to read.
Data Bus:
M data lines = Data Bus size = Word Size
(8, 16, 32 , 64 bits)

DAMERGI Emir – INSAT 2019
The Processor : Data Size
4
Processor
/ RD
/ WR
A0
A1
AN-1
D0
D1
DM-1
Byte enable
Data Bus:
M data lines = Data Bus size = Word Size
(8, 16, 32 , 64 bits)
32 bits Processors are processors
with 32 bits data bus
For 32 bits processors:
•Word = 32 bits
•Halfword = 16 bits
•Doubleword = 64 bits

DAMERGI Emir – INSAT 2019
The Processor: Addressing Capabilty/Space
5
Processor
/RD
/WR
A0
A1
AN-1
D0
D1
DM-1
Processor Addressing Capabilty =
2N * Words = 2N *M/8 Bytes
(expressed in Bytes)
Byte enable
1KByte =210 , 1MByte = 220 and 1GByte = 230
Processor Address Space :
0 -> (2N *M/8) – 1
0 Addr Capability (in Bytes)