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Descriptif de Formation - Ref:004837A - 25/05/2017 ARM Cortex R4/Cortex R4F - Conception système 4 jours OBJECTIFS Cette formation traite en détails les particularités des cœurs ARM, aussi bien logiciel que matériel dans le but de facilité la mise en oeuvre de cœurs Cortex-R4. Elle est destiné aux : Ingénieurs logiciel qui veulent non seulement obtenir des détails sur la façon d’écrire un logiciel pour processeur ARM Cortex-R4, mais qui souhaitent également comprendre l’implémentation matériel des cœurs au sein d’un microcontrôleur Ingénieurs matériel qui ont besoin de comprendre comment concevoir des systèmes basés sur ARM PRÉREQUIS Une compréhension de base des microprocesseurs et microcontrôleurs est utile mais non indispensable Cortex-R4 mais également être capable de comprendre Une compréhension de base de la logique numérique est utile les bases de la programmation logicielle sur ces plates- mais non indispensable formes Une compréhension de base de la programmation en assembleur ou en langage C est utile mais non indispensable Des notions sur les cœurs ARM sont utiles mais non FORMATIONS CONNEXES ARM Cortex R5 - Conception système indispensables CONFIGURATIONS ARM Cortex M4 - Conception système Pour les formations sur site, les travaux pratiques peuvent être effectués sous les environnements suivants : Keil DS-5, Keil PARTENAIRES µVision, ou IAR Workbench Thumb-2 instruction set CHAPITRES Program Status register Exceptions INTRODUCTION TO CORTEX-R4 System control coprocessor Block diagram Configurable options Highlighting the new features with regard to other ARM cores THUMB-2 INSTRUCTION SET ARMv7-R architecture Introduction Operating modes General points on syntax ARM instruction set Data processing instructions MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France Tel : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-training.com SIRET : 510 766 066 00029 - Identifiant TVA : FR 74510766066 - NAF : 8559A Déclaration d’activité enregistrée sous le n° 73 3105366 31 auprès du Préfet de région de Midi-Pyrénées 1 Descriptif de Formation - Ref:004837A - 25/05/2017 Branch and control flow instructions Instruction cycle timing Memory access instructions Dynamic branch prediction mechanism : global history buffer Exception generating instructions Guidelines for optimal performance If...then conditional blocks Data Processing Unit Stack in operation Dual issue conditions Exclusive load and store instructions Return stack Accessing special registers Instruction Memory Barrier Coprocessor instructions Prefetch queue flush Memory barriers and synchronization PMU related events Interworking ARM and Thumb states MEMORY TYPES Demonstration of assembly sequences aimed to understand this Memory types, restriction regarding load / store multiple new instruction set Device and normal memory ordering VFPV3 FLOATING POINT UNIT Memory type access restrictions Floating point number encoding (normalized, tiny, zero, infinite, Access order NAN) Memory barriers, self-modifying code Overview of VFPv3-D16 architecture MEMORY PROTECTION UNIT General purpose registers, FPU views of the register bank Memory protection overview, ARM v7 PMSA Compliance with IEEE754 standard Cortex-R4 MPU and bus faults Exception management Fault status and address registers NaN handling Region overview, memory type and access control, sub-regions Demonstration of floating point calculations generated from C Region overlapping language Setting up the MPU COMPILER HINTS AND TIPS EXCEPTION MANAGEMENT Automatic optimization Low Interrupt Latency : abandoning load / store instructions in Instruction scheduling progress Tail-call optimization Configuring the state in which exceptions are handled : endian Parameter passing mode, instruction set Array and structure access Configuring the FIQ as non-maskable Loop termination Primecell VICs Inline assembler Reducing interrupt latency through automatic vector generation Stack usage VIC basic signal timing Global data layout Connectivity : daisy-chained VIC Highlighting some optimisations through practical labs, for Interrupt priority and masking instance tail-call optimization Abort exception, fault handling EMBEDDED SOFWARE DEVELOPMENT Determining the cause of the fault through CP15 status registers ROM/RAM remapping Precise vs imprecise faults Exception vector table HARDWARE IMPLEMENTATION Reset handler Clock domains, CLKIN, FREECLKIN and PCLKDBG Initialization : stack pointers, code and data areas Using clock enable to determine the ratio between input clock and C library initialization operation clock Scatterloading Reset domains, power-on reset and debug reset Linker placement rules Power control, dynamic power management Long branch veneers Wait For Interrupt architecture C library functionality Debugging the processor while powered down Placing the stack and heap AXI PROTOCOL INSTRUCTION PIPELINE Topology : direct connection, multi-master, multi-layer Prefetch unit PL300 AXI interconnect Studying how instructions are processed step by step Separate address/control and data phases MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France Tel : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-training.com SIRET : 510 766 066 00029 - Identifiant TVA : FR 74510766066 - NAF : 8559A Déclaration d’activité enregistrée sous le n° 73 3105366 31 auprès du Préfet de région de Midi-Pyrénées 2 Descriptif de Formation - Ref:004837A - 25/05/2017 AXI channels, channel handshake AXI slave interface, write issuing capability, read issuing capability Support for unaligned data transfers Enabling or disabling AXI slave accesses Transaction ordering, out of order transaction completion Using chip-select to distinguish A-TCM, B-TCM, I-Cache and D- Read and write burst timing diagrams Cache accesses Atomic transactions Using the AXI slave interface to perform built-in self tests Understanding the error recovery mechanisms LEVEL 1 MEMORY SYSTEM Cache basics : organization, replacement algorithm, write policies Exclusive accesses, swap instructions, internal exclusive monitor, Cache organization requirement of an external exclusive monitor when implementing Write with allocate policy multiple cores APB - ADVANCED PERIPHERAL BUS Debugging when caches are active Second-level address decoding Parity / ECC protection Understanding transient cache line load / store : linefill buffers, eviction buffer Accessing the cache RAM from AXI slave interface Tightly Coupled Memories, address decoding, enabling on reset ECC/parity protection Interleaving BTCM accesses initiated by core and AXI DMA connected to AXI slave interface Pinout Read timing diagram Write timing diagram APB3.0 new features DEBUG UNIT Performance monitor, event counting Related interrupts, event bus Coresight specification overview Store buffer, merging data CP14 and memory-mapped registers, utilization of an APB slave L1 caches software read for debug purposes PMU related events interface APB port access permissions LEVEL 2 MEMORY SYSTEM Embedded core debug AXI master interface, write issuing capability, read issuing Invasive debug : breakpoints and watchpoints capability Vector catch AXI transaction identifiers Debug exception Controlling an external cache Debug Communication Channel Restrictions on AXI transfers External debug interface Determining the number and type of AXI transactions according to Understanding how the Debug unit, the Embedded Trace memory attributes and instruction type Macrocell and the Cross-Triggering Interface interact AXI transaction splitting Debugging systems with energy management capabilities NOTES Les supports de cours seront fournis sur papier à chaque participant pendant la formation CONTACT Tel : 05 62 13 52 32 Fax : 05 61 06 72 60 [email protected] MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France Tel : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-training.com SIRET : 510 766 066 00029 - Identifiant TVA : FR 74510766066 - NAF : 8559A Déclaration d’activité enregistrée sous le n° 73 3105366 31 auprès du Préfet de région de Midi-Pyrénées 3
