D - Free

ISEN
2006
COURS DE DSP
(Digital Signal Processor)
Partie 2: architecture
Alain Fruleux
1- DEVELOPPEMENT A PARTIR DE DSP.
 1.1 Du µP au DSP Quelle famille!!!


µP Microprocesseurs
µC Microcontrôleurs
DSP Digital Signal Processeur

Risc/Cisc…..8/16/32/64 bits

1.1.1 µprocesseur story
1.1.2 Spécificités du DSP (MAC)
1+2 = 3
Add
0001
+
0010
Multiply
0
1
0
1
x
x
x
x
5
Shifted and
added
multiple times
0011
Most Common Operation in DSP
A = B*C + D
E = F*G + A
..
.
Multiply, Add, and Accumulate
MAC Instruction
8
4
2
1
x
x
x
x
5*3 = 15
0011
0011
0011
0011
3
0000
0011
0000
0011
=
MAC Operation
Typically 70 Clock Cycles With
Ordinary Processors
Typically 1 Clock Cycle With
Digital Signal Processors
2 - Structure d ’un Système à DSP (µP)
 2-1 Vision Globale du DSK/TMS320C5510 de TI
 2-2 Architecture d ’une carte DSP
 2-3 Voyage au centre du DSP
 et parallélisme

2-0 Vision Globale DSK/TMS320c5510 de
TI
?
?
?
?
?
2-1 Vision Globale DSK/TMS320c5402 de TI
2-3 ARCHITECTURE D ’UNE CARTE µP
 2-3-1 Structure Générale/BUS
µP ou DSP

2-3 ARCHITECTURE D ’UNE CARTE µP
 2-3-2 BUS de données (exemple sur 8 bits)
0= 0v
1= 5v (..)
tristate= rien
ou haute impédance
 2-3-3 BUS d ’Adresses (exemple sur 3 bits)
2-3-4 Mapping Mémoire
Organisation de la mémoire du TMS320C5510

0000h
2-4-3 Wait states
2-4-5 Temps pris par une instruction

portw
*(a), 0h
p nombre de cycles d ’horloge pour waitstates mémoire programme
d nombre de cycles d ’horloge pour waitstates mémoire données
io nombre de cycles d ’horloge pour waitstates mémoire i/o

2-3-5 Architectures d’un Calculateur (source TI)
Von Neuman Machine
A
STORED
PROGRAM
AND
DATA
D
INPUT/
OUTPUT
ARITHMETIC
LOGIC
UNIT
A = ADDRESS
D = DATA
Harvard Architecture
A
A
ARITHMETIC
LOGIC
UNIT
STORED
PROGRAM
D
INPUT/
OUTPUT
STORED
DATA
D
2-4 Voyage au centre du DSP 54x
Program address generation
logic (PAGEN)
System control
interface
Data address generation
logic (DAGEN)
ARAU0, ARAU1
AR0-AR7
ARP, BK, DP, SP
PC, IPTR, RC,
BRC, RSA, REA
PA
B
P
B
Memory
and
external
interface
CA
B
C
B
DA
B
Peripheral
interface
D
B
EA
B
E
B
EXP
encoder
X
D
A
B
MUX
T register
T D A
A P C D
Sign ctr
T A B C
A(40)
Sign ctr
Multiplier (17 y 17)
A
Fractional
MUX
Adder(40)
ZERO
SAT
ROUND
Sign ctr
B A C D
S
Sign ctr
Sign ctr
MUX
0
B
B(40)
D
Barrel
shifter
ALU(40)
A
MU B
A
Legen
d: A Accumulator A
B Accumulator B
C CB data bus
D DB data bus
E EB data bus
M MAC unit
P PB program bus
S Barrel shifter
T T register
U ALU
B
MUX
S
COM
P
TR
N
T
C
MSW/LSW
select
E
C54x Architecture
Data Read A/D Bus (C)
Program A/D Bus (P)
Data Read A/D Bus (D)
PC
XPC
MAC
DP
@x2
Addr
Gen
ALU
AR0-7
Decode
A
B
Data Write A/D Bus (E)
MAC *AR2+, *AR3+, A
ADD @x2, B ...
4
2-4-1 ALU/Registres et bus internes
CB15 - CB0
DB15 - DB0
T
A
40
B T
C
D
SXM
A
MUX
MUX
Sign ctr
Sign ctr
X
Y
B
ACC
ALU
MUX
40
40
A
MAC
output
S
Shifter output (40)
40
M
U
B
40
SXM
OVM
C16
C
OVA/OVB
ZA/ZB
TC
Legend:
A Accum ulator A
B Accum ulator B
C CB data bus
D DB data bus
M MAC unit
S Barrel shif ter
T T register
U ALU
C5510 Architecture
2-4-2 Pipe-Line C5402
Loads PAB with
the PC's contents
Prefetch
Loads IR with the contents
of PB
Decodes the IR's contents
Fetch
Loads PB with the
fetched instruction
word
Decode
Loads DB with the data1
read operand
Loads CB with the data2
read operand
Loads EAB with the data3
write address, if required
Access
Loads DAB with the data1 read
address, if required
Loads CAB with the data2 read
address, if required
Updates auxiliary registers and
stack pointer
Time
Read
Execute/write
Executes the instruction
and loads EB with write
data
C54x Pipeline
Program A/D Bus (P)
Internal
Data Read A/D Bus (D)
Memory
Data Read A/D Bus (C)
Ext’l
Mem
I/F
A
D
External
Memory
Data Write A/D Bus (E)

Internal: Up to 4 accesses / cycle


Pipeline Phases
P - generate program address
F - get opcode
D - decode instruction
A - generate read address
R - read operands
X - execute
P F D A
P F D
P F
P
Full Pipeline
External: 1 access / cycle
up to 8M words program
R
A
D
F
P
X
R
A
D
F
P
X
R
A
D
F
X
R X
A R X
D A R X
6